JPS5853251A - Transmission system - Google Patents

Transmission system

Info

Publication number
JPS5853251A
JPS5853251A JP15125181A JP15125181A JPS5853251A JP S5853251 A JPS5853251 A JP S5853251A JP 15125181 A JP15125181 A JP 15125181A JP 15125181 A JP15125181 A JP 15125181A JP S5853251 A JPS5853251 A JP S5853251A
Authority
JP
Japan
Prior art keywords
address
protection code
transmission
frame
incoming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15125181A
Other languages
Japanese (ja)
Inventor
Takane Kakuno
覚「野」　高音
Mitsuhiro Ishizaka
石坂　充弘
Shigeo Nakatsuka
中塚　茂雄
Tachiki Ichihashi
市橋　立機
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP15125181A priority Critical patent/JPS5853251A/en
Publication of JPS5853251A publication Critical patent/JPS5853251A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3226—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using a predetermined code, e.g. password, passphrase or PIN

Abstract

PURPOSE:To prevent the leakage of a secret, by putting a protection code into a signal frame to protect an incoming address and giving permission only to a transmitter having a protection code made coincident with the contents of the above-mentioned protection code for fetching of the frame. CONSTITUTION:Now a transmitter ST3 is operated wrong in terms of its address to have the same address as a transmitter ST2. In such case, the ST3 fetches a frame on a transmission line 1 like the ST2. Then the ST3 sets a protection code, an incoming address and an outgoing address to a protection code register PCRG, an incoming address register DARG and an outgoing address register SARG respectively to compare them with corresponding codes of is own station. Then the corresponding protection code of a memory RAM is read out with the originating address of the register SARG used as an address and compared with the above-mentioned protection code through a protection code comparator COMP2. Then no coincidence is obtained from the comparison, and an AND gate is closed to give no indication of reception to a common control part COM.

Description

【発明の詳細な説明】 本発明は伝送システムに係り、複数の伝送装置を共通の
伝送路により接続し、任意の伝送装置間で伝送されるデ
ータの機密保持ができるようにした伝送システムに関す
る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a transmission system, and more particularly, to a transmission system in which a plurality of transmission devices are connected through a common transmission path and data transmitted between arbitrary transmission devices can be kept confidential.

第１図は伝送システム一般の構成例を示す図であり、１
は伝送路、ＳＴＩ　、ＳＴ２　、ＳＴ３　、・・。FIG. 1 is a diagram showing an example of the configuration of a general transmission system.
are transmission lines, STI, ST2, ST3,...

ＳＴｎ等の各ＳＴは伝送路１を介して任意の相手局とデ
ータ伝送を行なう伝送装置である。０ＰＵＩ　。Each ST such as STn is a transmission device that performs data transmission with an arbitrary partner station via the transmission path 1. 0PUI.

０ＰＵ２　、　ＣＰＵ３、−．０ＰＵｎ等の各ＣＰＵは
添字の対応する伝送装置ＳＴにデータ伝送の指示などを
行なう計算機である。0PU2, CPU3, -. Each CPU such as 0PUn is a computer that instructs the transmission device ST with the corresponding subscript to transmit data.

第２図は従来のフレーム構成例を示す図、第３図は従来
の伝送装置の構成例を示す図である。FIG. 2 is a diagram showing an example of a conventional frame structure, and FIG. 3 is a diagram showing an example of the structure of a conventional transmission device.

第２図中、１０はフレーム、１１はフレーム１０の先頭
を示すリーディングフラグ、１２はフレーム１０の最後
を示すエンドフラグ、１３は着信アドレス、１４は発信
アドレス、１５はコマンド、１６はインフォメーション
、１７は誤り検査コードである。In FIG. 2, 10 is a frame, 11 is a leading flag indicating the beginning of frame 10, 12 is an end flag indicating the end of frame 10, 13 is an incoming address, 14 is an outgoing address, 15 is a command, 16 is information, 17 is the error checking code.

第３図中、Ｒは受信器、Ｔは送信器、Ｒ−８ＨＦは受信
直並列変換器、Ｓ−８ＨＦは送信直並列変換器、ＡＤＳ
Ｗは伝送システトのアドレスを設定するアドレススイッ
チであり、伝送装置ＳＴの前面パネル等に設けである。In Figure 3, R is a receiver, T is a transmitter, R-8HF is a receiving serial-to-parallel converter, S-8HF is a transmitting serial-to-parallel converter, and ADS
W is an address switch for setting the address of the transmission system, and is provided on the front panel of the transmission device ST.

ＤＡＲＧは受信した着信アドレス１３をセットする着信
アドレスレジスタである。ＯＯＭＰＩは受信フレーム１
０の着信アドレス１３と自局のアドレススイッチＡＤＳ
Ｗの設定値とを比較するアドレス検定回路上してのアド
レス比較器、ＲＢＵＦは受信データを格納する受信デー
タバッファ、５ＢＵＦは計算機ＣＰＵの指示により送信
するデータを格納する送信データバッファ、１００は誤
り検出回路、ＣＯＭは伝送装ＭＳＴ全体を制御する共通
制御部、ＩＮＦは引算機ＣＰＵとの３− インタフェース部である。DARG is a destination address register in which the received destination address 13 is set. OOMPI is received frame 1
0's incoming address 13 and own address switch ADS
An address comparator on the address verification circuit that compares the setting value of W, RBUF is a reception data buffer that stores received data, 5BUF is a transmission data buffer that stores data to be transmitted according to instructions from the computer CPU, and 100 is an error. The detection circuit COM is a common control unit that controls the entire transmission device MST, and INF is a 3-interface unit with the subtraction machine CPU.

通常伝送装置ＳＴＩ　、ＳＴ２．８Ｔ３、−　、ＳＴｎ
のアドレススイッチＡＤＳＷは夫々“１ｎ、ｗ２ｍ。Normal transmission equipment STI, ST2.8T3, -, STn
The address switches ADSW are "1n, w2m," respectively.

“３”、・　、′ｎ”というように伝送システム内で一
意の値が設定される。Unique values are set within the transmission system, such as "3", . . . 'n'.

伝送路１を流れるフレーム１０は、各伝送装置ＳＴのア
ドレス比較器００ＭＰ１により、着信アドレス１３と自
局のアドレススイッチＡＤＳＷの設定値が比較されて一
致すると自局宛のフレームであると認められ、受信デー
タバッファＲＢ　Ｕ　Ｆに取り込まれ、誤り検出回路１
００でビットエラーが検出されなければ、インタフェー
ス部ＩＮＦを介して計算機ＣＰＵに転送される。The frame 10 flowing through the transmission path 1 is compared by the address comparator 00MP1 of each transmission device ST with the incoming address 13 and the setting value of the address switch ADSW of the own station, and if they match, it is recognized as a frame addressed to the own station, It is taken into the reception data buffer RBUF and sent to the error detection circuit 1.
If no bit error is detected at 00, the data is transferred to the computer CPU via the interface unit INF.

今、伝送装置ＳＴ３のアドレススイッチＡ、ＤＳＷが、
誤まって或いは故意に伝送装置ＳＴ２のアドレススイッ
チＡＤＳＷと同一の値に設定されたとする。この場合、
上述した如くフレーム１０の着信アドレス１３と自局の
アドレススイッチＡＤＳＷの１１′・。Now, the address switch A and DSW of the transmission device ST3 are
Suppose that it is set to the same value as the address switch ADSW of the transmission device ST2, either by mistake or intentionally. in this case,
As mentioned above, the incoming address 13 of the frame 10 and the address switch ADSW 11' of the own station.

設定値とをアドレス叱較器００ＭＰ１で比較し、一致す
ると受信するため、本来伝送装置ＳＴ”２にの＝４− み送られたデータが、伝送装置ＳＴ３においても受信で
きることになってしまう。The set value is compared with the address comparator 00MP1, and if they match, the data is received. Therefore, the data that was originally sent to the transmission device ST"2 can also be received by the transmission device ST3.

このため、この種の従来の伝送装置ＳＴを用いた伝送シ
ステムは、伝送装置ＳＴのパネル等に設けられたアドレ
ススイッチＡＤＳＷの値を変更することで、簡単に他局
宛のデータを傍受することが可能であり、機密が漏洩し
やすい等の欠点があった。特に艦船等に搭載された機器
を結ぶシステムにおいては、このような欠点は重大問題
であった。Therefore, in a transmission system using this type of conventional transmission device ST, data destined for another station can be easily intercepted by changing the value of the address switch ADSW provided on the panel of the transmission device ST. However, there were drawbacks such as the possibility of leakage of confidential information. These shortcomings were a serious problem, especially in systems that connect equipment mounted on ships and the like.

本発明は上記従来の欠点を除去したものであり、フレー
ム内に着信アドレスを保護する保護コードを設け、この
保護コードの内容と一致する保護コードをもつ伝送装置
のみが伝送路を流れるフレームを取り込めるようにし、
機密の漏洩を防止するようにした伝送システムを提供す
ることを目的とする。The present invention eliminates the above-mentioned drawbacks of the conventional technology. A protection code is provided in the frame to protect the incoming address, and only a transmission device with a protection code that matches the contents of the protection code can capture the frame flowing through the transmission path. So,
The purpose of the present invention is to provide a transmission system that prevents leakage of confidential information.

以下、本発明の一実施例につき第４図以下を参照して説
明する。・π４図は本発明になる伝送システムを適用し
たフレームの構成例を示す図、第５図は本発明になる伝
送システムに用いた伝送装置の構成例を示す図である。Hereinafter, one embodiment of the present invention will be described with reference to FIG. 4 and subsequent figures. - π4 diagram is a diagram showing an example of the configuration of a frame to which the transmission system according to the present invention is applied, and FIG. 5 is a diagram showing an example configuration of a transmission device used in the transmission system according to the present invention.

第４図中、１８は保護コードである。本例では、保護コ
ード１８の値が零のときには、各伝送装置ＳＴは着信ア
ドレス１３と自局のアドレススイッチＡＤＳＷの設定値
との一致のみで７レーム１９を爪−４→４４、保護コー
ド１８の値が 零μ外の場合には、自局の保持する保護コードとフレー
ム１９内の保護コードＰＣが一致し、かつ着信アドレス
１３が自局アドレスと一致したときにのみフレーム１９
を受信する。In FIG. 4, 18 is a protection code. In this example, when the value of the protection code 18 is zero, each transmission device ST transfers the 7 frames 19 from -4 to 44 and the protection code 18 only by matching the incoming address 13 with the setting value of the address switch ADSW of its own station. If the value of is outside of zero μ, frame 19 is sent only when the protection code held by the own station matches the protection code PC in frame 19, and the incoming address 13 matches the own address.
receive.

第５図中、ＰＣＲＧは受信フレーム１９の保護コード１
８をセットする保護コードレジスタ、５ＡＲＧは発信ア
ドレス１４をセットする発信レジスタ、ＺＤＥＯは保護
コード１８の値が零であることを検出する零検出回路、
ＲＡＭは自局と論理的に接続される他局間の保護コード
を格納しておくメモリ、００ＭＰ２はフレーム１９内の
保護コード１８とメモＩＪＲＡＭに格納されている自局
関連の保護コードとを比較する保護コード検定回路とし
ての保股コード比較回路、１０１はアンドゲート、１０
２はオアゲートである。その他の構成については、第３
図と同一構成部分に同一符号が付しである。In FIG. 5, PCRG is protection code 1 of received frame 19.
5ARG is a transmission register that sets transmission address 14, ZDEO is a zero detection circuit that detects that the value of protection code 18 is zero,
RAM is a memory that stores protection codes between the own station and other stations that are logically connected, and 00MP2 compares protection code 18 in frame 19 with the protection code related to the own station stored in memo IJRAM. A protection code comparison circuit as a protection code verification circuit, 101 is an AND gate, 10
2 is the or gate. For other configurations, please refer to the 3rd section.
Components that are the same as those in the figure are given the same reference numerals.

ここで、以下の説明においては、伝送装置Ｓ　’Ｉ”　
１をマスク局に位置づけ、計算機０ＰＵＩの指示により
各伝送装置ＳＴ間の論理的な接続に対する保護コードＰ
Ｃを、他の伝送装置８Ｔ２　、ＳＴ３　、、、、。Here, in the following explanation, the transmission device S'I"
1 is positioned as a mask station, and the protection code P for the logical connection between each transmission device ST is specified by the computer 0 PUI.
C to other transmission devices 8T2, ST3, .

５ＴｒＸこ配送する機能をもつとする。It is assumed that it has a function of delivering 5TrX.

第６図は各伝送装置間の論理的接続形態を示す図、第７
図は第６図に示した接続形態に対応する保護コードの一
例を示す図、第８図は保護コードを伝送するときのフレ
ーム構成例を示す図である。Figure 6 is a diagram showing the logical connection form between each transmission device, Figure 7
This figure shows an example of a protection code corresponding to the connection configuration shown in FIG. 6, and FIG. 8 shows an example of a frame structure when transmitting the protection code.

なお、保護コードの値は１６進表示で明記しである。Note that the value of the protection code is specified in hexadecimal notation.

マスク局である伝送装置ＳＴＩは、計算機ＣＰＵＩの指
示により、各伝送装置ＳＴ２．．ＳＴ３、−　。The transmission device STI, which is a mask station, transmits each transmission device ST2 . ．． ST3, -.

Ｓ’ｌ”ｎζこ第７図に示した伝送装置ＳＴの論理的接
続形態に対応する保護コードを伝送する。伝送装７− 置ＳＴ２に対して送られる第８図に示した内容のフレー
ム１９の情報は、伝送装置ＳＴＩの送信データバッファ
５ＢＵＦに設定され、送信直並列変換器８−８ＨＦおよ
び送信器Ｔを経由して伝送路１に送出される。A protection code corresponding to the logical connection form of the transmission device ST shown in FIG. 7 is transmitted.The frame 19 with the content shown in FIG. 8 is sent to the transmission device ST2. The information is set in the transmission data buffer 5BUF of the transmission device STI, and sent to the transmission line 1 via the transmission serial/parallel converters 8-8HF and the transmitter T.

伝送装置ＳＴ２では、第８図に示したフレーム１９を受
信器Ｒを経由して取り込むと、受信直並列変換器Ｒ−８
ＨＦによりシリアルからパラレルに変換し、保護コード
を保護コードレジスタＰＣＲＧに、着信アドレスを着信
アドレスレジスタＤＡＲＧに、発信アドレスを発信アド
レスレジスタ５ＡＲＧにセットしていく。保護コードレ
ジスタＰＯＲＧの保護コードは零であるので、零検出回
路ＺＤＥＯの出力がアクティブとなる。よってオアゲー
１−１０２の出力がアクティブとなる。次に着信アドレ
ス１３が自局アドレスと一致するかアドレス比較回路０
０ＭＰ１で比較される。この値が一致するとアンドゲー
ト１０１の両入力がアクティブとなり、共通制御部００
Ｍに受信指示が出力される。（但し、保護コードの値が
零のときは、従来通りの受信側８− 御である。）この受信指示により共通制御部００Ｍは、
コマンド１５．インフォメーション１６の内容をデータ
バッファＲＢＵＦに取り込む。最後にエンドフラグ１２
を受信すると、受信を終了し、誤り検出回路１００がノ
ーエラーを示すと、共通制御部ＣＯＭは受信データバッ
ファＲＢ　ＵＪｉ”からコマンドを読出し解析する。In the transmission device ST2, when the frame 19 shown in FIG.
HF converts from serial to parallel, and sets the protection code in protection code register PCRG, the incoming address in incoming address register DARG, and the outgoing address in outgoing address register 5ARG. Since the protection code of the protection code register PORG is zero, the output of the zero detection circuit ZDEO becomes active. Therefore, the output of the or game 1-102 becomes active. Next, whether the incoming address 13 matches the local address or not, the address comparison circuit 0
0MP1 is compared. When these values match, both inputs of the AND gate 101 become active, and the common control unit 00
A reception instruction is output to M. (However, when the value of the protection code is zero, the receiving side 8- is controlled as before.) Based on this reception instruction, the common control unit 00M:
Command 15. The contents of information 16 are taken into data buffer RBUF. Finally end flag 12
When the command is received, the reception ends, and when the error detection circuit 100 indicates no error, the common control unit COM reads out the command from the reception data buffer RB UJi'' and analyzes it.

この場合、保護コードセット命令ＳＰＯであるので、共
通制御部００Ｍは、受信データバッファＲ，Ｂ　ＵＦに
取り込んだ保護コードき対応する伝送装置８Ｔのアドレ
スを取り出し、相手伝送装置ＳＴのアドレスをメモリ１
１．ＡＭのアドレスとしてその保護コードを第９図に示
した如く書き込む。In this case, since it is a protection code set command SPO, the common control unit 00M takes out the address of the transmission device 8T corresponding to the protection code taken into the received data buffers R, BUF, and stores the address of the other transmission device ST in the memory 1.
1. The protection code is written as the AM address as shown in FIG.

以下同様にして伝送装置８Ｔ３、−．８ＴｎのメモリＲ
ＡＭにも各伝送装＠８Ｔ３、−　、ＳＴｎと接続関係の
ある伝送装置ＳＴのアドレスに対応する保護コードが書
き込まれる。こうして、システム内の伝送装置ＳＴ間の
論理的なポイント・トウ・ポイント接続形態に対応する
保砲コードが、各伝送装置ＳＴに設定される。Similarly, the transmission devices 8T3, -. 8Tn memory R
A protection code corresponding to the address of the transmission device ST that has a connection relationship with each transmission device @8T3, -, STn is also written in the AM. In this way, a gun protection code corresponding to the logical point-to-point connection form between the transmission devices ST in the system is set for each transmission device ST.

これ以後、例えば伝送装置ＳＴＩから伝送装置ＳＴ２に
データを伝送する場合、伝送装置ＳＴ１の共通制御部０
０Ｍは、相手伝送装置ＳＴ２のアドレスをメモリ１１．
ＡＭのアドレスとして該当保護コード（１０１）を読み
出し、送信データバッファ８ＢＵＰにセットする。以下
、順次着信アビ１１１３９発信アドレス１４．コマンド
１５．インフォメーション１６．誤り検査コード１７等
を送信データバッファＳ、ＢＵＦにセットしながら、送
信直並列変換器Ｓ−５ＨＦ　、送信器Ｔを介して、伝送
路１に８１０図に示すフレーム１９を送出する。After this, for example, when transmitting data from the transmission device STI to the transmission device ST2, the common control unit 0 of the transmission device ST1
0M stores the address of the partner transmission device ST2 in the memory 11.
The corresponding protection code (101) is read as the AM address and set in the transmission data buffer 8BUP. Hereinafter, incoming call Abi 11139 calling address 14. Command 15. Information 16. While setting the error check code 17 and the like in the transmission data buffers S and BUF, the frame 19 shown in FIG. 810 is sent to the transmission line 1 via the transmission serial/parallel converter S-5HF and the transmitter T.

受信局である伝送装置ＳＴ２は、受信器Ｒ２受信直並列
変換器Ｒ−８ＨＦを介して伝送路１を流れるフレーム１
９を取り込み、入力順に保護コード１８を保護コードレ
ジスタＦＯＲ，Ｇに、着信アドレス１３を着信アドレス
レジスタＩ）Ａ　ＲＧに、発信アドレス１４を発信アド
レスレジスタｆ９　Ａ、Ｒ，Ｇにセットする。保護コー
ド１８の値は零でないので、この受信した発信アドレス
１４をアドレスとしてメモＩＪ　ＲＡＭから対応する保
護コードを読み出す〇メモリＲＡＭから読み出されたこ
の値と保護コードレジスタＰＣＲＧの内容は、保護コー
ド比較器００ＭＰ２で比較される。結果は一致するため
、オアゲート１０２の出力がアクティブとなる。又、着
信アドレス比較器ＣＯＭＰＩで着信アドレスレジスタＤ
ＡＲ，Ｇの内容とアドレススイッチＡＤＳＷの値とが比
較され、この結果も一致するため、アントゲ−ト１０１
の両入力がアクティブとなり、共通制御部００Ｍに受信
指示が発生する。The transmission device ST2, which is a receiving station, receives frame 1 flowing through the transmission path 1 via the receiver R2 receiving serial/parallel converter R-8HF.
9, and set the protection code 18 in the protection code registers FOR, G, the incoming address 13 in the incoming address register I) ARG, and the outgoing address 14 in outgoing address registers f9 A, R, G in the order of input. Since the value of the protection code 18 is not zero, the corresponding protection code is read from the memory IJ RAM using the received sending address 14 as an address. This value read from the memory RAM and the contents of the protection code register PCRG are the protection code. Comparison is made by comparator 00MP2. Since the results match, the output of OR gate 102 becomes active. In addition, the incoming address comparator COMPI selects the incoming address register D.
The contents of AR,G and the value of the address switch ADSW are compared, and since the results match, the ant gate 101
Both inputs become active, and a reception instruction is generated to the common control unit 00M.

共通制御部００Ｍは、以下コマンド１５．インフォメー
ション１６の内容を受信データバッファＲＢ　ＵＦに取
り込み、誤り検査結果が正しいと、コマンド１５を解析
し、受信データを受信データバッファＲ，ＢＵＦよりイ
ンタフェース部ＩＮＦを介して計算機０ＰＵ２に転送し
、受信終了報告を行なう。The common control unit 00M executes the following command 15. The contents of information 16 are loaded into the reception data buffer RB UF, and if the error check result is correct, the command 15 is analyzed and the reception data is transferred from the reception data buffers R and BUF to the computer 0PU2 via the interface unit INF, and the reception ends. Make a report.

今、伝送装置ＳＴ３のアドレスが誤まって操作され、伝
送装置ＳＴ２に同じアドレスになっていたとする。Suppose now that the address of the transmission device ST3 has been manipulated by mistake, resulting in the same address as that of the transmission device ST2.

伝送装置ＳＴ３においても、伝送装置ＳＴ２と同様に伝
送路１上のフレーム１９を取り込み、保護コード１８１
着信アドレス１３９発信アドレス１４を夫々保護コード
レジスタＰＯＲＧ、着信アドレスレジスタＤＡＲＧ、発
信アドレスレジスタＳＩＧにセットする。着信アドレス
比較器００ＭＰ１において着信アドレスレジスタＤＡＲ
Ｇの内容とアドレススイッチＡＤＳＷの値とが比較され
るが、このとき伝送装置ＳＴ２のアドレスと同値にアド
レススイッチＡＤ　ＳＷが誤設定されているため、一致
を示す。The transmission device ST3 also captures the frame 19 on the transmission path 1 in the same way as the transmission device ST2, and transmits the protection code 181.
The incoming address 139 and outgoing address 14 are set in the protection code register PORG, incoming address register DARG, and outgoing address register SIG, respectively. Incoming address register DAR in incoming address comparator 00MP1
The contents of G and the value of the address switch ADSW are compared, but at this time, since the address switch ADSW is erroneously set to the same value as the address of the transmission device ST2, a match is shown.

しかし、発信アドレスレジスタ８ＡＲＧの発信アドレス
１４をアドレスとしてメモリＲ，ＡＭの該当保護コード
を読み出し、保護コード比較器００ＭＰ２で受信した保
護コード１８と比較すると不一致であるため、ＡＮＤゲ
ート２１の両入力がアクティブとならず、共通制御部０
０Ｍには受信指示が発生しない。よって、以下のコマン
ド１５．インフォメーション１６の内容は伝送装置ＳＴ
３では受信されない。However, when the corresponding protection codes in memories R and AM are read using the sending address 14 of the sending address register 8ARG as an address and compared with the protection code 18 received by the protection code comparator 00MP2, they do not match, so both inputs of the AND gate 21 are Not active, common control unit 0
No reception instruction occurs at 0M. Therefore, the following command 15. The content of information 16 is the transmission device ST.
3 is not received.

このように、上記構成になる伝送システムは、伝送装置
ＳＴのアドレスを決めるアドレススイッチＡＤ　ＳＷが
誤設定され、システム内に２個以上存在しても、相手局
対応に保護コード１８が設定されるため、目的局だけし
か受信できないので、システム内での情報の秘密を確実
に保護することができる。In this way, in the transmission system having the above configuration, the address switch AD SW that determines the address of the transmission device ST is incorrectly set, and even if there are two or more switches in the system, the protection code 18 is set for the other station. Therefore, since only the destination station can receive the information, the confidentiality of information within the system can be reliably protected.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は伝送システム一般の構成例を示す図、第２図は
従来のフレーム構成例を示す図、第３図は従来の伝送装
置の構成例を示す図、第４図は本発明になる伝送システ
ムを適用したフレームの構成例を示す図、第５図は本発
明になる伝送システムに用いた伝送装置の構成例を示す
図、第６図は各伝送装置間の論理的接続形態を示す図、
第７図は第６図に示した接続形態に対応する保護コード
の一例を示す図、第８図は保護コードを伝送するときの
フレーム構成例を示す図、第９図は本発明になる伝送シ
ステムが保護コードを保持するためのメモリの内容を示
す図、第１０図はデータ伝送時のフレーム構成を示す図
である。 １・・・・・・・伝送路、ＳＴ・・・・・・・・伝送装
置、ＣＰＵ・・・・・・・・計算機、１３・・・・・・
・・着信アドレス、１４・・・・・・・・・発信アドレ
ス、１５・・・・・・・・・コマンド、１６・・・曲・
・インフォメーション、１７・・・・・・・・・誤り検
査コード、１８・・・曲・・保護コード、１９・・・・
・・・・フレーム、ＡＤＳＷ・凹曲アドレススイッチ、
ＣＯＭＰｌ・曲・・アドレス比較器、ＣＯＭＰｚ・・・
・・・−・保護コード比較器、ＣｏＭ・・・・・曲共通
制御部。 代理人　葛野信−FIG. 1 is a diagram showing an example of the configuration of a general transmission system, FIG. 2 is a diagram showing an example of a conventional frame configuration, FIG. 3 is a diagram showing an example of the configuration of a conventional transmission device, and FIG. 4 is a diagram of the present invention. A diagram showing an example of the configuration of a frame to which the transmission system is applied, FIG. 5 is a diagram showing an example of the configuration of a transmission device used in the transmission system of the present invention, and FIG. 6 shows a logical connection form between each transmission device. figure,
FIG. 7 is a diagram showing an example of a protection code corresponding to the connection configuration shown in FIG. 6, FIG. 8 is a diagram showing an example of a frame structure when transmitting a protection code, and FIG. A diagram showing the contents of a memory for the system to hold a protection code, and FIG. 10 is a diagram showing a frame structure during data transmission. 1...Transmission line, ST...Transmission device, CPU...Computer, 13...
...Incoming address, 14...Outgoing address, 15...Command, 16...Song...
・Information, 17...Error check code, 18...Song...Protection code, 19...
...Frame, ADSW/concave address switch,
COMPl/song/address comparator, COMPz...
...--Protection code comparator, CoM... Song common control section. Agent Makoto Kuzuno

Claims (1)

【特許請求の範囲】 複数の伝送装置が共通の伝送路を介して接続され、該複
数の伝送装置間でデータ伝送を行なう伝送システムにお
いて、フレームは発着信アドレス。 コマンド、データ、上記伝送装置間の接続を示す発着信
アドレスの保護コード及び誤り検査コードで構成され、
上記伝送装置は自局アドレスを設定する機構と、上記フ
レーム内の着信アドレスと自局アドレスが一致するか否
かを検定するアドレス検定回路と、上記保護コードが自
局の保持している発着信アドレスに対応した保護コード
に一致するか否かを検定する保護コード検定回路と、上
記保護コードを自局と論理的に接続関係のある上記伝送
装置対応に保持する回路を有し、さらに上記伝送装置の
一つが上記伝送装置間の論理的な接続対応１こ、相手局
アドレスとともに前記保護コードを上記伝送路を介して
上記各伝送装置に通知する手段を有しており、受信した
フレーム内の着信アドレスと、発信アドレスに対応した
保護コードを夫々アドレス検定回路と保護コード検定回
路により検定し、両者ともに一致したとき受信フレーム
を取り込むようにしたことを特徴とする伝送システム。[Claims] In a transmission system in which a plurality of transmission devices are connected via a common transmission path and data is transmitted between the plurality of transmission devices, a frame is an originating and receiving address. Consists of commands, data, a protection code for the incoming and outgoing address indicating the connection between the above transmission devices, and an error check code,
The above transmission device includes a mechanism for setting the own address, an address verification circuit for verifying whether the incoming address in the frame matches the own address, and an outgoing/incoming call whose protection code is held by the own station. It has a protection code verification circuit that tests whether the address matches the protection code corresponding to the address, and a circuit that holds the protection code corresponding to the transmission device that has a logical connection relationship with the local station, One of the devices has a means for logical connection between the transmission devices and notifies each of the transmission devices of the protection code together with the destination station address via the transmission path. A transmission system characterized in that an incoming address and a protection code corresponding to an outgoing address are verified by an address verification circuit and a protection code verification circuit, respectively, and a received frame is captured when both match.
JP15125181A 1981-09-24 1981-09-24 Transmission system Pending JPS5853251A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15125181A JPS5853251A (en) 1981-09-24 1981-09-24 Transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15125181A JPS5853251A (en) 1981-09-24 1981-09-24 Transmission system

Publications (1)

Publication Number Publication Date
JPS5853251A true JPS5853251A (en) 1983-03-29

Family

ID=15514569

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15125181A Pending JPS5853251A (en) 1981-09-24 1981-09-24 Transmission system

Country Status (1)

Country Link
JP (1) JPS5853251A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02171454A (en) * 1988-12-26 1990-07-03 Kasumi Kiritani Ridge tile and ridge part execution method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02171454A (en) * 1988-12-26 1990-07-03 Kasumi Kiritani Ridge tile and ridge part execution method

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