JPH01143542A - Loop back test system - Google Patents

Abstract

PURPOSE:To minimize the reduction in the transmission efficiency of general frame even if a loop back test looping back a test frame as it is implemented by using a start flag of a transmission frame for a general use and a loop back test use. CONSTITUTION:A control flag CFL identifying a general frame and a loop back test frame is provided in a start flag of a transmission frame at first in the loop back test. The flag CFL indicates the general frame in case of CFL=1 and the loop back test frame in case of CFL=0. When the loop back test mode is set to an optional node, the flag CFL is set to the state of CFL=0 instructing the loop back test and sent to a transmission line 10. When the state of CFL=0 is discriminated in a sender destination node, e.g., a node B, which throws the changeover circuit 12 to the position of a path A of the loop back test state where the reception frame is sent as it is to return the frame to a sender node A. Thus, the reduction in the transmission efficiency of a general frame is minimized.

Description

[Detailed Description of the Invention] [Summary] Regarding a loopback test method for a system in which information is exchanged frame by frame between multiple nodes connected to a transmission line, even if a loopback test is performed in which test frames are sent as they are, normal frames are In order to minimize the decrease in transmission efficiency, a control flag is provided in the start flag of the transmission frame to distinguish between a general frame and a loopback test frame. The control flag of the node is set to indicate a loopback test and sent to the transmission line, and when the loopback test is determined from the control flag in the start flag received at the destination node, the switching circuit in the node is used to directly transfer the received frame to the transmission line. The configuration was configured to set the switching route for the return test sent to.

[Industrial Application Field] The present invention relates to a loopback test method for a system in which information is exchanged in units of frames between a plurality of nodes connected to a transmission line.

In a system in which multiple nodes with independent information processing functions are connected to a transmission path such as a local area network (LAN), and information is exchanged between each node in frame units, it is difficult for mutual transmission between nodes to occur properly. In order to confirm whether or not the test is being carried out, a return test is performed either at the operator's instruction or automatically.

In such a loopback test, a specific node that has been set to test mode sends a loopback test frame to a specified destination, and the source node identifies the loopback test frame that is returned from the destination. The transmission system is highly reliable (RASII).
performance).

[Prior Art] FIG. 5 is a block diagram of a conventional system. In this example, a plurality of nodes A and B are connected to the transmission line 10.

Nodes C, D, E, and F are connected, and each of the nodes A to F exchanges information on a frame-by-frame basis using the transmission path 10.

Each node in FIG. 5 has an internal configuration shown in FIG. 6.

In FIG. 6, 16 is a transmission line connector, and transmission line 1
It has the function of connecting 0 and nodes. Transmission line connector 16
There is a receiving receiver 18 and a transmitting driver 2 in the node.
0 is connected. Frame data (serial data) on the transmission path 10 received by the reception receiver 18 is converted into parallel data by the serial/parallel conversion circuit 22, and parallel data sent to the transmission driver 20 is converted to serial data by the parallel/serial conversion circuit 24. is converted to

Each of the serial-parallel conversion circuit 22 and the parallel-serial conversion circuit 24 is connected to the transmitting/receiving buffer 7 memory 28 via the return point switching circuit 12a.

Controller 3 for sending/receiving buffer 7 memory 28
0 is connected, and performs creation of a transmission frame and identification processing of a reception frame, and also transmits and receives a return test frame during a return test.

In addition, the transmitting/receiving buffer 7 memory 28 can be connected to an external channel or other device via an I10 interface 32. Furthermore, an external controller 34 is provided for the controller 30, and the external controller 34 handles information in the node. It functions as a sub-controller that monitors RASII functions and instructs RASII functions.

FIG. 7 shows a frame structure used in the conventional system.

First, as shown in FIG. 7(a), a transmission frame consists of a start flag ■, a partner address (destination) ■, a self address (source) ■, control information ■, information (data) ■, Fe
2 (frame checksum) ■ and end flag ■.

In such a frame configuration, the start flag ■,
Data ■ and end flag ■ are shown in Figure 7 (b
) to (d), the transmitting/receiving buffer memory 28
In the above, for example, it is treated as 8-bit data, but when converting the parallel 8-bit data from the transmission/reception buffer memory 28 into serial data, the parallel-to-serial conversion circuit 24 converts the parallel 8-bit data from the transmitting/receiving buffer memory 28 to bit "1," bit "d," and bit ", respectively. It has a function of adding "0", and therefore is handled as serial 9-bit data on the transmission line 10.

Therefore, when transmitting information from an arbitrary node, for example, node A, to node B, the destination address ■ is the node B address, and the self address ■ is the node A address.
A frame in which appropriate data is set for control information (1) and/or data (2) is created and stored in the transmission/reception buffer 1 memory 28, converted into serial data by the parallel/serial conversion circuit 24, and transmitted to the transfer path 10.

The frame data transmitted on the transmission line 10 in this manner is provided to the serial/parallel converter circuit 22 via the transmission line connector 16 and reception receiver 18 of the destination node B. The serial/parallel converter circuit 22 identifies each flag by checking the lower three bits of the 9-bit start flag, data, and end flag received from the transmission line 10. Also, from the time when the start flag is identified and synchronized, the information received from the transmission line 10 is identified every 9 bits as data or end flag, and is converted into 8-bit parallel data, and the information is converted into 8-bit parallel data, Destination address■
If they match, the received frame is stored in the transmitting/receiving buffer memory 28, and under the control of the controller 30 (decoded and necessary processing is performed).

On the other hand, in the node shown in FIG. 6, a loopback point switching circuit 12a and a loopback release timer 36 are provided for carrying out a loopback test.

Here, the loopback test in this type of system includes a test at a so-called loopback point where the received loopback test frame is returned to the sender as it is, and a test at a so-called loopback point where the received loopback test frame is stored in the transmitting/receiving buffer memory 28 and then returned to the sender. There are two types of so-called return point ■exams.

The return point switching circuit 12a is provided to switch between the return point test and the return route (■, ■) based on the return point test.
The output of the serial/parallel conversion circuit 22 is directly connected to the parallel/serial conversion circuit 24 as shown in path ■.On the other hand, when testing the return point ■, the output of the serial/parallel conversion circuit 22 is connected directly to the parallel/serial conversion circuit 24, as in the case of normal frame reception.
The serial/parallel conversion circuit 22 and the parallel/serial conversion circuit 24 are connected to the transmission/reception buffer 7 memory 28 as shown in FIG.

Further, the loopback release timer 36 has a function of maintaining the switched state of the loopback test route (2) for a certain period of time when receiving an instruction to test the loopback point.

FIG. 8 shows the operational flow of the conventional loopback point (2) test, and shows the case where the loopback test is conducted from node A to node B.

Assuming that node A is now set to a test mode for a return point test, node A transmits a return instruction frame to transmission line 10 with node B as the destination, as shown in step S1.

In this return instruction frame, as shown on the right side, the node B address is set as the destination address ■, the node A address is set as the source address ■, an instruction for the return point ■ is set in the control information ■, and furthermore, Test data is set as data ■.

When a return instruction frame is transmitted from node A in step S1, node B receives the frame in step S2, compares its own address and destination address in step S3, and if they match, proceeds to step S4 and receives the frame. The frame is stored in the transmission/reception buffer memory 28.

Subsequently, the controller 30 identifies the received frame stored in the buffer memory 28 in step S5, and then identifies the received frame stored in the buffer memory 28 in step S6.
If it is a turn-back instruction frame, it is checked in step S7 whether or not it is the turn-back point (3).

At this time, if the turning point ■ is determined, step S
At step 8, node B transmits a return notification frame to node A, which is the transmission source.

In this callback notification frame from node B, as shown on the right side, the destination address (■) is set to the node A address, the source address (■) is set to the node B address, and the control information (■) is set to return notification. .

The return notification frame transmitted from node B in step S8 is received by node A in step S9, and
If it is determined in step S10 that the addresses match, the process proceeds to step S11, where a received frame identification process is performed. When a return notification frame is determined from this identification process in step S12,
Proceeding to step S13, it is checked whether the test data for transmission and reception match. If they match, it is determined that the transmission function is normal; on the other hand, if they do not match, it is determined that the system is abnormal due to the occurrence of an error. This completes the series of return points.

FIGS. 9A and 9B show the operational flow when testing the return point from node A to node B.

First, when node A is set to a test mode for testing a loopback point, node A transmits a loopback instruction frame to the transmission line 10 in step S1.

This return instruction frame is taken out and shown on the right side,
It includes the transmission destination node B address (■), the transmission source node A address (■), and an instruction for the return point (■) as control information, but does not include the test data (2) for the return point (■) test in FIG.

The return instruction frame transmitted from node A in step S1 is received by node B in step S2, and if the addresses are compared in step S3 and match, step S
4, the received frame is stored in the transmission/reception buffer memory 28.

Subsequently, the controller 30 performs a process of identifying the received frame in step S5, and when a return instruction frame is determined in step S6, it is checked in step S7 whether or not it is a return point, and if it is a return point, step S8
Proceed to.

In step S8, the controller 30 outputs the I control signal to the return point switching circuit 12a to switch the return point (2), and at the same time starts the return release timer 36.

When the route of the return point (3) is thus set in the node B in step S8, the node B transmits a return confirmation frame to the source node A in step S9.

This return confirmation frame is taken out and shown on the right,
Node A address that will be the destination, Node B that will be the source
Address and further includes return confirmation information (■) as control information.

When a return confirmation frame is transmitted from node B in step S9, node A receives the transmitted frame in step S10, determines whether the addresses match in step 811, and stores the received frame in the buffer memory 28 in step S12. In the next step 313, the controller 30 performs identification processing of the received frame stored in the buffer memory 28, and when a return confirmation frame is determined in step S14, the process proceeds to step S15 in FIG. 9B.

In step S15 of FIG. 9B, node A transmits a return test frame to node B. This return test frame has both the destination address ■ and the source address ■ set to the node A address, and test data ■ added to the return instruction frame transmitted in step S1 of FIG. 9A.

When node A transmits a return test frame in step 315, at this time, the inside of node B is in step S8 of FIG. 9A.
As a result of the process, the route (2) is switched to the path (2) by the turn-back point [A], so the received frame is sent back to the transmission line 10 via the path of the turn-back point (2) as is, as shown in step S17.

The return test frame that is returned as is from node B is received by the source node A in step 31B, and address matching is determined in step 319 and stored in the buffer memory 28 in step 320. 30 performs identification processing on the received frame in step 321, and when it is determined in step S22 that it is a return test frame, in step 323, it checks whether the transmitted and received test data match or do not match, and determines the return point of the series. End familiarization.

Of course, the loopback release timer 36 activated in step S8 of FIG. 9A times out after a predetermined test setting time has elapsed, and the loopback test route is restored to the normal frame transmission/reception state in order to return to route (3).

[Problems to be solved by the invention] However, in the conventional return point test,
Even if the loopback test is completed, the received frame cannot be stored in the transmitting/receiving buffer 7 memory until the loopback release timer times out, so general frames sent from other nodes will not be looped back during that time. As a result, there was a problem in that the efficiency of information transmission between nodes was reduced due to the return point test.

The present invention has been made in view of such conventional problems, and provides a loopback test method that can minimize the reduction in transmission efficiency of general frames even when a loopback test is performed in which test frames are sent back as they are. The purpose is to

[Means for solving problems] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1(a), there is a system in which information is transmitted between multiple nodes A and B connected to a transmission line 10 in frame units, and this frame is transmitted as shown in FIG. 1(b). It includes at least a start flag, a destination address, a source address, control information, and data.

In the loopback test method of the present invention, first, as shown in FIG. 1(b), a control flag (CFL) for distinguishing between a general frame and a loopback test frame is provided in the start flag of a transmission frame.

Here, the general frame includes a so-called conventional return point (2) test in which the return test frame is processed within the node and then sent back to the transmission source.

The control flag CFL placed in the start lug indicates, for example, a general frame when CFL=1, and a return test frame when CFL=0.

When a loopback test mode is set for an arbitrary node, for example, node A, the control flag CFL in the start flag is set to CFL=O, which indicates a loopback test, and is transmitted to the transmission line 10.

When the destination node, for example, node B, determines from the control flag CFL included in the start flag of the received frame that a return test is performed in which CFL=O, it causes the switching circuit 12 in node B to transmit the received frame as it is to the transfer path 10. Switch to route [A] in return test state and send source node A
send it back to

[Function] Control flag C provided in the start flag of the received frame
The circuit can be switched from the FL to the loop test state where the loop test is immediately determined without frame identification processing by the controller, etc., and the received frame is sent back to the transmission path as is, and the loop test can be completed with one transmission access. can.

In addition, as soon as the return of the loopback test frame is completed, the state returns to the normal frame reception state (route ■), and instead of continuing the switchover route for the loopback test for a certain period of time by a timer as in the past, immediately after the loopback test frame is returned. It is possible to store general frames received in the buffer memory and perform normal identification processing, and even if loopback tests are performed, the 'J' effect on normal frame transmission can be minimized, improving the information transmission efficiency of the system. can be improved.

[Example] FIG. 2 is an explanatory diagram showing the internal configuration of a node used in the loopback test method of the present invention.

In FIG. 2, reference numeral 10 denotes a transmission path, to which a plurality of nodes A to F are connected as shown in FIG. 5, and information is mutually transmitted between nodes A to F in frame units.

A node is connected to this transmission line 10 via a transmission line connector 16. That is, a reception receiver 18 and a transmission driver 20 provided within the node are connected to and from the transmission line connector 16, respectively.

The reception frame (serial data) from the transmission line 10 received by the reception receiver 18 is converted into parallel data by the serial/parallel conversion circuit 22, and stored in the transmission/reception buffer 7 memory 28 via the return point switching circuit 12a. . Further, the output of the parallel-serial conversion circuit 24 is connected to the transmission driver 20, and the transmission/reception buffer memory 2
Frame data (parallel data) read from 8 is given, converted into serial data by a parallel-to-serial conversion circuit 24, and sent to the transmission line 1 via the transmission driver 20 and transmission line connector 16.
It will now send on 0.

The controller 3 is connected to the transmitting/receiving buffer memory 28.
0 is provided, and the controller 30 has a control function of data transmission/reception based on the general frame and loopback test based on the loopback test frame.

The transmitting/receiving buffer 7 memory 28 can be connected to an external channel or other device via an I10 interface 32, and an external controller 34 is provided for the controller 30, and the external controller 34 allows information in the node to be The controller functions as a sub-controller that supports RAS functions.

FIG. 3 is an explanatory diagram showing the structure of a transmission frame used in a system in which a plurality of nodes having the internal structure shown in FIG. 2 are connected to the transmission line 10.

First, as shown in Figure 3(a), the transmission frame has a start flag ■, a destination address ■, and a destination address ■, as in the conventional system.
, source address■, control information■, information data)■,
Consists of Fe50 and end flag ■.

In the present invention, for such a transmission frame, as shown in FIG.
We have prepared two start flags: a general frame start flag and a return test frame start flag.

That is, the general frame start flag that is handled on the buffer memory as 8-bit data shown in FIG. 3(b) is rolllllloJ, and on the transmission path, the 8-bit data on the buffer memory 1 bit “1” when converting parallel data to serial data
is added to make it 9 bits, so the start flag for general frames on the transmission path is rollllllolJ.
becomes.

On the other hand, in the start flag for the return test frame shown in Figure 3(C), the 3rd bit from the least significant bit for 8-bit data on the buffer memory, and the least significant bit for 9-bit data on the transmission path. The fourth bit from the additional bit "1" is set to bit "0". That is, the third bit on the buffer memory and the fourth bit on the transmission path becomes the control bit rCFLJ for identifying the general frame and the return test frame.
CFL=1 indicates a general frame start flag,
FL=O indicates the start flag for the return test frame.

Regarding data ■ and end flag ■, see Figure 3 (d
) and (e), the 8-bit data on the buffer memory is handled on the transmission path as 9-bit data with bits rqJ and rOJ added, and this point is the same as in the conventional system.

On the other hand, in the present invention, as shown in FIGS. 3(b) and (C), the fourth bit on the transmission path is the control bit CFL for identifying the general frame and the return test frame. The check range of the start flag data and end flag in the serial/parallel conversion circuit 22 of FIG. 2 is set to the lower 4 bits including the control flag CFL, compared to the conventional lower 3 bits.

Note that the general frame start flag shown in FIG. 3(b) is the conventional switching point where the return test frame is stored in the transmitting/receiving buffer memory 28 and then sent to the transmission path and returned to the source.■ Test return test frame This includes: Therefore, the start flag for the loopback test frame shown in FIG.
It will only apply to exams.

Means for identifying the control flag CFL set in the fourth bit of the start flag shown in FIG. 3 is provided in the serial-to-parallel converter circuit 22 in FIG.
Converts the 9-bit start flag received from the transmission line 10 into parallel data and checks the lower 4 bits.
For example, when the lower 4 bits have the logic condition rllolJ, the loopback point switching circuit 12a switches the serial/parallel converter circuit 22 and the parallel/serial converter circuit 24 to the transmitting/receiving buffer memory 28 side to create a route for the loopback point (2).

In addition, the 9
rolol from the lower 4 bits of the bit start flag
When the identification output of J is obtained, this identification output causes the return point switching circuit 12a to connect the output of the serial-to-parallel conversion circuit 22 directly to the parallel-to-serial conversion circuit 24.
is in the switching state. The switching state of the turning point (2) is canceled when the serial/parallel conversion circuit 22 finishes transferring the end flag, which is the final data of the received frame, to the parallel/serial conversion circuit 24, and the path returns to the switching point (2).

Next, the loopback test of the present invention, that is, the test at the loopback point, will be explained with reference to the loopback test operation flowchart of the present invention shown in FIG.

Now, as shown in the system of FIG. 5, it is assumed that a loopback test is performed from node A to node B.

First, when node A receives the test mode setting for the return point test, node A transmits a return instruction frame to the transmission path 10 in step S1.

This return instruction frame is taken out and shown on the right side,
Start flag■, Node B address as destination■
, consists of the node bear address as the sender ■, return test information ■, test data ■, FC3 ■, and end flag ■, and the start flag ■ is 8-bit data on the buffer 7 memory in Figure 3 (C). roll as shown
llolo” and the third control bit CFL
is set to CFL=O. The loopback test start flag on this buffer memory is given to the parallel-to-serial conversion circuit 24 via the loopback point switching circuit 12a, and the parallel-to-serial conversion circuit 24 adds 1 bit '1' to it as 9-bit data and sends it to the transmission line. sent to. The transmission of this 9-bit data to the transmission line 10 is the same for the test data (2) and the end flag (2) as shown in FIGS. 3(d) and (e).

Referring again to FIG. 4, when a return instruction frame is transmitted from node A to the transmission path in step S1, node B receives the transmitted frame in step S2, and in step S3
identifies the lower 4 bits of the start flag of the received frame. At this time, since the lower 4 bits are CFL=O, it is in rololJ, and it is determined that this is a return test frame, and the process proceeds to step S5, where the destination address of the received frame is compared with the self address of node B, and both are confirmed. If they match, the process proceeds to step S6, where the loopback point switching circuit 12a is controlled to switch to the loopback point (2) based on the identification output of the loopback test frame determined in step S4.

As a result, the received frame obtained in 8-bit units from the serial-to-parallel conversion circuit 22, that is, the loopback instruction frame, is directly applied to the parallel-to-serial conversion circuit 24 via the loopback point switching circuit 12a, and is again converted into 9-bit serial data. and is sent out to the transmission path 10 as shown in step S7. When all received frames have been sent out, the loopback point switching circuit 12a returns to the loopback point (2) via the transmission/reception buffer memory 28 again.

Transmission path 1 is determined by the path of turnaround point ■ in step S7.
The return instruction frame sent to Node A is received by node A in step S8, and if address matching is determined in step S9, the process proceeds to step S10 and the received frame is stored in the buffer memory 28. In the next step 311, the controller 30 identifies the received frame, and if it is determined in step 312 that it is a return test frame, the process proceeds to step 313 to check whether the transmitted frame and the received frame match, and if they match, the controller 30 identifies the received frame. It is assumed that normal data transmission was performed, and if there is a mismatch, a system error is determined. This completes the series of turnaround point tests.

On the other hand, if the lower 4 bits of the start flag in node B are rllolJ in step S4, that is, if the control flag CFL=1, it is determined that it is a general frame, and in step 314, the presence or absence of address matching is checked. If the addresses match, the received frame is stored in the buffer memory 28 in step S15, and step S16
Then, the controller begins to perform identification processing of the received frame stored in the buffer 7 memory 28. Of course, the turning point of the conventional system ■ Step S16 in the test
When the frame identification process is performed, the flow shown from step S6 onward in FIG. 8 is executed.

[Effects of the Invention] As explained above, according to the present invention, by using the start flag of a frame for general use and loopback test, the node can be switched to loopback test only when a loopback test frame is received. Therefore, the effect on the transmission of general frames can be minimized by the loopback test, and even if the loopback test is performed, the efficiency of information transfer using the general frame can be improved.

In addition, since the test process of sending back the return test frame as is can be completed with one access from the source to the destination, the return test can be completed in a short time and the impact of the return test on the transmission of general frames is minimized. can be suppressed to

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention: Fig. 2 is a configuration diagram of an embodiment of the invention: Fig. 3 is a frame configuration diagram of the present invention: Figure 4 is a flowchart of folding test operation of the present invention: Fig. 5 Figure 6 is a conventional system configuration diagram: Figure 6 is a conventional node configuration diagram: Figure 7 is a conventional frame configuration diagram: Figure 8 is a conventional return point ■Test operation flow diagram: Figures 9A and 9B are conventional Return point ■It is an operation flow diagram of the test. In the figure, 10: Transmission line 12: Switching circuit 12a: Return point switching circuit 16: Transmission line connector 18: Receiver for reception 20: Driver for transmission 22: Serial to parallel conversion circuit 24: Parallel to serial conversion circuit 28: Transmission and reception buffer Memory 30: Controller 32: I10 interface 34: External controller check range (d) Data abε"L
Color 13 pins [l) 1 tsuhua memory stop 4S1 MiU too!
Brave! Tano L1 Buddha delivery also L1 check Inuda (el Esid flag 0111110
1 [1st month 6 frame structure on computer memory - August figure Figure 3

Claims (1)

[Scope of Claims] A plurality of nodes (A) connected to a transmission path (10), each having a transmission frame including at least a start flag, a destination address, a source address, control information, and data;
(B) A system for exchanging information in units of frames, wherein a control flag (CFL) for identifying a general frame and a return test frame is provided in the start flag of the transmission frame, and an arbitrary node When the loopback test mode is set in (A), a loopback test instruction is set (CFL=0) in the control flag (CFL) in the start flag and transmitted to the transmission path, and the above is received at the destination node (B). When determining the return test from the control flag (CFL) in the start flag,
A loopback test method characterized in that a switching circuit (12) in the node is switched to a loopback test path [A] that transmits received frames as they are to a transmission path.