JPH1145212A - Opposing method against deciphering attack regarding secret information - Google Patents

Abstract

PROBLEM TO BE SOLVED: To oppose an attack for deciphering secret information by replacing and storing the secret information in a different place by electronic devices each time it is written to a volatile memory. SOLUTION: Data on the address 0000 of secret information before conversion in a memory 10 are D7hex and when the secret information is stored for the first time according to a storage converting rule, it is stored in address 0003 of the volatile memory 11 by conversion to F7hex. For second storage, it is stored in address 0003 of the volatile memory 11 by conversion to code data other than F7hex. Similarly, data on the address 0001 are 17hex, first storage in the address 0003 of the volatile memory 11 is performed by conversion to A2hex, and data on the address 0002 are 9Bhex; and first storage in address C123 of the volatile memory 11 is performed by conversion to 5Dhex. Thus, the secret information is stored in different places by electronic devices each time it is stored in the memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for countering an attack for decrypting secret information stored in a memory of an electronic device housed in a housing.

[0002]

2. Description of the Related Art Conventionally, electronic devices that hold secret information are subjected to various methods for disassembling the housing of the electronic device and easily reading the held secret information from a memory so that the secret information cannot be decoded. ing. For example, as a method of countering an attack that attempts to decipher confidential information stored in a volatile memory inside an electronic device (Tamper Resistant), a method is provided in which a memory is enclosed in a container and a means for detecting an external attack is provided. A method of erasing the secret information in the memory when receiving the information is known from Japanese Patent Application Laid-Open No. 2-44447.

[0003]

However, in the above-described conventional method of detecting an attack and erasing the secret information in the memory, when the structure to be erased is clarified, the backup of the volatile memory is performed. It becomes possible to read the secret information without erasing it. For example, there is a problem that a content comparison of a plurality of pieces of read information and a condition for decoding based on a positional relationship where information is stored are given.

[0004] The present invention solves the above-mentioned problem. When writing secret information to a volatile memory, the present invention converts the content and storage location of the secret information into an attack for deciphering the secret information. An object of the present invention is to provide a countermeasure for countermeasures against decryption of secret information which can be countered.

[0005]

In order to solve the above-mentioned problems, the present invention comprises means for arbitrarily converting write information into a volatile memory holding secret information. Is converted and stored in a different location for each electronic device and each time it is written to the volatile memory.

According to the present invention, it is possible to combat an attack for decrypting secret information.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention comprises means for arbitrarily converting write information into a volatile memory holding secret information, and the secret information is converted by the conversion means. It is converted and stored in a different place for each electronic device and each time it is written to the volatile memory. Since the position of the secret information written to the volatile memory is unspecified, a plurality of read secret information This has the effect that it is possible to make it difficult to provide information that is a clue for decryption.

According to a second aspect of the present invention, the conversion means is constituted by a switch for arbitrarily converting information on the address signal line and the data signal line and exchanging each signal line. And data signal lines can be replaced arbitrarily, and can be accessed by replacing the address order and the bit position of data corresponding to the number of address and data signal lines. The above information has the effect that the number of combinations of signal lines can be made different for each device.

According to a third aspect of the present invention, the conversion means comprises a conversion memory in which information for address signal lines and data signal lines is arbitrarily converted and information for replacing each signal line is written. The secret information is stored non-linearly by the information in the conversion memory, the secret information can be stored in a non-linear space with respect to the volatile memory, and the volatile memory can be converted to a combination of signal lines or more. It has the effect of being able to access.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

(Embodiment 1) FIG. 1 shows the principle of converting secret information into a volatile memory and storing it in an arbitrary location by a method for countering the attack of deciphering secret information according to a first embodiment of the present invention. FIG. In FIG. 1, reference numeral 10 denotes a memory indicating a storage state of secret information before conversion, and reference numeral 11 denotes a state after storing the secret information based on a different storage conversion rule for each electronic device and each time writing to the memory. Volatile memory.

In this configuration, the data at the address 0000 of the secret information before conversion in the memory 10 is D
7 hex, and the first storage based on the storage conversion rule of the secret information is the address 0003 of the volatile memory 11.
The address is converted into F7hex and stored. In the second storage, code data other than F7 hex is converted and stored at address 0003 of the volatile memory 11.

Similarly, the data of the address 0001 of the secret information before conversion in the memory 10 is 17
hex, which is based on the storage conversion rule of the secret information.
The second storage is performed by converting A2hex into the address 0003 of the volatile memory 11 and storing the converted data.
The data at the address 0002 of the secret information before the conversion at 0 is 9Bhex, and the first storage based on the storage conversion rule of the secret information is converted into 5Dhex at the address C123 of the volatile memory 11 and stored. . Similarly, in the second storage, code data other than those described above is converted and stored at the address. When the secret information converted and stored in the volatile memory 11 is read out, the secret information before the conversion shown in the memory 10 can be returned by performing a conversion reverse to that at the time of storage.

As described above, since the secret information is converted into information and stored in the volatile memory based on the storage conversion rule in different places for each electronic device and each time the data is written to the memory, a plurality of pieces of the secret information stored in the volatile memory are used. , It is possible to make it difficult to understand the features for decoding.

(Embodiment 2) Embodiment 2 of the present invention will be described with reference to FIGS. FIG. 2 shows the first embodiment.
Is a block diagram in which a conversion circuit is provided on an address bus and a data bus connecting a volatile memory and a microprocessor, and FIG. 3 is a block diagram in a case where the conversion circuit is constituted by a changeover switch. FIG. 4 is a configuration diagram of the changeover switch.

In FIG. 2, reference numeral 12 denotes a microprocessor (MPU), and reference numeral 13 denotes storage and conversion of secret information transferred from outside the electronic device to a different location under the control of the microprocessor 12 for each electronic device and each time it is written to a memory. A conversion circuit 14 for converting based on the rule is a volatile memory for storing the secret information converted by the conversion circuit 13. An address bus 15 is provided between the microprocessor 12 and the conversion circuit 13.
The conversion circuit 13 and the volatile memory 14 are connected by an address bus 17 and a data bus 18.

In FIG. 3, the conversion circuit 13 comprises address change switches SWA0, SWA1,... Of a select type of 1: n corresponding to the address terminals A0 to An and the data terminals D0 to Dm of the microprocessor 12. 1: m select type data switch SWD
., And one input / output terminal of each of the address changeover switches SWA0, SWA1,... Is connected to the address signal lines of the addresses A0 to An of the microprocessor 12, and further, each of the address changeover switches SWA0, SWA1,. SW
The same signal lines at the n input / output terminals of A0, SWA1,... Are connected in parallel to the address signal lines of addresses A0 to An of the volatile memory 14. In addition, the data changeover switch S
Are connected to the data signal lines of the data D0 to Dm of the microprocessor 12, and further, each of the data changeover switches SWD0, SWD.
The same signal lines at the n input / output terminals of the 1...
Are connected in parallel to the data signal lines of the data D0 to Dm.

FIG. 4 shows the configuration of an address and data selector switch, which is constituted by a 1: n or 1: m select type switch, which is switched by a control signal SWSELxx from the microprocessor 12. Section SWxx is connected to n or m input / outputs B, C, D
.., The input / output A is switched to n or m input / outputs B, C, D.

In the above configuration, the input and output B of each changeover switch are connected by the same signal line, and each changeover switch is controlled by the control signal from the microprocessor 12 in the same signal line in units of address buses and data buses. Is selected so that, for example, the changeover switch SWA0 input / output A is connected to the address A0 of the microprocessor 12, and the changeover switch SWA0 input / output B
Thereafter, it is connected to the addresses A0 to An of the volatile memory 14. The control signal SWSELxx from the microprocessor 12 causes the address A of the volatile memory 14 to be changed.
Assuming that 1 has been selected, an address other than the address A1 of the volatile memory 14 is selected for the changeover switches other than the changeover switch SWA0. Also, data can be converted in the same manner as in the case of address.

Therefore, according to the second embodiment, the software of the microprocessor 12 can store data in an arbitrary address space that is visible in the same memory space and is discontinuous. Since the bit position of the data can be changed, even if the same secret information is written in each electronic device, the information on the memory can be different for each device up to the number of signal line combinations.

(Embodiment 3) Embodiment 3 of the present invention will be described with reference to FIG. FIG. 5 is a block diagram showing a configuration when a conversion memory is used for the conversion circuit 13.

In FIG. 5, a conversion circuit 13 includes an address conversion memory 131 in which information for address conversion is written, a data write / conversion memory 132 in which information for conversion is written when data is written, and data read. And a data bus for selecting the data write / conversion memory 132 or the data read / conversion memory 133 by switching the data bus when writing data and when reading data. Switching devices 134 and 135 are provided.

In the above configuration, the address of the microprocessor 12 accessing the volatile memory 14 is converted by the address conversion memory 131, and the converted address is output to the volatile memory 14.
The volatile memory 14 will be accessed non-linearly as shown in FIG. When writing the secret information, the data bus of the microprocessor 12 is connected to the address bus of the data write conversion memory 132 by the data bus switch 134, and the data bus of the data write conversion memory 132 is connected to the data bus switch. 135 connects to the data bus of the volatile memory 14. When reading the secret information, the data bus of the volatile memory 14 is connected to the address bus of the memory 133 for data reading and conversion by the data bus switch 135, and the data bus of the memory 133 for reading and converting data is switched to the data bus. The device 134 connects to the data bus of the microprocessor 12.

Therefore, each conversion memory 131,
By writing non-linear information in 132 and 133, it is possible to convert and access to more than a combination of address and data signal lines.

[0025]

As described above, according to the present invention, since the position of the secret information written in the volatile memory is unspecified, information that is a clue for decryption can be obtained from a plurality of read secret information. It can be difficult to give.

Further, according to the present invention, the means for arbitrarily converting the information of the address signal lines and the data signal lines is constituted by a switch. Access can be made by exchanging bit positions, so that even if the same secret information is written in each device, the information on the memory can be made different for each device up to the number of combinations of signal lines.

According to the present invention, secret information is stored in a non-linear space with respect to a volatile memory by using information in a conversion memory in which information for arbitrarily converting information on an address signal line and a data signal line is written. It can be stored and converted to more than a combination of signal lines to access the volatile memory.

[Brief description of the drawings]

FIG. 1 is a principle explanatory diagram in a case where secret information is converted and stored in a volatile memory at an arbitrary location by a method for countering the attack of deciphering secret information in Embodiment 1 of the present invention.

FIG. 2 is a block diagram of a second embodiment in which the method of the first embodiment of the present invention is realized by providing a conversion circuit on an address bus and a data bus connecting a volatile memory and a microprocessor;

FIG. 3 is a block diagram when a conversion circuit according to a second embodiment of the present invention is configured by a changeover switch;

FIG. 4 is a configuration diagram of a changeover switch according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration when a conversion memory is used for a conversion circuit in Embodiment 3 of the present invention;

[Explanation of symbols]

 10 Memory indicating the storage state of secret information before conversion 11 Volatile memory indicating storage state of secret information after conversion 12 Microprocessor 13 Conversion circuit 14 Volatile memory 15, 17 Address bus 16, 18 Data bus SWA0, SWA1 Address Data changeover switch SWD0, SWD1 data changeover switch 131 address conversion memory 132 data write conversion memory 133 data read conversion memory 134, 135 data bus switch

Claims (3)

[Claims] 1. A means for arbitrarily converting write information with respect to a volatile memory holding secret information, wherein the conversion means stores the secret information in a different location for each electronic device and each time the secret information is written to the volatile memory. A method for countermeasures against cryptanalysis of confidential information characterized by conversion and storage. 2. The conversion means comprises a switch for arbitrarily converting information of an address signal line and a data signal line and exchanging each signal line, and the switch switches the address signal line and the data signal line arbitrarily. 2. The method according to claim 1, wherein the attack is against a decryption attack of the secret information. 3. The conversion means comprises a conversion memory in which information for address signal lines and data signal lines is arbitrarily converted and information for replacing each signal line is written, and a non-linear conversion is performed by the information in the conversion memory. 2. The method according to claim 1, wherein the secret information is stored in the secret information.