JP2006304059A - Electronic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption even when data having different properties flows through the bus. <P>SOLUTION: Between a CPU 11 and a data bus 18, a coding system suitable for property of data among a coder 21, a decoder 23 or a coder 22, a decoder 24 is selected by controlling switches 25, 26 with a switching control unit 50. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electronic circuit that transmits and receives data by outputting encoded data on a bus, receiving the data on the bus, and decoding the data.

  In recent years, with the further miniaturization of semiconductor integrated circuits, the operation speed of semiconductor integrated circuits has also increased, and for this reason, the capacity of bus wiring through which data is transmitted and received tends to be relatively large. In addition, many functions are integrated in the semiconductor integrated circuit. Therefore, in an electronic circuit in which such a semiconductor integrated circuit is incorporated, there arises a problem that power consumption at the time of inversion of each bit constituting data flowing on a bus such as an address bus or a data bus increases. In order to solve this problem, a technique has been proposed in which data flowing on the bus is encoded to reduce the number of bit inversions and to reduce power consumption.

  For example, Non-Patent Document 1 proposes a Bus-invert encoding technique. In this technique, when transmitting data on the bus, if bits exceeding half the number of bits of the bus width are inverted, the data is not transmitted as it is, but all bits are inverted and transmitted. As a result, the number of inverted bits on the bus can always be suppressed to less than half of the bus width. When decoding on the receiving side, a signal line for transmitting a 1-bit signal indicating whether or not the data is inverted is added to the bus wiring, and on the receiving side, the 1-bit signal is confirmed and the data is received. If it is inverted, it is inverted again and the decoding process is performed. Such an encoding technique is such that the maximum number of bits to be inverted on the bus is less than half the number of bits of the bus width. There is a reduction effect.

  Non-Patent Document 2 proposes an ALBORZ (Address Level Bus Power Optimization) encoding technique. In general, the address signal transmitted through the address bus is frequently incremented (+1), and even in other cases, the displacement is frequently within a certain range (for example, −16 to +17). In such a case, the power consumption can be reduced by adopting the ALBORZ encoding technique.

  FIG. 3 is a diagram showing a conventional electronic circuit employing the ALBORZ encoding technique.

  A 32-bit address signal, which is a source word, is input to the register 101 and the subtractor 102 included in the electronic circuit 100 illustrated in FIG. The register 101 stores the previous address value. The subtracter 102 obtains a difference value (offset value) between the address value to be transmitted this time and the previous address value stored in the register 101, and outputs the difference value to the encoder 103.

  If the encoder 103 determines that the difference value does not fall within a certain range (here, −16 to +17), the encoder 103 transmits the address as it is to the address bus via the switch 104 without encoding. On the other hand, if it is determined that the difference value falls within a certain range, encoding is performed. Information indicating that encoding has been performed is sent to the flip-flop 105, and a code-on flag is output from the flip-flop 105. The code-on flag is transmitted through a 1-bit signal line added to the address bus. The encoder 103 converts the difference value of the address from the subtracter 102 into a code word shown in FIG.

  FIG. 4 is a diagram showing a difference value from the subtracter shown in FIG. 3 and a code word converted corresponding to the difference value.

  On the left side of FIG. 4, the difference values +1 and +2,..., +17, −1,. Further, on the right side of FIG. 4, codewords converted corresponding to these difference values +1 and +2,..., +17, −1,. Each of these code words has a 32-bit configuration. For example, when the code word “00000000h” corresponding to the difference value +17 shown in FIG. 4 is represented by 32 bits, “0000 0000 0000 0000 1000 0000 0000 0000” is obtained.

In this way, the sign of “1” is one or less, and the exclusive OR circuit 106 shown in FIG. To the address bus via. In this way, the number of bits to be inverted on the address bus is 0 bit when the address displacement is +1, and 1 bit when the address displacement is -16 to +17. Therefore, the power consumption caused by the displacement of the address signal flowing on the address bus can be reduced.
M.M. R. Stan and W.C. P. Burleson, “Bus-invert coding for low power I / O,” IEEE Trans. on VLSI Systems, vol. 3, pp. 49-58, Mar. 1995. Y. Aghagiri, F .; Fallah, M .; Pedram, ALBORZ: Address Level Bus Power Optimization, International Symposium on Quality Electronic Design, California, Mar. 2002.

  In an electronic circuit including a semiconductor integrated circuit whose use is determined, it is considered that the effect of reducing power consumption is high when an encoding technique suitable for the use is employed. However, recent high-performance semiconductor integrated circuits have specific characteristics because data having different characteristics (for example, data representing voice and data consisting of numerical information) flow on the bus in a mixed manner. When an encoding technique that has the effect of reducing power consumption is employed for data, there is a problem that the power consumption is not reduced or deteriorated for data having another property.

  In view of the above circumstances, an object of the present invention is to provide an electronic circuit that can reduce power consumption even when data having different properties flows on a bus.

The electronic circuit of the present invention that achieves the above object is an electronic circuit that transmits and receives data by outputting encoded data on a bus and receiving and decoding the data on the bus.
A plurality of types of encoding units that perform different types of encoding on the data; and
Depending on the nature of the data output on the bus, select any one of the above-mentioned multiple types of encoding units and cause the selected encoding unit to encode the data and output it on the bus And an encoding selection unit for performing the above operation.

  The electronic circuit of the present invention is an encoding unit selected according to the nature of data output on the bus, and the data is encoded and output on the bus. For this reason, even when data having different properties flow in a mixed manner on the bus, it is possible to perform an encoding process that suppresses power consumption for each of the data having different properties. Therefore, even when data having different properties flows on the bus, the power consumption can be reduced.

  Here, it is preferable that the encoding selection unit monitors the data flowing on the bus, determines the property of the data, and selects any one encoding unit according to the determination result. .

  In this way, it is possible to further reduce the power consumption for the data flowing on the bus as compared to the case of using a fixed encoding method.

  According to the electronic circuit of the present invention, power consumption can be kept small even when data having different properties flows on the bus.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram illustrating an electronic circuit according to a first embodiment of the present invention.

  The electronic circuit 1 shown in FIG. 1 encodes and outputs an address and data on the address bus 14 and the data bus 18, and receives and decodes the address and data on the address bus 14 and the data bus 18, thereby This is an electronic circuit for sending and receiving addresses and data. On the data bus 18, data having different properties (for example, data representing voice and data consisting of numerical information) flow together.

  The electronic circuit 1 includes a CPU 11, a RAM 12, and an input / output device 13.

  The electronic circuit 1 also encodes an address output from the CPU 11 and outputs it on the address bus 14. The electronic circuit 1 receives the address on the address bus 14, decodes it, and outputs it to the RAM 12. A decoder 16 and a decoder 17 that receives an address on the address bus 14, decodes it, and outputs it to the input / output device 13 are provided.

  Furthermore, in this electronic circuit 1, between the data bus 18 and the CPU 11, encoders 21 and 22 that perform different types of encoding on data, and a decoder 23 that performs different types of decoding on data. , 24 and switches 25, 26 are provided. The switchers 25 and 26 select one of the encoders 21 and 22 in accordance with the nature of the data output on the data bus 18, and send the data to the selected encoder. The data is encoded and output on the data bus 18. The switchers 25 and 26 select any one of the decoders 23 and 24 according to the property of the data input from the data bus 18, and decode the data to the selected decoder. And output to the CPU 11.

  Also, in this electronic circuit 1, between the data bus 18 and the RAM 12, encoders 31 and 32 that perform different types of encoding on data, and a decoder 33 that performs different types of decoding on data. , 34 and switching devices 35, 36. The switchers 35 and 36 select one of the encoders 31 and 32 in accordance with the nature of the data output on the data bus 18 and transfer the data to the selected encoder. The data is encoded and output on the data bus 18. The switchers 35 and 36 select any one of the decoders 33 and 34 according to the property of the data input from the data bus 18 and decode the data to the selected decoder. And output to the RAM 12.

  Further, in this electronic circuit 1, between the data bus 18 and the input / output device 13, encoders 41 and 42 for encoding data of different types, and data of different types of decoding are applied. Decoders 43 and 44 and switchers 45 and 46 are provided. The switchers 45 and 46 select one of the encoders 41 and 42 according to the nature of the data output on the data bus 18 and transfer the data to the selected encoder. The data is encoded and output on the data bus 18. The switchers 45 and 46 select any one of the decoders 43 and 44 according to the property of the data input from the data bus 18 and decode the data to the selected decoder. And output to the input / output device 13. Here, the set of the encoder 21 and the decoder 23, the set of the encoder 31 and the decoder 33, and the set of the encoder 41 and the decoder 43 are a set adopting the ALBORZ encoding method. On the other hand, the set of the encoder 22 and the decoder 24, the set of the encoder 32 and the decoder 34, and the set of the encoder 42 and the decoder 44 are a set adopting the bus-invert encoding method.

  Further, the electronic circuit 1 is provided with a switching control device 50 that controls switching of the above-described switches 25, 26, 35, 36, 45, and 46 according to an instruction from the outside or a software executed by the CPU 11. ing. Here, the switches 25, 26, 35, 36, 45, and 46 and the switching control device 50 correspond to an example of the encoding selection unit according to the present invention.

  In the electronic circuit 1 configured as described above, the address output from the CPU 11 is encoded by the encoder 15, decoded by the decoders 16 and 17, and output to the RAM 12 and the input / output device 13. As the encoding method, the aforementioned ALBORZ encoding method or the like can be used.

  Since data flowing on the data bus 18 is bidirectional, for example, between the CPU 11 and the data bus 18, an encoder 21 and a decoder 23 (or an encoder 22 and a decoder) according to the direction of the data. 24) is switchably controlled. Also, as described above, there are two sets of the encoder 21 and the decoder 23 and the pair of the encoder 22 and the decoder 24 between the CPU 11 and the data bus 18, Encoding and decoding functions according to different encoding schemes are provided. The encoding method is selected by the switchers 25 and 26. As described above, the switching control device 50 controls the switching units 25 and 26 according to an external instruction or a software instruction executed by the CPU 11. For example, audio signal data that has not been encoded has a characteristic that the change in value before and after the time axis is not large. Therefore, by performing encoding processing based on the difference between the previous and subsequent values by the ALBORZ encoding method Power consumption in the data bus 18 can be reduced. When random data, which is data having other properties, flows on the data bus 18, power consumption can be reduced by the bus-invert encoding method. In this way, the switching control device is externally or by software so that the former encoding method is adopted when audio data is flowing, and the latter encoding method is adopted when other random data is flowing. Give instructions to 50.

  As described above, the electronic circuit 1 of the present embodiment is an encoder selected according to the nature of the data output on the data bus 18, encodes the data, and outputs the encoded data on the data bus 18. is there. For this reason, even when data having different properties flow together on the data bus 18, it is possible to perform an encoding process that suppresses power consumption for each data having different properties. Therefore, even when data having different properties flows on the data bus 18, the power consumption can be reduced.

  FIG. 2 is a diagram illustrating an electronic circuit according to a second embodiment of the present invention.

  The same components as those of the electronic circuit 1 shown in FIG. 1 are denoted by the same reference numerals, and different points will be described.

  The electronic circuit 2 shown in FIG. 2 is different from the electronic circuit 1 shown in FIG. 1 in that a feature extractor 61, a threshold generator 62, a comparator 63, decoders 71 and 72, and switches 73 and 74 are added. Is different. Here, the feature extractor 61, the threshold generator 62, the comparator 63, the decoders 71 and 72, the switchers 25, 26, 35, 36, 45, 46, 73 and 74, and the switch control device 50 are included in the present invention. This corresponds to another example of the encoding selection unit.

  Based on the output of the switching control device 50, the switchers 73 and 74 select the decoder of the encoding method currently in use from the decoders 71 and 72. As a result, the original data before encoding the data flowing on the data bus 18 is output from the switch 73.

  The feature extractor 61 monitors the data output from the switch 73, extracts the feature of the data, and outputs a value corresponding to the extracted feature.

  The threshold generator 62 generates and outputs a predetermined value.

  The comparator 63 compares the value from the feature extractor 61 with the value from the threshold generator 62 and outputs the comparison result to the switching control device 50.

  For example, when audio signal data is transmitted / received between the CPU 11 and the data bus 18, the audio signal data has a characteristic that the value does not change greatly before and after the time axis, so that the feature extractor 61 is relatively free. A small value is output. The comparator 63 compares this small value with the value from the threshold generator 62 and outputs a signal as a comparison result, that is, a signal indicating that the ALBORZ encoding method is adopted, to the switching control device 50. In the switching control device 50, based on this signal, the switches 25 and 26 select a set of the encoding 21 and the decoder 23.

  Further, when random data is transmitted and received between the CPU 11 and the data bus 18, a relatively large value is output from the feature extractor 61. The comparator 63 compares this large value with the value from the threshold generator 62 and outputs a signal indicating that the bus-invert encoding method is adopted to the switching control device 50. In the switching control device 50, based on this signal, the switches 25 and 26 select a set of the encoding 22 and the decoder 24. By doing so, the power consumption for the data flowing on the data bus 18 can be further reduced.

It is a figure which shows the electronic circuit of 1st Embodiment of this invention. It is a figure which shows the electronic circuit of 2nd Embodiment of this invention. It is a figure which shows the electronic circuit which employ | adopted the conventional ALBORZ encoding technique. It is a figure which shows the difference value from the subtractor shown in FIG. 3, and the codeword converted corresponding to the difference value.

Explanation of symbols

1, 2 Electronic circuit 11 CPU
12 RAM
13 I / O device 14 Address bus 15, 21, 22, 31, 32, 41, 42 Encoder 16, 17, 23, 24, 33, 34, 43, 44, 71, 72 Decoder 25, 26, 35, 36, 45, 46, 73, 74 Switching device 50 Switching control device 61 Feature extractor 62 Threshold generator 63 Comparator

Claims (2)

In an electronic circuit that transmits and receives data by outputting encoded data on a bus and receiving and decoding the data on the bus,
A plurality of types of encoding units that perform different types of encoding on the data; and
Depending on the nature of the data output on the bus, one of the plurality of types of encoding units is selected and the selected encoding unit encodes the data and outputs it on the bus An electronic circuit comprising: an encoding selection unit that causes   The encoding selection unit monitors data flowing on a bus, determines the property of the data, and selects any one encoding unit according to the determination result. Item 2. The electronic circuit according to Item 1.

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