JPH114389A - Release timing control circuit for freeze circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid a deteriorated freeze image from being displayed by checking again recovery of a received detection pulse after the lapse of a prescribed time from a rising point of time of the received detection pulse and releasing freeze after confirming the recovery of a received radio wave. SOLUTION: A reception detection pulse 5 is given respectively to a 34 ms delay circuit 41 and a gate circuit 42 respectively. A pulse delayed by 34 ms from the reception detection pulse 5 given to the 34 ms delay circuit 41 is outputted from the circuit 41. Then freeze is not released automatically singly at the rising point of time of the pulse delayed by 34 ms and the reception state of the reception detection pulse 5 is checked again at a rising point of time by a gate circuit 42 of the next stage. That is, when the reception radio wave is recovered, the freeze is released and when deteriorated, the freezing is continued. In this case, in order to confirm the recovery of the received radio wave for pluralities of number of times, the display of the deteriorated freeze image is accurately avoided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display circuit, and more particularly to a freeze circuit for displaying one screen of a displayed moving image as a still image.

[0002]

2. Description of the Related Art When a television image is received while a vehicle is running using a vehicle-mounted BS antenna or the like, a good received image can be obtained in a state where there is no obstacle around the satellite. However, when passing near a high-rise building or traveling in a tunnel, the radio waves are cut off by them, and sometimes the reception screen often looks like a sandstorm.

An effective countermeasure for such a case is a "freeze circuit". The freeze circuit detects the interruption of the received radio wave as described above, and upon detection, displays one of the good received images immediately before the interruption occurs as a still image.

FIG. 1 schematically shows an example of the operation of a conventional freeze circuit. In FIG. 1A,
The delay circuit (DLY) 1 is composed of a delay memory for giving a time margin from when a received radio wave starts to deteriorate to when it is detected. The gate circuit 2 controls whether or not the received image data in the delay circuit 1 is transferred to the screen display frame memory 3 at the next stage.

The gate circuit 2 is turned on / off by a control signal from a control circuit (not shown) for detecting deterioration of a received image. The frame memory (FRM) 3
Temporarily stores the received data for each screen. In the case of the NTSC system, since 30 screens are displayed per second, it takes about 33 ms (30 sheets / second) to receive one screen. Finally, the contents of the frame memory 3 are displayed on the display 4.

FIG. 1A shows a case where the reception condition of the radio wave is good. The gate circuit 2 is turned on, and the image data of the delay circuit 1 remains in the next stage after a predetermined delay. The data is transferred to the frame memory 3. FIG. 1 (b)
1 to (e), the radio wave receiving condition shown in FIG. 1A is temporarily deteriorated from the good receiving condition ((b) and (c)), and returns to the original good receiving condition again ((b) and (c)). (D) and (e) show a series of freeze circuit operations.

That is, in FIG. 1B, the delay circuit 1
First, the deterioration of the received image starts, and when the degree of deterioration becomes equal to or less than a predetermined value (after the elapse of time), the control circuit determines that the image has deteriorated and turns off the gate circuit 2 (H → L).
Accordingly, thereafter, as shown in FIG. 1C, only the received data of the delay circuit 1 is updated, and the image data in the normal frame memory 3 immediately before the deterioration judgment is made is displayed as a still image on the display 4. Will be displayed.

Next, when the recovery of the received image is detected as shown in FIG. 1D, the control circuit elapses more than the delay time of the delay circuit 1 as shown in FIG. 1E. And then turns on the gate circuit 2 (L →
H). As the time elapses, the deteriorated image remaining in the reception screen after the detection of the recovery is wiped out, and the transfer of a favorable moving image is restarted after the gate circuit 2 is turned on.

[0009]

The above-described conventional freeze circuit works well in most cases. However, the radio wave reception state does not always last for a certain period of time. For example, while the radio wave cutoff state continues for a moment (34 msec or less)
May recover, and then immediately return to the previous shut-off state. In this case, the freeze screen is a mixture of “good screen” and “sand storm”, and in the worst case, the vertical synchronization of the screen is lost and the screen flow may occur. there were.

FIG. 2 schematically shows an example of occurrence of a problem in the freeze circuit. 2 (f-1) is FIG. 1 (d), FIG. 2 (f-2) is FIG. 1 (e), and FIG. 2 (f-3) is FIG. 1 (b). Corresponds to each state.

FIG. 2 (f-1) shows a state in which the recovery of the received image is detected and the waiting for one screen reception time or more has elapsed, and is (d) itself in FIG. However, in (f-2) of FIG. 2, the deteriorated image is received again after the lapse of the one-screen reception time, and the image is deteriorated in the frame memory 3 by turning on (L → H) the gate circuit 2 after the lapse of the time. Image data is transferred.

Further, as shown in FIG. 2 (f-3),
When the degree of image deterioration becomes equal to or less than a predetermined value (after the elapse of the time), the gate circuit 2 is turned off again (H → L) and returns to the initial freeze state. As a result, the deteriorated still screen is displayed continuously until the next received video is restored.

FIG. 3 shows a C / C in a vehicle-mounted BS receiver.
It shows an example of the N value and the freeze release timing. In an in-vehicle BS receiver, a C / N value representing a ratio between a carrier level and a noise level received for freeze control is generally used, and the control circuit turns on the gate circuit 2 based on the value. / Off control. In general, the C / N value of a clean screen is 15 dB or more, and a threshold (VTH) for on / off control of the gate circuit 2 shown in FIG. 3A is set to, for example, 7 dB.

In FIG. 3A, when the received image starts to deteriorate and the C / N value decreases, the received signal becomes low at the threshold value (VTH) in FIG. 3B. FIG.
(C), the change to the low level signal indicates the start of the freeze state. Thereafter, when the C / N value rises and exceeds the threshold value, the reception signal shown in FIG. 3B becomes a high level. Then, as shown in FIG. 3C, the freeze is released when the delay time of the delay circuit 1 described above has elapsed from that point.

When the freeze is released, the C / N
There is no problem if the value is restored as shown by the solid line in FIG. 3A, but if the C / N value has deteriorated again as shown by the dotted line in FIG. The situation described above will be reached, and the degraded still screen will be displayed until the received video is restored next.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a freeze circuit release timing control circuit that minimizes display of a deteriorated freeze screen.

[0017]

According to the present invention, there is provided a freeze circuit for detecting deterioration or interruption of a received image signal and displaying a good screen before the detection as a still image.
A detection circuit for detecting normality / deterioration of a received image signal, a first memory circuit for delaying the received image signal, a second memory circuit for storing an image signal displayed on a display device in screen units, and A control circuit for controlling the transfer or writing of the image signal to the second memory circuit in accordance with the normal / deterioration detection signal from the detection circuit, wherein the control circuit is configured to control the second signal by the deterioration detection signal from the detection circuit. The transfer to or writing to the memory circuit is stopped, and only when a normal signal is detected when at least one screen of image transfer or writing time to the second memory circuit has elapsed since the time of generation of the normal detection signal. A control circuit is provided for giving a release timing of a freeze circuit for releasing the stop of transfer or writing.

Further, according to the present invention, the control circuit further comprises a control circuit for controlling all of the control circuits at predetermined time intervals at least during a time for transferring or writing an image of one screen to the second memory circuit from the time when the normal detection signal is generated. The stop of the transfer or writing is released only when a normal signal is detected. The control circuit may further include at least one of the second memory circuit and
When the deterioration detection signal is detected during the image transfer or write time for one screen, the transfer or write is performed at least after the image transfer or write time for one screen to the second memory circuit from the time when the normal detection signal is generated thereafter. Release the stop of writing.

Further according to the invention, the control circuit comprises:
Stopping transfer to or writing to the second memory circuit by a deterioration detection signal from the detection circuit,
Thereafter, each time a normal detection signal is generated, counting of image transfer or writing time for at least one screen with respect to the second memory circuit is started from the time of occurrence, and the transfer or writing is stopped when the time has elapsed. To release.

[0020]

4 and 5 show a vehicle-mounted B equipped with a freeze circuit release timing control circuit according to the present invention.
1 shows an embodiment of an S receiver. FIG. 4 shows a block configuration of an in-vehicle BS receiver, and FIG. 5 shows a basic configuration example of a freeze circuit release timing control circuit according to the present invention. Hereinafter, a description will be given mainly of a portion related to the present invention.

In FIG. 4, a BS radio wave from a satellite is received and amplified by a front end 25 and an input amplifier 29.
The image signal is detected by the video detection circuit 30 and A / A
After being converted into a digital signal by the D converter 31, it is input to the memory 32. Note that the memory 32 is provided in FIG.
Of the delay circuit 1 of FIG.

The image data in the memory 32 operates as a delay circuit and is written in the second frame memory 33. The write control signal controls the write timing, and realizes the function of the gate circuit 2 in FIG. The D / A converter 34 converts the image data in the second frame memory 33 into an analog signal, and the video output is displayed on a display.

The clock generator 35 supplies 14.3 MHz obtained by multiplying the crystal oscillation frequency 3.58 MHz by 4 to the above blocks 31 to 34 as an operation reference clock. A clock obtained by dividing the frequency by the frequency dividing circuit 36 is supplied as a detection clock.

The amplified signal received from the input amplifier 29 is detected by a band-pass filter 24 having a center frequency of 12 MHz to detect its carrier-noise component, and thereafter passes through a noise amplifier 23, a peak detection circuit 22, and a non-linear amplifier 21. A C / N detection voltage (see FIG. 3A) corresponding to the above-mentioned C / N value is given. The microcomputer circuit 3 of FIG.
Reference numeral 9 corresponds to the control circuit described above, and generates a reception detection pulse (see FIG. 3B) by comparing the C / N detection voltage with a reference threshold voltage (VTH) provided inside the circuit. I do.

FIG. 5 shows first to fourth basic configuration examples of a freeze circuit release timing control circuit according to the present invention. In FIG. 5, the signals of and are respectively connected to the signals of the same numbers in FIG. 6 to 9 are operation timing diagrams of the respective components in FIG. 5, and FIGS. 10 to 12 show specific circuit examples of a freeze circuit release timing control circuit.

In the first example shown in FIG. 5A, the reception detection pulse (corresponding to FIG.
And the gate circuit 42. FIG. 6 shows the operation timing of this example. The 34 ms delay circuit 41 outputs the same pulse delayed () by 34 ms from the input reception detection pulse.

In this embodiment, the freeze is not automatically released at the rising edge of the 34 ms delayed pulse, but the receiving state of the reception detection pulse is checked again at the rising edge in the next gate circuit 42. . That is, as shown in the upper part of FIG. 6, if the recovery (solid line) has occurred, the freeze is released, and if the recovery has been made (dashed line), the freeze is continued.

FIG. 10 shows an example in which the gate circuit 42 is constituted by using an AND gate circuit 51. Since the output does not become 1 unless both the reception detection pulse and the 34 ms delay pulse become 1, the freeze release timing is delayed by 34 ms. If the reception time is 34 ms or less, the output remains at 1 and the freeze is not released.

Next, a second example of FIG. 5B will be described. In this example, the reception detection pulse is input to the cyst register circuit 43 of the next stage. The shift register circuit 4
3, a clock of several ms is inputted from the frequency dividing circuit of FIG. FIG. 7 shows the operation timing of this example.

The shift register circuit outputs reception detection pulses sequentially delayed by a predetermined time according to the clock. In FIG. 7, as an example, the reference clock 5 m
s FF third stage output (10 to 15 ms delay), fifth stage output (20 to 25 msec delay), eighth stage output (35 to
An example of a signal with a delay of 40 msec) is shown. The gate circuit 42 of the present example checks the level of the original reception detection pulse a plurality of times at each rising point of each of the delay pulses. Then, when all of them are at the high level, an instruction is given to release the freeze.

FIG. 11 shows an example of the circuit of FIG. In FIG. 11, the original reception detection pulse is three clocks of the reference clock (for example, 5 ms), five clocks,
The signal delayed by eight clocks is input to the AND gate circuit 55 together with the original reception detection pulse. With this configuration, 34 msec from the reception detection at the time of freeze
Even after the reception state c, the detection accuracy in the case where the interruption is performed during the reception state is improved.

The example shown in FIG. 5C is obtained by further adding a one-shot multi-circuit 45 to the example shown in FIG.
5A detects only a delay time of 34 ms from the rise time of the original reception detection pulse, whereas if a pulse-like noise or a chattering signal is generated during that time, an additional 34 ms is used as a reference. It is a delay. FIG. 8 shows an example of the operation timing of the present example.

In FIG. 5D, a noise signal or the like generated further during the operation of the one-shot multi-circuit 45 cannot be detected in the example of FIG.
And a retriggerable one-shot delay circuit in place of the one-shot multi-circuit 45. As shown in the operation timing of FIG. 9, according to the present example, all the rising points of the original reception detection pulse are used as starting points.
Since a delay of 4 ms is obtained, it is possible to reliably release the freeze.

The retriggerable one-shot circuit may be an analog type as shown in FIG. 12 or a digital circuit.

[0035]

As described above, according to the present invention, the following effects are produced. (1) The recovery of the reception detection pulse is checked again after a lapse of a predetermined time (one screen reception time or more) from the rise of the reception detection pulse, and the freeze is released after confirming the recovery of the received radio wave. The display of the freeze screen can be avoided.

(2) Since the recovery of the received radio wave is confirmed a plurality of times within the predetermined time, it is possible to more accurately avoid the display of the deteriorated freeze screen. (3) Further, the deterioration of the received radio wave generated at an arbitrary timing within the predetermined time is detected, and then the detection is performed for a predetermined time (1
To release the freeze after the screen reception time has elapsed)
The display of the deteriorated freeze screen can be reliably avoided.

[Brief description of the drawings]

FIG. 1 is a diagram schematically showing an example (1) of an operation of a conventional freeze circuit.

FIG. 2 is a diagram schematically illustrating an example (2) of an operation of a conventional freeze circuit.

FIG. 3 is a diagram illustrating an example of a C / N value and a freeze release timing in a vehicle-mounted BS receiver.

FIG. 4 is a diagram showing an embodiment (1) of an in-vehicle BS receiver including a freeze circuit release timing control circuit according to the present invention;

FIG. 5 is a diagram showing an embodiment (2) of an in-vehicle BS receiver including a freeze circuit release timing control circuit according to the present invention;

FIG. 6 is a diagram showing an example of the operation timing of FIG.

FIG. 7 is a diagram showing an example of the operation timing of FIG. 5 (b).

FIG. 8 is a diagram showing an example of the operation timing of FIG. 5 (c).

FIG. 9 is a diagram showing an example of the operation timing of FIG. 5 (d).

FIG. 10 is a diagram illustrating an example of the circuit of FIG. 6;

FIG. 11 is a diagram showing an example of the circuit of FIG. 7;

FIG. 12 is a diagram illustrating an example of the circuit of FIG. 9;

[Explanation of symbols]

 1. Delay circuit 2. Gate circuit 3. Frame memory 4. Display

Claims (4)

[Claims] 1. A freeze circuit for detecting deterioration or interruption of a received image signal and displaying a good screen before the detection as a still image, a detection circuit for detecting normality / deterioration of the received image signal, A first memory circuit for delaying the read image signal, a second memory circuit for storing the image signal displayed on the display device in screen units, and the second memory according to a normal / deterioration detection signal from the detection circuit. A control circuit for controlling transfer or writing of an image signal to a circuit, wherein the control circuit stops transfer or writing to the second memory circuit by a deterioration detection signal from the detection circuit, and then detects normality. At least when an image transfer or writing time for one screen to the second memory circuit elapses from the signal generation time. Release timing control circuit freeze circuit and cancels the transfer or stop writing only when it detects a normal signal. 2. The control circuit further detects all normal signals at a predetermined time interval at least during a time for transferring or writing an image for one screen to the second memory circuit from the time when the normal detection signal is generated. 2. The control circuit according to claim 1, wherein the stop of the transfer or the writing is released only at a time. 3. The control circuit according to claim 1, further comprising: when detecting a deterioration detection signal during at least one screen image transfer or writing time to the second memory circuit from the time when the normal detection signal is generated, the control circuit detects a subsequent normal detection signal. 2. The control circuit according to claim 1, wherein the stop of the transfer or the writing is released at least after an image transfer or a writing time for one screen to the second memory circuit from the time when the detection signal is generated. 4. A freeze circuit for detecting deterioration or interruption of a received image signal and displaying a good screen before the detection as a still image, a detection circuit for detecting normality / deterioration of the received image signal, A first memory circuit for delaying the read image signal, a second memory circuit for storing the image signal displayed on the display device in screen units, and the second memory according to a normal / deterioration detection signal from the detection circuit. A control circuit for controlling transfer or writing of an image signal to a circuit, wherein the control circuit stops transfer to or writing to the second memory circuit by a deterioration detection signal from the detection circuit, and thereafter detects normality. Each time a signal is generated, the time of image transfer or writing time for at least one screen with respect to the second memory circuit from the point of generation is counted Start the cement, release timing control circuit freeze circuit and cancels the transfer or stop writing when the time has elapsed.