JPH03138587A - Ultrasonic detector - Google Patents

Abstract

PURPOSE:To preclude malfunction and misdetection due to a voltage drop by stopping at least the operation of a transmitting and receiving circuit system in a period wherein abnormality of a power source which is caused by the transmitting and receiving circuit system is detected. CONSTITUTION:If an instantaneous power failure, etc., occurs to cause the voltage of an external power source 4 to drop greatly, the output voltage of a 2nd constant voltage circuit 3 drops almost to 0V and an abnormality detection block 5 detects that and outputs an abnormality signal (a). Then a control block 6 stops the output of a clock signal in response to the signal (a) to stop transmitting and receiving operation and a storage block 7 holds recording contents and maintains its output state. The output voltage of a 1st constant voltage circuit 2, on the other hand, drops gradually because of a capacitor C1, so the holding operation of the block 7 is carried out throughout the output period of the signal (a) and a high signal is outputted 17. Then when the abnormal state ends and the voltage of the circuit 3 recovers to a normal voltage, a normalcy signal is outputted 5 and the output of the clock signal is restarted 6; and the transmitting and receiving operation is restarted and the block 7 is released from the holding state.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an ultrasonic detector that detects the presence or absence of an object by transmitting and receiving ultrasonic pulses, and particularly relates to an ultrasonic detector that detects the presence or absence of an object by transmitting and receiving ultrasonic pulses. A sound wave detector opens.

(Prior Art) Normally, an ultrasonic detector uses a wave transmitting/receiving circuit system to repeatedly transmit and receive pulses to detect an object, and a control circuit system controls the operation of the wave transmitting/receiving circuit system. I have to.

In such an ultrasonic detector, a power backup capacitor is connected to the control circuit system in order to prevent malfunction due to a drop in power supply voltage caused by a momentary power outage or the like.

(Problems to be Solved by the Invention) On the other hand, since the power consumption of peripheral circuits such as the above-mentioned wave transmitting/receiving circuit system is relatively large, it has been difficult to take measures using backup capacitors. Therefore, there is a risk that a drop in power supply voltage caused by a momentary power outage or the like may cause malfunctions such as failure to perform wave transmission or wave reception operations and failure to detect objects.

The present invention has been made in view of the above problems, and an object of the present invention is to provide an ultrasonic detector that can prevent false detections due to instantaneous power outages, etc.

(Means for Solving the Problems) The present invention includes a wave transmitting/receiving circuit system that detects an object by transmitting and receiving ultrasound pulses in return, and a control circuit system that controls the operation of the wave transmitting/receiving circuit system. In the ultrasonic detector, an abnormality detecting means detects that an abnormality has occurred in the power supply for the wave transmitting/receiving circuit system, and at least the operation of the wave transmitting/receiving circuit system is stopped during the period when the abnormality is detected. It is equipped with operation stopping means.

[Effect]

According to the ultrasonic detector with the above configuration, when an abnormality occurs in the power supply for the wave transmitting/receiving circuit system due to a momentary power outage, at least the operation of the wave transmitting/receiving circuit system stops during a period when it becomes difficult to maintain normal wave transmitting/receiving operation. be done.

〔Example〕

FIG. 1 is a block diagram of a first embodiment of an ultrasonic detector according to the present invention.

The power supply block 1 has a first constant voltage circuit 2 and a second constant voltage circuit 3, and receives power from an external power supply 4, for example, ACI OOV.
It supplies commercial voltage or a predetermined DC voltage at a constant voltage. That is, the first constant voltage circuit 2 converts the voltage from the external voltage m4 into a DC voltage of, for example, 5V and supplies it to an abnormality detection block 5, a control block 6, and a memory block 7, which will be described later. In addition, a diode D1 and a backup capacitor C1 are connected to the input side of the first constant voltage circuit 2, so that even if a sudden voltage drop occurs in the external power supply 4 due to a momentary power outage, etc. (FIG. 2, waveform j),
The output voltage of the first constant voltage circuit 2 is made to decrease only gradually (FIG. 2, waveform Q). The second constant voltage circuit 3 converts the voltage from the external power supply 4 into a DC voltage of, for example, 8V (FIG. 2, waveform k), and transmits and receives signals to devices other than the abnormality detection block 5, control block 6, and memory block 7. It supplies the circuit system.

The abnormality detection block 5 is supplied with power from the first constant voltage circuit 2, and detects whether the output voltage of the second constant voltage circuit 3 is lower than the set voltage and outputs it to the control block 6 and the memory block 7. . That is, the comparator 51 compares the output voltage from the second constant voltage circuit 3 with the set voltage of a set voltage section 52 consisting of, for example, an internal battery, so that the output voltage from the second constant voltage circuit 3 is equal to the set voltage. When the voltage is higher than the set voltage, a low signal is output as a normal signal, while a high signal is output as an abnormal signal (waveform a in Figure 2) during a period when the output voltage from the second constant voltage circuit 3 is lower than the set voltage. This is what is output.

The control block 6 is supplied with power from the first constant voltage circuit 2 and outputs a clock signal (waveform b in FIG. 2) for transmitting and receiving timing to the transmitting gate circuit 9 and the receiving gate circuit 10. It is something. Further, when the control block 6 receives the abnormality signal a from the abnormality detection block 5, it stops outputting the clock signal S. Oscillation circuit 8
oscillates at a preset frequency, for example 4QKHz, and outputs it to the AND circuit 11. The wave transmission gate circuit 9 outputs a wave transmission gate pulse (waveform C in FIG. 2) of a predetermined width to the AND circuit 11 in synchronization with the clock signal. The AND circuit 11 outputs the logical product of the signals from the oscillation circuit 8 and the wave transmission gate circuit 9. That is, the AND circuit 11 outputs a burst wave signal (waveform d in FIG. 2) during the input period of the transmission gate pulse C. The transmitted and driven circuit 12 amplifies the power of the burst wave signal d and excites the transducer 13.

The transducer 13 is composed of an ultrasonic transducer or the like, and converts the burst wave signal d from the wave transmission drive circuit 12 into an ultrasonic pulse and transmits the wave, and receives reflected waves returning from an object. .

The amplifier circuit 14 amplifies the reflected wave signal (waveform e in FIG. 2) from an object received by the transducer 13. The detection circuit 15 performs envelope detection of the signal from the amplifier circuit 14, and outputs a signal of a certain level or higher from the detected signal to the AND circuit 16 as a received signal as it is or after pulse shaping. Yes (Figure 2, waveform f)
. The reception gate circuit 10 delays the clock signal from the control block 6 and outputs a reception gate pulse (waveform 0 in FIG. 2) having a predetermined width to the AND circuit 16. When the reception signal f from the detection circuit 15 is input within the input period of the reception gate pulse q from the reception gate circuit 10, the AND circuit 16 generates a high signal (waveform h in FIG. 2).
is output to the storage block 7.

The memory block 7 is supplied with power from the first constant voltage circuit 2, and when a normal signal is input from the abnormality detection block 5, during the input period of pulse 0 from the reception gate circuit 10 to the reception gate circuit 10, When a high signal is input from the AND circuit 16, the output is set to high (waveform i in FIG. 2).

Furthermore, when a high signal is not input from the AND circuit 16 within the input period of the reception gate pulse q, the memory block 7 maintains a low output. Roughly speaking, the storage block 7 can retain the stored contents and its output during the input period of the abnormality signal a from the abnormality detection block 5.

The output circuit 17 is composed of a relay or the like, and outputs the output signal of the memory block 7 to a display device (not shown) or the like.

Next, the operation of the first embodiment will be explained using FIG. 2.

When the f13i wave pulse D is transmitted from the transducer 13 and reflected by a distant object, for example, this reflected wave signal "1" is received by the transducer 13 and then detected by the detection circuit 15. Since this detection signal F1 is outside the period of the reception gate pulse G1 from the transfer gate circuit 10, no output is sent from the AND circuit 16, and the output of the memory block 7 remains low.

On the other hand, when the ultrasonic pulse D is reflected by an object at a closer distance, for example, a reflected wave signal E2) and a detected signal @F2 are output from the detection circuit 15. This detected signal F2 is the received signal F2.
- Since it is within the period of pulse G2, the AND circuit 16 outputs the pulse signal H1, and the memory block 7 outputs a high signal.

After this, an abnormality such as a momentary power outage occurs in the external power source 4 due to lightning if it is a commercial power source, or an ignition switch turned on or an overload if it is a car battery, at time 11.
As shown in waveform j in Fig. 2, the voltage of the external power supply 4 is approximately O.
When V decreases significantly, the output voltage from the second constant voltage circuit 3 decreases to approximately OV, as shown by waveform k in FIG.

This drop in the output voltage of the second constant voltage circuit 3 is detected by the abnormality detection block 5, and the abnormality detection block 5 outputs an abnormality signal A.

The control block 6 stops outputting the clock signal due to this abnormal signal Δ, thereby stopping the wave transmitting and wave receiving operations. On the other hand, the recorded contents of the memory block 7 are retained by the abnormal signal A, and the output state of the memory block 7 is maintained as shown by waveform i in FIG. Also, the waveform C in Figure 2
As shown in FIG. 2, since the output voltage of the first constant voltage circuit 2 is asymptotically reduced by the capacitor C1, the operation of holding the recorded contents of the memory block 7 is continued during the output period of the abnormal signal A. That is, a high signal from the memory block 7 is outputted to a display device or the like through the output circuit 17.

Then, when the abnormal state ends at time t2 and the voltage of the second constant voltage circuit 3 returns to normal voltage, the abnormality detection block 5
A normal signal is output from. Therefore, the output of the clock signal from the control block 6 is restarted, the wave transmitting and wave receiving operations are restarted, and the holding state of the memory block 7 is released. For example, when an ultrasonic pulse D2 is transmitted and a reflected wave signal F3 reflected by a distant object is detected, this detected signal F3 falls outside the period of the reception gate pulse G3. The AND circuit 16 remains at a low output, and the memory block 7 inverts its output to low.

As described above, in the first embodiment, when an abnormality in which the output voltage of the second constant voltage circuit 3 significantly decreases is detected, the wave transmitting and wave receiving operations are immediately stopped, and the recorded contents of the memory block 7 are retained. be done. Then, when the second constant voltage circuit 3 returns to normal voltage, the wave transmitting and wave receiving operations are resumed, and the holding state of the memory block 7 is released. Therefore, false detection can be prevented during the suspension period of wave transmission and wave reception operations.

Next, a second embodiment of the ultrasonic detector according to the present invention will be described using FIG. 3. Components in the figure with the same numbers as in FIG. 1 have the same functions. Second
This embodiment is obtained by adding an abnormality detection gate circuit 18 and an AND circuit 19 to the first embodiment.

0 The abnormality detection gate circuit 18 detects the receiving gate pulse q from the rising edge of the clock signal S from the control block 6.
It outputs an abnormality detection gate pulse that remains high for a period up to the falling point of the signal (waveform m in FIG. 4). The AND circuit 19 is connected to the abnormality detection block 5 and the above abnormality detection block 1.
- Outputs the logical product of the signals from the circuit 18 to the control block 6 and the memory block 7 (Fig. 4, waveform n
).

Next, the operation of the second embodiment will be explained using FIG. 4.

When the ultrasonic pulse D is transmitted from the transducer 13 and reflected by a nearby object, for example, this reflected wave is transmitted to the transducer 13.
The wave is detected after being received by the When this detection signal F4 is within the period of the reception gate pulse G4, the output of the memory block 7 becomes high.

After that, when an abnormality occurs at time t3, a decrease in the output voltage of the second constant voltage circuit 3 is detected by the abnormality detection block 5, and as shown in waveform a in FIG.
An abnormality signal A1 is output from. If the abnormality detection pulse M1 is input to the AND circuit 19 during the period in which the abnormality signal A1 is generated,
As shown by waveform n in FIG. 4, a high signal N1 is output from the AND circuit 19. This high signal N1 causes the control block 6 to stop outputting the clock signal, thereby stopping the wave transmitting and receiving operations. On the other hand, the storage block 7 retains the recorded contents by the high signal N1, and the high signal from the storage block 7 is outputted through the output circuit 17 to a display device or the like.

Then, when the abnormal state ends at time t4 and the voltage of the second constant voltage circuit 3 returns to normal voltage, the output of the AND circuit 19 becomes low, and the wave transmitting and wave receiving operations are restarted again. Then, when a reflected wave is received outside the period of the reception gate pulse G5 (detection signal F5), the memory block 7 inverts its output to low.

After this, if an abnormality occurs at time t5 outside the period of received wave G1 to pulse G5, the abnormality detection block 5 outputs an abnormality signal A2. During the input period of this abnormal signal A2, the reception gate pulse G5 is not input to the AND circuit 19, so the AND circuit 19
The output of will remain low. Therefore, the control block 6 and the storage block 7 continue to operate normally during the momentary power outage. That is, the memory block 7 outputs a low signal.

Then, when the abnormal state ends at time t6 and the voltage of the second constant voltage circuit 3 returns to normal voltage, the ultrasonic pulse D is transmitted, and for example, the reflected wave reflected from a nearby object is transmitted. Waves are received. Since this detection signal F6 falls within the period of the reception gate pulse G6, the output of the memory block 7 becomes high, and a high signal is output from the output circuit 17.

In this way, in the second embodiment, the operation is not changed even if an abnormality occurs during a period when the wave transmitting/receiving circuit system does not need to operate normally. It can be prevented.

In addition, since the transmitter/receiver circuit system is not operated when an abnormality occurs,
Power consumption when an abnormality occurs can be reduced, and the time required to return to a normal state can be shortened.

3 Next, a third embodiment of the ultrasonic detector according to the present invention will be described using FIG. In addition, in the figure, parts with the same numbers as in FIG. 3 perform the same functions. In the third embodiment, an abnormality detection gate circuit 20 is provided in place of the abnormality detection gate circuit 18 of the second embodiment. Also,
A diode D2 and a backup capacitor C2 are connected to the input side of the second constant voltage circuit 3, so that even if the voltage from the external power supply 4 decreases due to, for example, a momentary power outage, the output voltage of the second constant voltage circuit 3 will only gradually decrease. We are trying not to do that.

The abnormality detection gate circuit 20 detects abnormal timings with relatively narrow pulse widths at the rising edge of the transmitting gate pulse C of the transmitting gate circuit 9 and at the rising and falling edges of the receiving gate pulse q of the transfer gate circuit 10. The pulse is output to the AND circuit 19 (FIG. 6, waveform 0). In other words, the abnormal timing pulses at the rising edge of each of the transmitting gate pulse C and the receiving gate pulse Q are used to confirm whether or not the transmitting/receiving circuit system can be operated. The abnormal timing pulse when falling is used to check whether the wave transmitting/receiving circuit system is malfunctioning during the wave transmitting/receiving operation. Even if an abnormal signal occurs outside the output period of each of the abnormal timing pulses, the wave transmitting/receiving circuit system is configured to perform normal operation.

Next, the operation of the third embodiment will be explained using FIG. 6.

An ultrasonic pulse is transmitted during the output period of the transmission gate pulse 1-pulse C, and is reflected by a nearby object, for example, and the detection signal "7" applied to this reflected wave is within the period of the reception gate pulse G7. , the output of storage block 7 goes high.

Now, when an abnormality such as a momentary power outage occurs at time 17 and the output voltage of the second constant voltage circuit 3 gradually decreases and becomes lower than the set voltage of the abnormality detection block 5, an abnormality signal A3 is output from the abnormality detection block 5. be done. If, for example, the abnormal timing pulse 02 among the abnormal timing pulses 01, 02.03 is input to the AND circuit 19 during the input period of the abnormal signal A3, the AND circuit 19 outputs a pulse P1. Then, the wave receiving operation is stopped by this pulse P1. Further, the storage block 7 holds the recorded contents, and the held, for example, high signal from the storage block 7 is output to the output circuit 17 .

Note that when the abnormal timing pulse 01 is input to the AND circuit 19 during the input period of the abnormal signal A3, the transmission and reception of the ultrasonic pulse is stopped, and the recorded contents of the memory block 7 are further held and output. Further, when the abnormal timing pulse 03 is input to the AND circuit 19 during the input period of the abnormal signal A3, the recorded contents of the memory block 7 are held and output.

On the other hand, when neither the abnormal timing pulse Ch 2 nor 02.03 is input to the AND circuit 19 during the input period of the abnormal signal A3, the memory block 7 and the like operate normally even during the abnormal period.

In this manner, in the third embodiment, an abnormality such as a momentary power outage is determined and processed during the period of the abnormal timing pulse having a relatively narrow pulse width, so that the configuration of the control unit 66 can be easily constructed. Further, when a microcomputer is used for the control block 6, the control program can be shortened.

Next, a fourth embodiment of the ultrasonic detector according to the present invention will be described using FIG. 7. In addition, in the figure, the same numbers as those in FIG. 5 are assigned the same functions. The fourth embodiment has abnormality detection gate circuits 21 to 2 instead of the abnormality detection circuits 1 to 20 and the AND circuit 19 of the third embodiment.
3 and AND circuits 24 to 26 are provided, and a control block 27 and a storage block 28 are provided in place of the control block 6 and storage block 7.

That is, the abnormality detection gate circuit 21 outputs a first abnormal timing pulse (waveform q in FIG. 8) having a relatively narrow pulse width to the AND circuit 24 at the rising edge of the transmission gate pulse of the transmission gate circuit 9. It is something. The abnormality detection gate circuit 22 outputs a second abnormal timing pulse (waveform r in FIG. 8) having a relatively narrow pulse width to the AND circuit 25 at the falling edge of the transmission gate pulse. The abnormality detection gate circuit 23 outputs a third abnormal timing pulse (waveform S in FIG. 8) having a relatively narrow pulse width to the AND circuit 26 at the falling edge of the reception gate pulse of the reception gate circuit 10. be.

The AND circuit 24 receives the abnormality signal a from the abnormality detection block 5.
and the first abnormal timing pulse q is output to the control block 27 and the storage block 28 (FIG. 8, waveform t).

AND circuit 25 receives abnormality signal a from abnormality detection block 5.
and the second abnormal timing pulse r is output to the control block 27 and the storage block 28 (waveform U in FIG. 8). The AND circuit 26 outputs the AND of the abnormality signal a from the abnormality detection block 5 and the third abnormal timing pulse S to the control block 27 and the storage block 28 (FIG. 8, waveform V).

When the control block 27 receives the high signal from the AND circuit 24, it controls the transmission gate circuit 9 and the reception gate circuit 10.
When the output of each clock signal to the receiving gate circuit 10 is stopped and a high signal from the AND circuit 25 is input, the output of the clock signal to the receiving gate circuit 10 is stopped. Note that when the control block 27 inputs the high signal from the AND circuit 26, the output of each clock signal to the wave transmitting gate circuit 9 and the wave receiving gate circuit 10 has been completed, so that the wave transmitting and wave receiving operations are performed. I'm trying to continue as is.

Further, when the memory block 28 receives a high signal from the AND circuits 24 to 26, it holds the stored contents and outputs the stored contents.

Next, the operation of the fourth embodiment will be explained using FIG. 8.

When the abnormality detection block 5 outputs a normal signal, the first abnormality timing pulse Q is output from the abnormality detection gate circuit 21 at the time of starting transmission of the ultrasonic pulse D.
At the end of transmission of the ultrasonic pulse D, a second abnormality timing pulse R is output from the abnormality detection gate circuit 22. Furthermore, at the end of the reception gate pulse G, a third abnormality timing pulse S is output from the abnormality detection gate circuit 23.

9 When the ultrasonic pulse D is reflected by, for example, a nearby object and the detected signal F of this reflected wave is within the period of the reception gate pulse G, the output of the memory block 7 becomes high.

After this, for example, the abnormality detection block 5 outputs the abnormality signal A4.
While Q is being output, the first abnormal timing pulse Q
When 1 is output to the AND circuit 24, the AND circuit 24 outputs a detection pulse T1. This detection pulse T1 is input to the control block 27 and the memory block 28, respectively, and the output of the clock signal from the control block 27 to the wave transmitting gate circuit 9 and the wave receiving gate circuit 10 is stopped, and the memory block 28 is inputted to the current It retains the memory contents and outputs the memory contents. That is, both wave transmission and wave reception operations are stopped.

On the other hand, for example, the abnormality signal A5 from the abnormality detection block 5
While the second abnormal timing pulse R is being outputted, the second abnormal timing pulse R
When 1 is output to the AND circuit 25, the AND circuit 25 outputs a detection pulse U1. This detection pulse U1 is input to the control blocks 27 and 0 and the memory block 28, and the output of the clock signal from the control block 27 to the receiving gate circuit 10 is stopped, and the memory block 28 retains the current memory contents. and outputs the stored contents. In other words, only the transfer operation is stopped.

On the other hand, for example, the abnormality signal A6 from the abnormality detection block 5
While the third abnormal timing pulse S
When 1 is output to the AND circuit 26, the AND circuit 26 outputs a detection pulse V1. This detection pulse V1 is input to the control block 27 and the memory block 28, and the clock signal is continued to be output from the control block 27 to the wave transmitter gate circuit 9 and the wave receiver gate circuit 10, and the memory block 28 Holds the current memory content and outputs the memory content. That is, both wave transmission and wave reception operations are continued.

In this way, in the fourth embodiment, since the wave transmission and wave reception operations are changed depending on the timing at which the abnormality detection block 5 outputs the abnormality signal, it is possible to improve responsiveness to abnormalities. In addition, if an abnormality occurs after transmitting an ultrasonic pulse, the receiving operation will not be performed.
After the system returns to normal, it starts transmitting ultrasonic pulses again, so the response time can be shortened.

Next, a fifth embodiment of the ultrasonic detector according to the present invention will be described using FIG. 9. In addition, in the figure, Figure 3 (Figure 2)
Components with the same numbers as those in the embodiment) perform the same functions. In the fifth embodiment, an abnormality detection block 53, a control block 29, and an abnormality detection gate circuit 30 are provided in place of the abnormality detection block 5, control block 6, and abnormality detection gate circuit 18 of the second embodiment. Further, a diode D2a and a backup capacitor C2 are connected to the input side of the second constant voltage circuit 3.

The comparator 54 of the abnormality detection block 53 compares the voltage of the external power supply 4 and the set voltage of the set voltage section 55, and
When the voltage of m4 is higher than the set voltage, a low signal is output as a normal signal, and during a period when the voltage of external power supply 4 is lower than the set voltage, a high signal is output as an abnormal signal. . Also, 1-choki backazo for 2]nden ()
The capacity of C2 is that if the period from the start of sending of sending wave 1-pulse C to the end of receiving gate pulse G is set to, for example, 10 m5, sending wave J5 and receiving wave can operate in the event of an abnormality. The time is set to be 15 m5, for example. In other words, even if an abnormality occurs at the start of the wave transmission operation, the voltage of the second constant voltage circuit 3 is gradually lowered (Fig. 10, waveform Z), so that the wave reception operation of the reflected wave due to the wave transmission is delayed. It is too difficult to ensure that the process is terminated.

The control block 29 outputs an abnormal timing pulse (FIG. 10, waveform W) to the abnormality detection circuit 30, and also outputs a clock signal (FIG. 10, waveform X) delayed from this abnormal timing pulse W by TH2 period. is outputted to the wave transmitter 1 circuit 9 and the wave receiver gate circuit 10. The circuit 30 to the abnormality detection game 1 outputs a delayed timing pulse (waveform y in FIG. 10) of a predetermined width TH1, which is triggered by the abnormal timing pulse W, to the AND circuit 19.

3 Next, the operation of the fifth embodiment will be explained using FIG. 10.

When the abnormality detection block 53 is outputting a normal signal, the abnormality timing pulse W from the control block 29 causes the abnormality detection circuit 1 to 30 to output a delayed timing pulse Y with a pulse width TH1 to the AND circuit 19.

On the other hand, a transmitting gate pulse C and a receiving gate pulse G are outputted by the clock signal X from the two control blocks.

Then, the abnormality signal A output from the abnormality detection block 5
7 is outside the output period of the delayed timing pulse Y1, for example, the output from the abnormality detection block 53 remains low, and the output of one AND circuit remains low. Therefore, the wave transmitting and wave receiving operations are both continued, and the wave transmitting gate pulse C2 and the wave receiving gate pulse G9 are outputted from the wave transmitting gate circuit 9 and the wave receiving circuits 1 to 10, respectively.

On the other hand, the abnormality signal outputted from the abnormality detection block 5
is within the output period of the delayed timing pulse 4, for example, the high signal N is output from the AND circuit 19.
2 is output, and this high signal N2 is input to the control block 29. When the control block 29 receives the high signal N2, it outputs high (abnormal timing pulse W1).

Therefore, the two control blocks are re-triggered, and after the output period of 8 to the abnormal signal has elapsed, it becomes high until the T old period (delayed timing pulse Y2). Further, the control block 29 stops outputting the clock signal X until the TH2 period elapses after the elapse of the output period of the abnormal timing pulse W1. That is, the backup capacitor C2 that was discharged due to the abnormality is charged again, and the second constant voltage circuit 3
The clock signal × is not outputted until a constant voltage is outputted from and the wave transmitting and wave receiving operations become possible.

Furthermore, the storage block 28 retains the current storage contents due to the high signal N2 and outputs the storage contents.

As described above, in the fifth embodiment, the control block 29 is simplified because the timing when an abnormality occurs and the control block 29 determines the abnormality is before the period during which the wave transmitting/receiving circuit system needs to operate normally. can be converted into Also,
When microcomputers are used for two control blocks, the control program can be shortened.

〔Effect of the invention〕

According to the present invention, when an abnormality occurs in the power source for the wave transmitting/receiving circuit system, the operation of the wave transmitting/receiving circuit system is stopped at least during the period during which the abnormality is detected, so that the voltage of the power source decreases due to the abnormality. It is possible to prevent false detections due to malfunctions caused by this, and it is possible to provide a highly reliable ultrasonic detector.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the first embodiment of the ultrasonic detector according to the present invention, FIG. 2 is a timing chart explaining the operation of the first embodiment, and FIG. 3 is a block diagram of the ultrasonic detector according to the present invention. A block diagram of the second embodiment, FIG. 4 is a timing chart for explaining the operation of the second embodiment, and FIG.
A block diagram of the embodiment, FIG. 6 is a timing chart explaining the operation of the third embodiment, FIG. 7 is a block diagram of the fourth embodiment of the ultrasonic detector according to the present invention, and FIG. 8 is a diagram of the fourth embodiment. FIG. 9 is a block diagram of the fifth embodiment of the ultrasonic detector according to the present invention, and FIG. 10 is a timing chart explaining the operation of the fifth embodiment. 1... Power supply block, 2... First constant voltage circuit, 3.
... Second constant voltage circuit, 4... External power supply, 5... Abnormality detection block, 6... Control block, 7... Memory block, 8... Oscillation circuit, 9... Wave transmission gate circuit,
10... Receiving gate circuit, 11.16... AND circuit, 12... Transmitting drive circuit, 13... Transducer/receiver, 1
4... Amplification circuit, 15... Detection circuit, 17... Output circuit, 51... Comparator, 52... Setting voltage section, C
1...Backup capacitor.

Claims (1)

[Claims] 1. In an ultrasonic detector equipped with a wave transmitting/receiving circuit system that detects an object by repeatedly transmitting and receiving ultrasonic pulses, and a control circuit system that controls the operation of the wave transmitting/receiving circuit system, the above-mentioned wave transmitting/receiving circuit system is Ultrasonic waves characterized by comprising: an abnormality detecting means for detecting the occurrence of an abnormality in the power source for the ultrasonic wave; and an operation stopping means for stopping the operation of at least the above-mentioned wave transmitting/receiving circuit system during the period during which the above-mentioned abnormality is detected. Detector.