JPH07320483A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent the mis-read-out, to reduce the power consumption, to operate at a high speed, and to widen the application range by forming a power saving circuit from a pulse generation circuit and an operation circuit including a delay element. CONSTITUTION:A pulse generation circuit 51 generates a delay pulse in which only the fall time of a signal SYN is delayed by a delay element DI. And an operation circuit 52 reverses the signal SYN with an inverter IV2. By this delay pulse and a NAND logic, a power saving signal PS in which only the delay time from the leading edge of an activation level of the signal SYN by the delay element DI is made to be at an activation level is obtained. The period of the activation level of this signal PS is adapted to an operation period of a sense amplifier circuit 3. Thereby, mis-read-out of data is prevented and a high speed operation can be performed. Further, whole power consumption including the sense amplifier is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a low power consumption, synchronous semiconductor memory device for controlling activation of a sense amplifier circuit in synchronization with a synchronization signal.

[0002]

2. Description of the Related Art Synchronous semiconductor memory devices are often composed of a dynamic type circuit inside, and are easy to reduce power consumption and speed, and often have large capacity.

FIG. 5 is a block diagram showing an example of a conventional synchronous general semiconductor memory device.

This semiconductor memory device includes a memory cell array 1 for reading stored data at a designated address, an address selection circuit 2 for designating an address of the memory cell array 1 according to an address signal AD, and a power save signal PSx.
Sense amplifier circuit 3 which is activated in accordance with the above and detects, amplifies and outputs the data read from memory cell array 1, and output data of this sense amplifier circuit 3 is used as power save signal P.
An output latch circuit 4 that latches, holds and outputs according to Sx, and a power save signal PSx according to a synchronization signal SYN.
Is generated and supplied to the sense amplifier circuit 3 and the output latch circuit 4 and a power save circuit 5x.

In such a semiconductor memory device, activation / deactivation of the sense amplifier circuit 3 is controlled by the power save signal PSx, and the sense amplifier circuit 3 is almost 0 m in the inactivated state.
W, several mW of power is consumed per sense amplifier in the activated state. Normally, several to several tens of sense amplifiers are present in the synchronous semiconductor memory device, so that the power consumption of the sense amplifier circuit 3 in the activated state is about several tens of mW, which is the power consumption of the semiconductor memory device. Account for more than 50%.

On the other hand, for example, when the cycle of the synchronizing signal SYN set by the system is 20 ns and the duty ratio of the activation level and the inactivation level is 50%, the activation level time is 10 ns. In recent devices,
The operation time of data detection, amplification, etc. of the sense amplifier necessary for reading is about 5 ns, which is not necessary as much as the pulse width of the synchronization signal SYN. Sync signal SY set by the system
Since N is governed by the operating speed of the low speed ALU or the like existing in the system, it cannot be set in accordance with the operating speed of the semiconductor memory device. AL in the future
Even if the operation speed of U and the like is improved and the synchronization signal can be made faster, the same problem occurs because the operation speed of the synchronous semiconductor memory device is also improved.

Therefore, for example, Japanese Patent Laid-Open No. 57-19538.
As in the invention described in Japanese Patent No. 2 publication, a power save circuit (5
x), there is proposed an example in which a power save signal PSx for shortening a period during which the sense amplifier circuit 3 is activated is generated from a synchronization signal SYN set in the system to reduce power consumption.

FIG. 6 shows a circuit diagram corresponding to the power save circuit according to the invention described in the above publication.

The power save circuit 5x has a synchronization signal S
A delay element D3 for delaying YN for a predetermined time and an inverter IV3 for inverting the level of the output signal of this delay element D3
And the output signal of the inverter IV3 and the synchronization signal SY.
And a 2-input NOR type logic gate G5 which receives N corresponding to each of the first and second input terminals and outputs a power save signal PSx.

Next, the operation of the power save circuit 5x will be described with reference to the timing chart of FIG.

Sync signal SY when the cycle is 20 ns
N is delayed by a delay element D3 for a predetermined time (td, for example, 5 ns) and becomes a delay signal of a node N11. This signal is inverted by an inverter IV3 and becomes a signal of a node N12.
The signal of the node N12 and the synchronizing signal SYN are logically operated by the NOR type logic gate G5 to obtain the power save signal PS.
Output as x.

The semiconductor memory device which controls the sense amplifier circuit 3 by the power save signal PSx has a synchronization signal S
The power save signal PSx rises to a high level in response to the fall of YN, activates the sense amplifier circuit 3, and starts reading. After 5 ns set by the delay element D3, that is, in the case of FIG. 7, 50% of the time of 10 ns which is the low level time of the synchronizing signal SYN, the power save signal becomes low level and the sense amplifier circuit 3 is turned off. Activate.

On the other hand, when the sense amplifier circuit 3 is controlled only by the synchronizing signal SYN instead of the signal generated by the power save circuit 5x, data reading is performed from the falling point of the synchronizing signal SYN in FIG. , Sync signal SY
The sense amplifier circuit 3 is activated during the time when the N level is low. Therefore, by controlling the sense amplifier circuit 3 with the power save signal PSx generated by the power save circuit 5x, the time in the activated state can be reduced by 50%, which occupies 50% or more of the semiconductor memory device. Since the current consumption when the sense amplifier circuit 3 is active can be reduced by 50%, the power consumption of the entire semiconductor memory device can be reduced by 25% or more.

In this example, the activation level of the synchronizing signal SYN is set to the low level and the activation level of the power save signal PSx is set to the high level, but the activation levels of these signals include those including the sense amplifier circuit 3. It is set arbitrarily according to the conditions of the peripheral circuit.

In the example of FIG. 7 (first example), the synchronization signal SY
Although the duty ratio of N is 50%, this duty ratio can be set arbitrarily. In FIG. 8, the duty ratio 1
Delay element D3 with 5% (cycle 20 ns, high level 3 ns)
7 shows a timing chart of an example (second example) when the delay time due to is 4 ns.

In this example, the power save signal PSy is generated 1 ns after the leading edge of the synchronization signal SYN at the low level (activation level), and the activation level period is equal to the high level period of the synchronization signal SYNa. It will be 3 ns. Therefore, assuming that the operation time of the sense amplifier circuit 3 is 5 ns, the pulse width of the power save signal PSy becomes insufficient, and the read data does not reach a level sufficient to discriminate between "1" and "0". There is a risk of sticking out. Even if the pulse width is increased to 5 ns by some means, it takes 6 ns from the leading edge of the activation level of the synchronization signal SYN to the end of data reading, which makes high-speed reading difficult.

[0017]

In the conventional semiconductor memory device described above, in the first example of the synchronizing signal SYN having a period of 20 ns and a duty ratio of about 50%, the delay time Td by the delay element D3 in the power save circuit 5x is increased. A power save signal PSx having a pulse width (activation level) of a minute portion is used to control activation of the sense amplifier circuit 3 which requires power consumption of 50% or more of the entire power consumption at the time of activation. However, in the second example using the synchronization signal SYN whose high level time is shorter (for example, 3 ns) than the delay time (for example, 4 ns) of the delay element D3,
Since the pulse width (activation level) of the power save signal PSy is equal to the high level time of the synchronizing signal SYN, the operation time of the sense amplifier circuit 3 is insufficient and read data "1" or "0" is discriminated. However, even if the pulse width of the power save signal PSy is widened by a certain amount by any means, the activation level (low level) of the synchronization signal SYN is not increased. There is a problem in that it takes time from the leading edge to the end of data reading, and high-speed reading is difficult. Therefore, the duty ratio and pulse width of the synchronization signal are restricted and the applicable range is limited.

An object of the present invention is to obtain a power save signal having a predetermined pulse width under any condition of the synchronizing signal, without risk of erroneous reading, and to reduce power consumption and high speed operation. It is an object of the present invention to provide a semiconductor memory device whose application range can be expanded.

[0019]

In a semiconductor memory device of the present invention, a memory cell array for reading stored data at a specified address and a memory cell array activated in response to an activation level of a power save signal are read from the memory cell array. It has a sense amplifier circuit that detects data, amplifies and outputs the data, and a power save circuit that generates the power save signal that becomes an activation level for a predetermined time from the leading edge of the synchronization signal. The power save circuit includes a pulse generation circuit that generates a delayed pulse in which only the leading edge of the synchronization signal is delayed for a predetermined time, and the delay pulse and the synchronization signal from the leading edge of the synchronization signal to the delay pulse A pulse generator circuit having an arithmetic circuit for generating a power save signal which becomes a time activation level corresponding to the delay time of the leading edge, and a leading edge of the synchronizing signal as a changing point from a high level to a low level. A first inverter that inverts the level of the synchronization signal, a two-input NAND type first logic gate that receives an output signal of the inverter at a first input terminal, an output signal of the first logic gate, and A two-input NAND type second logic gate that receives the synchronization signal corresponding to each of the first and second input terminals and an output signal of the second logic gate are delayed by a predetermined time and then output. A delay circuit for supplying a delay pulse to the second input terminal of the first logic gate to output a delay pulse from the output terminal of the first logic gate; and an arithmetic circuit for inverting the level of the synchronization signal. And an output signal of the second inverter and the delay pulse corresponding to each of the first and second input terminals, and outputs a power save signal whose activation level is low.
It is configured as a circuit including an input NAND type third logic gate.

Further, the leading edge of the synchronizing signal is set as a transition point from a low level to a high level, the pulse generating circuit receives an inverter for inverting the level of the synchronizing signal, and an output signal of the inverter at a first input terminal. A two-input NAND type first logic gate, a delay element for delaying an output signal of the first logic gate for a predetermined time, and an output signal of the delay element and the synchronization signal at first and second input terminals. A two-input NAND type second logic gate which outputs a reception delay pulse corresponding to each and supplies it to the second input end of the first logic gate, and the arithmetic circuit is the synchronization signal. And a delayed pulse corresponding to each of the first and second input terminals, and outputs a power save signal whose activation level is a high level, and is configured as a circuit including a third logic gate of a 2-input NAND type. It is.

[0021]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

This embodiment differs from the conventional semiconductor memory device shown in FIGS. 5 and 6 in that the power save circuit 5 is used.
Is a first inverter IV1 that inverts the level of the synchronization signal SYN whose leading edge is a transition point from a high level (inactivation level) to a low level (activation level), and an output signal of this inverter IV1 is 2-input NAN received at the input end
D-type first logic gate G1, this first logic gate G
A two-input NAND type second logic gate G2 which receives the output signal of 1 and the synchronization signal SYN corresponding to the first and second input terminals, respectively, and the output signal of the second logic gate G2 for a predetermined time. The first logic gate G including the delay element D1 which is delayed and supplied to the second input terminal of the logic gate G1
A pulse generation circuit 51 for generating a delayed pulse in which only the leading edge of the synchronization signal SYN is delayed by a predetermined time from the output terminal of 1.
A second inverter IV that inverts the level of the synchronization signal SYN
2 and the output signal of the second inverter IV2 and the delay pulse corresponding to the first and second input terminals, respectively, and outputs the power save signal PS whose activation level is low level from the output terminal. An arithmetic circuit 52 including a two-input NAND type third logic gate G3 is provided, and a circuit for generating a power save signal PS which becomes an activation level for a predetermined time from the leading edge of the synchronizing signal SYN is provided.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. FIG. 2 is an example when a synchronization signal SYN having a cycle of 20 ns and a duty ratio of 15% (high level) is used.

First, when the synchronization signal SYN is at a high level (inactivation level) and a sufficient time has elapsed (state of T1),
The node N1 goes low due to the inverter IV1, and therefore the node N4 goes high regardless of the level of the node N3. At this time, the node N2 is at a low level because both the synchronizing signal SYN, which is the input of the logic gate G2, and the node N4 are at a high level, and the node N3 has a sufficient time and the level of the node N2 is transmitted through the delay element D1. Because it is a low level.

Next, when the synchronization signal SYN changes to the low level (activation level) (state of T2), the node N1 is at the high level 1 by the inverter IV1 and the node N2 has the synchronization signal SYN at the low level. High level regardless of level. Due to the delay element D1, the node N3 does not transmit a signal change and remains at the low level, and therefore the node N4 remains at the high level.

Next, when the level of the node N2 is transmitted to the node N3 5 seconds after the delay time td set by the delay element D1 (state of T3), the node N3 becomes high level and the node N1 is also high level. Therefore, the node N4 becomes low level. Further, at this time, the level of the node N2 does not change and remains at the high level even when the node N4 changes from the high level to the low level because the synchronization signal SYN remains at the low level. Next, when the synchronization signal SYN changes to high level (state of T4), the node N1 becomes low level, so that the node N4 is high level regardless of the level of the node N3, and the node N2 has both the synchronization signal SYN and the node N4. It becomes a high level and therefore a low level. Further, even when the level of the node N2 is transmitted to the node N3 by the delay element D1, the node N3 does not change to the low level, so that the node N4
Remains high. That is, this is the same state as T1 described above.

As described above, the node N4 which is the output of the pulse generation circuit 51 responds to the synchronizing signal SYN having a cycle of 20 ns and a duty ratio of 15% at the falling edge of the synchronizing signal SYN (the leading edge of the activation level). ) Only delay element D1
Generates a delayed pulse delayed by.

Then, in the arithmetic circuit 52, the synchronization signal SYN
Is converted into a signal of the node N5 which is inverted by the inverter IV2, and a NAND logic of this and the delay pulse of the output of the pulse generation circuit 51 is taken, so that the delay element D1 is provided from the leading edge of the activation level of the synchronization signal SYN. Delay time td
A power save signal PS having an activation level (low level) corresponding to (5 ns) is obtained. That is, the power save signal PS has an activation level immediately regardless of the duty ratio of the synchronization signal SYN and without a time difference with respect to the leading edge of the activation level of the synchronization signal SYN, and the delay time by the delay element D1. The waveform is such that the activation level is held only for the time determined by td.

Therefore, the period of the activation level of the power save signal PS can be adapted to the operation time of the sense amplifier circuit 3, so that the erroneous reading of data can be prevented, and the synchronization signal SYN and power save can be prevented. Signal PS
Since the leading edges of the activation levels of the power saving signal PS coincide with each other, high-speed operation is possible, and the period of the activation level of the power save signal PS can be made shorter than the period of the activation level of the synchronization signal SYN ( In this embodiment, 5 for 17 ns
ns, that is, about 70% reduction), the power consumption by the sense amplifier circuit 3 is reduced accordingly, and the overall power consumption can be reduced (in this embodiment, exceeds 35%).
Moreover, since the activation level time and duty ratio of the power save signal PS can be determined independently of the duty of the synchronization signal SYN, the applicable range can be expanded.

FIG. 3 is a circuit diagram of a power save circuit showing a second embodiment of the present invention, and FIG. 4 is a timing chart of signals at respective parts for explaining the operation thereof.

In the power save circuit 5a of this embodiment, the leading edge of the synchronizing signal SYN is used as a transition point from a low level to a high level, and the pulse generating circuit 51a uses an inverter IV1 for inverting the level of the synchronizing signal SYN and this inverter. IV1
2 input NAND type first logic gate G1 which receives the output signal of the first logic gate G1 and a delay element D2 which delays the output signal of the first logic gate G1 by a predetermined time (td).
And a 2-input NAND type which outputs the output signal of the delay element D2 and the synchronization signal SYN corresponding to the first and second input terminals, respectively, and outputs a delay pulse to the second input terminal of the logic gate G1. And a second logic gate G2 of the operation circuit 52a, and the operation circuit 52a receives the synchronization signal SYN and the delay pulse corresponding to the first and second input terminals, respectively, and a power save signal whose activation level is a high level. PS
a two-input NAND type third logic gate G3 for outputting a
And a synchronization signal S whose high level is an activation level.
With respect to the leading edge of YN, the activation level becomes a high level without any time difference, and the time of the activation level generates the power save signal PSa determined by the delay time td by the delay element D2.

Next, the operation of this embodiment will be described with reference to the timing chart of FIG. FIG. 4 is an example when the synchronization signal SYN having a cycle of 20 ns and a duty ratio of 85% (high level) is used.

First, when sufficient time has passed while the synchronization signal SYN is at the low level (state of T11), the node N6 is at the high level by the inverter IV1 and the node N9 is at the synchronization signal S.
Since YN is at low level, it is at high level regardless of the level of node N8, and node N7 is at low level because both nodes N6 and N9, which are inputs to the logic gate G1, are at high level. It is at a low level because the level of the node N7 is transmitted through the element D2.

Next, when the synchronizing signal SYN changes to the high level (state of T12), the node N6 becomes the low level by the inverter IV1, and therefore the node N7 becomes the high level regardless of the level of the node N9. Since the signal is not transmitted to the node N8 because of the delay element D2, the node N8 remains at the high level.

Next, when the level of the node N7 is transmitted to the node N8 5ns after the delay time td set by the delay element D2 (state of T13), the node N8 becomes high level and the synchronization signal SYN is also at high level. Therefore, the node N9 becomes low level. At this time, the level of the node N7 does not change and remains at the high level even when the node N9 changes from the high level to the low level because the node N6 remains at the low level.

Next, when the synchronizing signal SYN changes to the low level (state of T14), the node N6 is at the high level by the inverter IV1, the node N9 is at the high level 1 regardless of the level of the node N8, and the node N7 is at the node N6. And the node N9 both become high level, and thus become low level. Also, when the level of the node N7 is transmitted to the node N8 by the delay element D2, the node N8 does not change to the low level and the node N9 remains at the high level. That is, the above-mentioned T1
It is the same state as 1.

As described above, the pulse generation circuit 51 responds to the synchronization signal SYN having a cycle of 20 ns and a duty ratio of 85%.
The output node N9 of "a" generates a pulse in which the delay element D2 delays and inverts only the rising edge of the signal with respect to the synchronizing signal SYN. Then, the arithmetic circuit 52a obtains the synchronization signal SYN by taking the AND logic of the synchronization signal SYN and the delay pulse of the output of the pulse generation circuit 51.
From the leading edge of the activation level of the power saving signal PSa, the power save signal PSa which becomes the activation level (high level) for the delay time td (5 ns) by the delay element D2 is obtained.

Also in this embodiment, the same effect as that of the first embodiment can be obtained.

In the above-described embodiment, the present invention can be applied even when the activation levels of the synchronization signal and the power save signal are different, and in this case as well, although the configuration is slightly different (for example, addition of an inverter). The basic circuit configuration is the same, and there may be modifications of the above-described embodiments (for example, replacement of logic gates with NOR type).

[0041]

As described above, according to the present invention, the power save circuit is composed of a pulse generating circuit for generating a delayed pulse in which only the leading edge of the synchronizing signal is delayed for a predetermined time, and the delay pulse and the synchronizing signal. By providing a circuit including an arithmetic circuit that generates a power save signal that becomes a time activation level corresponding to the delay time of the leading edge of this delay pulse from the leading edge of the synchronization signal, the activation level of this power save signal can be changed. Since the period can be adapted to the operation time of the sense amplifier circuit, erroneous reading of data can be prevented, and high-speed operation is possible because the leading edges of the activation levels of the sync signal and power save signal match. Therefore, the period of the activation level of the power save signal PS can be made shorter than the period of the activation level of the synchronization signal. Power consumption is reduced, the overall power consumption can be reduced, and the activation level time and duty ratio of the power save signal can be set regardless of the duty ratio of the synchronization signal, so the applicable range is expanded. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 5 is a block diagram showing an example of a conventional semiconductor memory device.

6 is a circuit diagram showing a specific example of a power save circuit of the semiconductor memory device shown in FIG.

7 is a timing chart of a first example of signals of respective parts for explaining the operation of the semiconductor memory device including the power save circuit shown in FIG.

8 is a timing chart of a second example of signals of respective parts for explaining the operation of the semiconductor memory device including the power save circuit shown in FIG.

[Explanation of symbols]

 1 memory cell array 2 address selection circuit 3 sense amplifier circuit 4 output latch circuit 5, 5a, 5x power save circuit 51, 51a pulse generation circuit 52, 52a arithmetic circuit D1 to D3 delay element G1 to G5 logic gate IV1 to IV3 inverter

Claims (4)

[Claims] 1. A memory cell array for reading stored data at a specified address, and a sense amplifier circuit which activates in response to an activation level of a power save signal to detect, amplify, and output data read from the memory cell array. And a power save circuit for generating the power save signal which becomes an activation level for a predetermined time from the leading edge of the synchronization signal. 2. A power save circuit comprising: a pulse generating circuit for generating a delay pulse in which only a leading edge of a synchronizing signal is delayed for a predetermined time; the delay pulse and the synchronizing signal; and a leading edge of the synchronizing signal. 2. The semiconductor memory device according to claim 1, further comprising an arithmetic circuit that generates a power save signal that becomes a time activation level corresponding to the delay time of the leading edge of the delay pulse. 3. A first inverter for inverting the level of the synchronizing signal in a pulse generating circuit, wherein a leading edge of the synchronizing signal is set as a transition point from a high level to a low level, and an output signal of the inverter is a first input. The first of the two-input NAND type received at the end
, A second input NAND type second logic gate for receiving the output signal of the first logic gate and the synchronizing signal corresponding to the first and second input terminals, respectively, and the second logic A delay element for delaying the output signal of the gate for a predetermined time and supplying the delayed signal to the second input terminal of the first logic gate to output a delay pulse from the output terminal of the first logic gate; A circuit receives a second inverter that inverts the level of the synchronization signal, an output signal of the second inverter, and the delay pulse corresponding to each of the first and second input terminals, and a low level is an activation level. 3. The semiconductor memory device according to claim 2, which is a circuit including a two-input NAND type third logic gate which outputs the power save signal. 4. A pulse generation circuit, wherein an inverter for inverting the level of the synchronizing signal is used as a transition point from a low level to a high level for the leading edge of the synchronizing signal, and an output signal of the inverter is received at a first input end. A two-input NAND type first logic gate, a delay element for delaying an output signal of the first logic gate for a predetermined time, and an output signal of the delay element and the synchronization signal at first and second input terminals. A two-input NAND type second logic gate which outputs a reception delay pulse corresponding to each and supplies it to the second input end of the first logic gate, and the arithmetic circuit is the synchronization signal. And a delayed pulse corresponding to each of the first and second input terminals to output a power save signal whose activation level is a high level, and a circuit including a third logic gate of a 2-input NAND type. The semiconductor memory device described.