JPH1140763A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the increase rate of the surface area on a film formed on a wafer. SOLUTION: The method is to grow hemispherical or mushroom-like fine crystal grains on the surface of a silicon film by an annealing processing. When the fine crystal grains are formed to desired sizes, gas for inhibiting the surface migration of silicon atoms is added and grain growth is simultaneously stopped. Thus, the size and the form of a fine crystal nucleus on the surface of the silicon film can be controlled and the grains of forms optimum for the device are obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a silicon film having an uneven surface.

[0002]

2. Description of the Related Art Recently, dynamic RAM (hereinafter referred to as DR)
Semiconductor devices such as semiconductor memories such as AM) require a higher degree of integration, and in order to meet this demand, the area required for each memory cell is extremely reduced. For example, 1MDRAM or 4MDRAM
Adopts a design rule such that the minimum design width is 0.8 microns, while a 16MDRAM adopts a design rule such that the minimum design width is 0.6 microns or less. As described above, when the area of the memory cell is reduced, the amount of electric charge stored in the memory cell is also reduced, and it is difficult to secure the amount of electric charge required for the memory cell with high integration.

On the other hand, in order to secure a required amount of charge for a memory cell, a memory cell having a trench type or a stacked type capacitor has been proposed and put into practical use.

[0004] Among them, the structure of a memory cell having a stacked capacitor has advantages in that it has higher soft error resistance and does not damage a silicon substrate, as compared with a structure having a trench capacitor. Therefore, it is expected as a memory cell structure in the next generation. Further, it has been studied to increase the α-ray resistance in the trench by forming the trench capacitor into a stacked trench structure. Therefore, the stacked memory cell is promising as a next-generation technology.

Here, HSG (hemi-sph) is used as a multilayer capacitor applicable to a DRAM of 64 M or more.
A technique using an electronic-grain technique, that is, a technique using a hemispherical particle technique has been proposed (Japanese Unexamined Patent Publication No. 03-2).
72165). The HSG technique is intended to substantially increase the surface area of the storage electrode by forming a large number of hemispherical particles or mushroom-shaped particles on the surface of the storage electrode of the capacitor, thereby realizing a large capacitance. is there.

A method for forming a storage electrode having the above-mentioned hemispherical grains is disclosed in Japanese Patent Application Laid-Open No. 03-272165. In this method, hemispherical grains are formed at a temperature at which the crystallinity of the silicon film transitions from amorphous to polysilicon in LPCVD silicon film growth. By applying this film to the lower electrode of the multilayer capacitor, the surface area of the electrode is greatly increased, and the amount of accumulated charge is increased. JP-A-03-26
In Japanese Patent No. 3370, although the state of surface irregularities is unknown,
It is disclosed that in PCVD silicon film growth, the electrode surface area increases at a temperature at which the crystallinity of the silicon film transitions from amorphous to polysilicon.

[0007] Then, a paper Device published by Watanabe et al.
e application and structure
re observation for hemi-s
chemical grained Si ”Jour
nal of Applied Physics, Vo
l. 71, No. 7, pp 3538-3543 (199
From 2), the growth mechanism of the hemispherical or mushroom-shaped grains was clarified. Specifically, the grains forming the surface irregularities are not formed in the process of growing the silicon film by the CVD method.
It is formed during annealing immediately after the growth of the silicon film.

[0008] More specifically, "Amorphous silicon is deposited during growth by the CVD method, and microcrystalline nuclei are thermally formed on the surface of the amorphous silicon film during an annealing process after the deposition. Silicon atoms migrating on the surface of the amorphous silicon are captured by the microcrystal nuclei, and the microcrystal nuclei grow large, forming hemispherical or mushroom-like grains. "

According to the above-mentioned paper, since a thin oxide film is formed on the surface of the amorphous silicon by exposing the silicon film to the atmosphere after the deposition of the amorphous silicon, the surface migration of silicon atoms is suppressed, and It is described that a grain or mushroom-like grain cannot be formed.

In recent years, a technique for forming the surface unevenness has been further improved, and a technique for suppressing even the density and size of grains has been reported (Japanese Patent Application No. 7-07276). In the specification of Japanese Patent Application No. 7-072276,
Irradiate a gas such as silane to supply silicon atoms to be nuclei to the surface of the amorphous silicon film without a natural oxide film previously processed into an electrode shape, with the nuclei formed after this irradiation as the center, By collecting silicon atoms in each peripheral portion, large irregularities, that is, hemispherical or mushroom-like particles are formed on the surface.

In this method, the grain density is basically controlled by the silane gas irradiation time, and the grain size is controlled by the annealing time. Further, as a method for controlling the grain density, it is described that the substrate is exposed to an oxidizing gas during annealing after the silane gas has been flown. At this time, the oxidizing gas is added at 0.01 torr.
This is done with a moderate pressure. The addition of oxygen at this pressure suppresses the formation of nuclei on the surface of the amorphous silicon film.

However, since the migration of silicon atoms is not completely suppressed, the grain growth is continued. The grain size is basically controlled by the annealing time.

Here, the above-mentioned multilayer capacitor having the electrode surface having irregularities is manufactured as follows. First, an interlayer insulating film is provided on a substrate including a semiconductor element such as a MOSFET. Next, a contact hole is formed in the interlayer insulating film. Next, a silicon film to be finally electrically connected to the semiconductor element is deposited through the contact hole. This silicon film is patterned to form a lower electrode. The formation of the irregularities on the electrodes is performed by using the above-described technique or the like. After the formation of the irregularities, a multilayer capacitor is obtained by sequentially laminating the capacitance insulating film and the upper electrode.

As described above, a method of controlling the size of the hemispherical or mushroom-like grains constituting the irregularities by controlling the annealing time has been proposed. But,
If the annealing time changes for each wafer, the size of the grains will vary from wafer to wafer.
As a result, there arises a problem that the amount of charge stored in the capacitor changes and device characteristics also vary.

[0015]

For this reason, as described above, the annealing time is controlled as accurately as possible for the purpose of making the grain size uniform.

However, according to experiments performed by the present inventor, it has been found that it is difficult to manufacture a large amount of DRAMs by controlling the size and shape of Glen that gives optimum characteristics to a device only by annealing time. . The reason will be described below.

For example, in the case of producing a large amount of hemispherical or mushroom-like grains in a single-wafer apparatus, the grains must be grown in a relatively short time. If you want to finish grain growth in a short time,
A temperature of 550 ° C. or more is appropriate, and annealing is also performed at such a temperature. In the case of the single-wafer method, removal of the wafer after annealing is performed after the wafer temperature has dropped to some extent. The manner in which the wafer temperature decreases is affected by differences in the film formed on the wafer and the device structure.

Actually, in the portion of page 12 [0057] of the specification of Japanese Patent Application No. 7-072276, "Since the influence of the heat capacity of the silicon substrate and the heater is large, the wafer is so small that the influence of the annealing after irradiation with disilane gas is eliminated. Cannot be quenched. " Thus, it is difficult to strictly control the annealing time.

Even when HSGs are formed by a batch type apparatus, it is difficult to strictly control the annealing time. In a batch system, the annealing time may be relatively long because a large amount of wafers are loaded. Therefore, the difference in the temperature lowering speed due to the difference in the type of the wafer and the film quality does not significantly affect the device characteristics.

However, the following problem occurs. For example, in a growth method using a batch type CVD system having a load lock, an annealing time for grain growth is cooled by removing a wafer from a heated furnace body.

In a general LPCVD apparatus, wafers are arranged in a row on a boat and processed in a furnace.
When the wafer is taken out for cooling after the processing is over, the wafer that has been in the back side of the furnace body stays in the heated zone for a long time, and the wafer existing near the outlet of the furnace body is The time to stay in the zone being heated is very short.

In the load-lock type, since there is little oxygen and the like in the furnace, the grains grow even when the wafer is taken out, and there is a problem that the grain size changes due to a difference in the heat history at the time of taking out the wafer.

An object of the present invention is to provide a method of manufacturing a semiconductor device in which a lower electrode of a multilayer capacitor can be formed with good reproducibility, and as a result, a multilayer capacitor having desired characteristics can be formed.

[0024]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device in which fine crystal grains on an amorphous silicon surface are grown by annealing. The grain growth is stopped by adding a gas that inhibits the surface migration of silicon atoms when the microcrystal grains reach a desired size.

Further, a gas containing oxygen atoms is added as the gas that inhibits the migration.

The addition of the gas is carried out under the same conditions as the annealing temperature for growing the fine crystal grains.

The annealing for growing the fine crystal grains is performed in a vacuum or in an inert gas or nitrogen atmosphere.

The pressure at which the gas is added is 1 × 10 ^−2.
The pressure is set higher than Torr.

Further, the shape of the formed fine crystal grains is as follows:
Hemisphere or mushroom-like.

Further, by controlling the shape of the hemispherical or mushroom-like gray, the concentration of impurities diffusing into the grains is controlled.

[0031]

According to the present invention, the grain growth is instantaneously stopped by adding a gas that inhibits the surface migration of silicon atoms when the microcrystal grains reach a desired size.

In this treatment, it was effective to add a gas containing an oxygen atom as a gas that inhibits migration.

When the addition of the gas for suppressing the migration was the same as the annealing temperature for growing the fine crystal grains, the temperature control was very easy and the mass productivity was excellent.

This is performed before addition of a gas for inhibiting migration. It has been found that annealing for growing fine crystal grains is preferably performed in a vacuum or in an inert gas or nitrogen atmosphere.

It has been found that it is desirable that the pressure of the gas for inhibiting migration be higher than 1 × 10 ⁻² Torr.

It has also been clarified that by controlling the grain shape by the above-described method, it is possible to control the impurity concentration in the grain to be optimum for the device characteristics.

[0037]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a configuration diagram showing a semiconductor device for implementing a method of manufacturing a semiconductor device according to Embodiment 1 of the present invention. In FIG. 1, Embodiment 1 of the present invention
The semiconductor manufacturing apparatus according to the first embodiment processes the sample chamber 11 into which a wafer (not shown) is loaded and the wafer, and processes the HSG-
A reaction chamber 12 for forming a Si film is provided, and a wafer transfer chamber 13 held in a vacuum is provided between the sample chamber 11 and the reaction chamber 12. Here, the wafer is placed in the sample chamber 11.
It is assumed that the wafer has amorphous silicon formed before being carried into the wafer, and the surface of the wafer is formed by the amorphous silicon. Reference numeral 14 denotes a door for opening and closing the sample chamber 11.

More specifically, the wafer carried into the sample chamber 11 includes a semiconductor substrate on which semiconductor elements such as MOSFETs are formed, an interlayer insulating film formed on the semiconductor substrate and having a control hole, and And amorphous silicon to be finally electrically connected to the semiconductor element via the contact hole, and the amorphous silicon is patterned. As a result, the amorphous silicon is exposed on the upper surface and the side surfaces, and the upper surface and the side surfaces of the amorphous silicon and the upper surface of the interlayer insulating film form the wafer surface. The semiconductor substrate and the amorphous silicon that have undergone the above-described processing are collectively referred to herein as a wafer. Also,
Hereinafter, the grains on the surface of the silicon film having a hemispherical or mushroom shape are referred to as HSGs.

In FIG. 1, a wafer is loaded by a carriage through a door 14 attached to the sample chamber 11 into the sample chamber 11 maintained at a degree of moisture of less than about 1 × 10 ⁻⁶ Torr by a vacuum pump. The native oxide film on the surface of the wafer guided into the sample chamber 11 is
It has been removed in advance by treatment with an aqueous HF solution.

In the illustrated semiconductor manufacturing apparatus, a wafer is guided to a wafer transfer chamber 13 connected to a sample chamber 11 via a gate valve (not shown). The wafer transfer chamber 13 has a transfer robot (not shown) therein.
have. The wafer is sent from the wafer transfer chamber 13 to the reaction chamber 12 by the transfer robot installed in the wafer transfer chamber 13.

The reaction chamber 12 includes a chamber portion formed of quartz, SiC, or the like, and a bellows portion provided at a lower portion of the chamber portion for isolating from the atmosphere. The isolating bellows unit can move the wafer from which gaseous impurities have been removed in a predetermined direction, for example, in the front and back directions in the figure. FIG. 2 shows a specific device structure.

As shown in FIG. 2, a heater 207 formed by a coil is provided outside the reaction chamber 201 (corresponding to the reaction chamber 12 in FIG. 1). It is evacuated by a vacuum pump and an auxiliary vacuum pump. Further, in the reaction chamber 201, a wafer installation boat 205 capable of accommodating a plurality of wafers is provided on the installation table 2.
04 and silane (Si
An introduction pipe for introducing a silicon-containing gas such as H ₄ ) and an inert gas such as N ₂ is connected. In this case, the installation table 204 and the wafer installation boat 205 are
The bellows 202 is fixed to the isolation bellows 202 in the inside of the reaction chamber 201 and can be moved in the front and back directions in the drawing according to the expansion and contraction of the isolation bellows 202. 21 is a vacuum pump, 22 is a wafer transfer robot, 26 is a dry pump, and 206 is a dummy wafer.

Before the wafer is transferred to the reaction chamber 201, a silane gas is introduced into the reaction chamber 201 as a silicon-containing gas. At this time, the reaction chamber 201 is 1 × 1
The degree of vacuum is maintained at about 0 ^-8 Torr, and the temperature is maintained at a temperature equal to or higher than the decomposition temperature of the silicon-containing gas, for example, 560 ° C. However, the introduction of the silicon-containing gas may be performed at a temperature at which the HSG is formed.

In this atmosphere, the wafer is heated from the wafer transfer chamber 13 into the reaction chamber 12 so that the wafer is heated.
Irradiate the wafer at a flow rate of cm. The silane gas decomposes on the amorphous silicon surface of the wafer to form crystal nuclei. After the introduction of the silane gas, HSG was formed on the upper surface and side surfaces of the amorphous silicon by annealing in the vacuum for 10 minutes while maintaining the vacuum.

Specifically, from the carrier cassette 23 shown in FIG. 2, 50 wafers are transferred from the upper side (gas inlet side) of the wafer setting boat 205 to the lower side (mounting table side).
The HSGs were grown in all the slots up to. As a result, although HSGs were formed on all the wafers from the top to the bottom of the boat 205, it became clear that the shape and size of the HSGs differed depending on the location of the boat 205. It was found that the size of the grains on the upper side of the boat 205 was larger than that on the lower side, the shape of the grains was close to a sphere, and the contact area with the lower electrode was smaller.

Specifically, the grain diameter on the TOP side is 80
In contrast to about 0 °, the lower grain diameter is 70 mm.
It was about 0 °. However, no significant difference was found in the HSG density itself.

In order to investigate the cause, the boat descending speed after the completion of annealing in the HSG forming process was changed. When comparing the case where the lowering speed of the boat 205 is set to 10 mm / min and the case where the lowering speed is set to 400 mm / min, the difference between the boat positions of the grain size is larger when the lowering speed is slower. Was. When it was lowered at 10 mm / min, the HSGs of the wafers on the upper side of the boat grew greatly, and most of the wafers had a shape in which the grains were connected. On the other hand, in the case of lowering at 400 mm / min, most of the HSG grains on the wafer grown on the upper side of the boat are larger than those on the wafer grown on the lower side of the boat, but most of the HSGs on the wafer are grown on the lower side of the boat. HSG grains were not connected.

From these results, it is considered that in the apparatus having the load lock type, the growth of HSG continues even while the boat is descending because the oxygen concentration and the water partial pressure in the apparatus are low. It is considered that the reason why the grains on the upper side of the boat are larger is that the upper wafers pass through the zone heated by the heater over a longer time.

In order to solve this problem and form a uniform HSG irrespective of the position of the boat, the HSG is completely stopped when the growth of the HSG becomes appropriate, and this effect is continued even when the boat descends. It is thought that this will be possible.

Therefore, when the annealing process in the HSG forming process is completed, an attempt was made to irradiate the wafer surface with oxygen gas to oxidize the surface and suppress the surface migration of silicon atoms.

Specifically, silane irradiation and annealing were performed at 560 ° C., and thereafter, oxygen gas was irradiated, and the boat 205 was lowered at a boat lowering speed of 10 mm / min. At this time, the oxygen irradiation pressure was set to 0.005 torr and 0.
Irradiation was performed under three pressures of 01 Torr and 0.1 Torr for 2 minutes and 5 minutes, respectively, for comparison.

As a result, in the case of 0.005 torr, the influence of the position dependence of the boat on the grain size was smaller than in the case where oxygen irradiation was not performed, but the degree of growth of the grain was larger on the upper side of the boat (grain diameter 850 °). Was stronger than the lower part of the boat (grain diameter 750 °). Also, the difference in grain size was smaller when irradiation was performed for 5 minutes than when irradiation was performed for 2 minutes.

On the other hand, even when oxygen was irradiated at 0.01 torr for 2 minutes, a slight difference in grain diameter was observed between the upper and lower sides of the boat. On the other hand, when the boat was lowered after oxygen irradiation for 5 minutes, the grain diameter was 700 ° regardless of the location of the boat 205. Further, the shape of the grains does not depend on the location of the boat 205. 0.1
When oxygen irradiation was performed at torr, a uniform HSG was obtained irrespective of the irradiation time and independent of the boat position. The shape of the grains was almost the same as that obtained by irradiating oxygen at 0.01 torr for 5 minutes.

From the above, it has been found that by irradiating oxygen under appropriate conditions, the grain growth can be suppressed, and the influence of the descent of the boat can be completely suppressed.

(Embodiment 2) In Embodiment 2 of the present invention,
Non-load lock type vertical LPCVD shown in Fig. 3
Using an apparatus, the formation of HSG using the method described in JP-A-03-272165 was studied.

In this process, hemispherical grains are formed at a temperature at which the crystallinity of the silicon film changes from amorphous to polysilicon in LPCVD silicon film growth. By applying this film to the lower electrode of the multilayer capacitor, the surface area of the electrode is significantly increased, and the amount of accumulated charges is increased.

Using the apparatus shown in FIG. 3, the temperature at which HSG was grown was measured using an internal thermocouple and found to be 590 ° C.
On the other hand, the temperature of the external thermocouple was 550 ° C. At this temperature, a silane gas is flowed at 500 sccm at a pressure of 1 Torr, and a silicon film of 1000 ° is deposited on the polycrystalline silicon film doped with phosphorus.
Annealing was performed for 2, 14, 16, 18, 20, and 30 minutes.

Thereafter, a capacitor insulating film was formed by a thermal nitridation process + CVD nitride film growth + nitride film oxidation, and a polysilicon electrode as an upper electrode was deposited. The diffusion of the impurities into the HSG was performed by a method of thermally diffusing the phosphorus-added polysilicon below the HSG into the HSG during the heat treatment at the time of forming the capacitance film.

As a result of observing the wafer after HSG growth, it was found that HSG was formed on the wafer surface regardless of the annealing time. However, it has been found that the shape of the HSG changes depending on the annealing time, which also affects the device characteristics. In this experiment,
Since an ordinary LPCVD apparatus is used, when the boat descends after the annealing process for growing the HSG, the air seems to enter the furnace and oxidize the HSG surface. Little difference was seen. FIG. 4 shows the state of the apparatus when the boat descends.

FIG. 5 shows the amount of increase in the electrode surface area, the extent of expansion of the depletion layer of the capacitor, and the grain shape depending on the annealing time. As a result, a state in which the depletion layer optimal for the device characteristics is not extended and a high capacitance is realized.
It can be seen that the optimum annealing time has a very narrow range. In practice, it is found that about 14 minutes is optimal.

The reason is that the annealing time is 10 minutes,
If the length is too short, the grain growth is insufficient and the capacity increase rate is low. In addition, the annealing time is reduced from 16 minutes to 20 minutes.
As the length increases, the rate of increase in capacity increases, but the grains constituting the surface irregularities grow on the base in a shape very close to a sphere.

As a result, the area where the underlying polysilicon and the HSG contact each other is reduced, so that the paths through which phosphorus can diffuse into the grains are reduced, and the phosphorus concentration in the grains cannot be sufficiently increased. It grows.

As described above, the annealing process for 14 minutes was the optimum HSG formation condition for the device characteristics.
However, when the HSG forming process employing the 14 minute annealing process was continuously performed, a new problem occurred. The problem is that particles increase significantly.

When the process was repeated five times, about 500 particles were generated on the 6-inch wafer. When the cause of the generation was examined, 14 hours after flowing silane gas.
If the evacuation time is as short as one minute, the inside of the furnace will not be sufficiently purged, so that when the boat 205 descends, organic matter and moisture in the atmosphere enter the furnace and react strongly with the remaining silane gas to generate particles. Became clear. In particular, the generation of dust in the exhaust pipe was remarkable.
As described above, under the condition of generating particles, even when the device is manufactured, the probability of obtaining a good product due to dust is reduced.

Then, a silane gas is flowed, and after that, an annealing process is continuously performed for 14 minutes. Thereafter, an oxygen gas is introduced into the furnace of the reaction section 201 at a pressure of 0.1 Torr for 2 minutes, and then a nitrogen gas is supplied at a flow rate of 500 sccm. While flowing
A method of purging for 20 minutes in an atmosphere of 0.1 Torr and lowering the wafer setting boat 205 was studied. As a result, generation of particles could be suppressed. Further, in the furnace of the reaction section, HSG having a shape and a size optimal for device characteristics could be formed uniformly. The decrease in particles is due to release to the atmosphere (when the boat 205 descends).
I think that it was because enough purge was done before. The reason why the shape and size of the HSG do not change during the purging is considered to be that the addition of oxygen gas oxidized the surface of the silicon film and suppressed migration of the silicon film on the film surface.

The same effect can be obtained by using N ₂ O or O ₃ gas instead of oxygen gas. In addition, even if the gas is different from the above, any gas that suppresses migration of the silicon film by attaching or reacting to the silicon film surface can be used instead of oxygen gas.

[0068]

As described above, according to the present invention, when a hemispherical or mushroom-like grain is formed by annealing in a furnace in a reaction section, the shape and size of the grain become optimal for the device. At this point, by adding a gas such as oxygen, migration of silicon atoms on the surface of the silicon film can be suppressed, and a grain having an optimal shape can be obtained.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a semiconductor manufacturing apparatus for performing a method of manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a specific semiconductor manufacturing apparatus for performing the semiconductor device manufacturing method according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram illustrating a semiconductor manufacturing apparatus for performing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram showing an operation state of a semiconductor manufacturing apparatus for performing a method of manufacturing a semiconductor device according to a second embodiment of the present invention.

FIG. 5 is a view illustrating a manufacturing method according to a second embodiment of the present invention.
FIG. 4 is a characteristic diagram showing an increase amount of an electrode surface area, a degree of expansion of a depletion layer of a capacitor, and a grain shape due to a difference in annealing time.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Wafer 100 Semiconductor substrate 101 Device layer 11 Sample chamber 12 Reaction chamber 13 Wafer transfer chamber 23 Cassette 14 Door 21 Vacuum pump 22 Wafer transfer robot 201 Reaction section 202 Bellows 24, 207 Heater 25 Main vacuum pump 26 Dry pump 205 Wafer installation Boat 204 Installation table 206 Dummy wafer

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device in which microcrystal grains on an amorphous silicon surface are grown by annealing treatment, wherein the surface migration of silicon atoms is inhibited when the microcrystal grains reach a desired size. A method for manufacturing a semiconductor device, wherein grain growth is stopped by adding a gas. 2. The method according to claim 1, wherein a gas containing an oxygen atom is added as the gas that inhibits migration. 3. The method according to claim 1, wherein the addition of the gas is performed under the same conditions as an annealing temperature for growing fine crystal grains. 4. The method according to claim 1, wherein the annealing for growing the fine crystal grains is performed in a vacuum or in an inert gas or nitrogen atmosphere. 5. The addition pressure of the gas is 1 × 10 ⁻² To.
2. The method according to claim 1, wherein the pressure is set to be higher than rr. 6. The method according to claim 1, wherein the shape of the formed fine crystal grains is a hemisphere or a mushroom. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the concentration of impurities diffusing into the grains is controlled by controlling the shape of the hemisphere or mushroom gray.