GB2327299A - Method of manufacturing silicon hemispherical grains - Google Patents

Abstract

Silicon crystal nuclei are formed on an amorphous silicon layer surface in a silicon-containing gas, eg silane, atmosphere at a temperature of around 560‹C. The wafer is then annealed in vacuum, or in an inert gas atmosphere, for a predetermined time to form hemispherical silicon grains (HSGs) around the nuclei. The grains are formed by the surface migration of silicon atoms from the amorphous layer towards the nuclei. A gas, eg O 2 , N 2 O, O 3 , for preventing the surface migration of the silicon atoms is supplied upon completion of annealing, thereby stopping HSG growth. By stopping HSG growth before removal of many wafers from the anneal chamber the size and shape of the HSGs on each wafer can be made more uniform. The hemispherical grains are used ti increase the surface area of a capacitor electrode used in a DRAM.

Description

Specification Title of the Invention Method of Manufacturing Semiconductor Device Background of the Invention The present invention relates to a method of manufacturing a semiconductor device, for example, a method of forming a silicon film with an uneven surface.

Recently, demands arise for higher integration degrees of semiconductor memory devices such as a dynamic random access memory (DRAM). To meet the demands, the area necessary for each memory cell is also greatly reduced.

For example, a l-Mbit or 4-Mbit DRAM employs a design rule with a minimum design width of 0.8 pm. A 16-Mbit DRAM employs a design rule with a minimum design width of 0.6 pm or less. A smaller memory cell area decreases the storage charge amount of the memory cell. Therefore, as the integration degree increases, the charge amount necessary for the memory cell becomes difficult to ensure.

To ensure the charge amount necessary for the memory cell, a memory cell having a trench or stacked capacitor has been proposed and put into practical use.

Of such memory cells, one having a stacked capacitor is advantageous in higher soft error resistance than one having a trench capacitor. In addition, this memory cell does not damage a silicon substrate and thus is expected to be a next-generation memory cell structure. Further, it is also examined to enhance the a-ray resistance in the trench by changing the trench capacitor into a stacked trench structure.

Therefore, the stacked memory cell is a promising next-generation structure.

As a stacked capacitor applicable to 64-Mbit or higher DRAMs, one using an HSG (HemiSpherical Grain) technique has been proposed. According to the HSG technique, many hemispherical or mushroom-shaped grains are formed on the surface of a capacitor storage electrode to substantially increase the surface area of the storage electrode, thereby realizing a large capacitance.

A method of forming the storage electrode with hemispherical grains has been disclosed in Japanese Patent Laid-Open No. 3-272165 (reference 1). In the method disclosed in reference 1, hemispherical grains are formed during silicon film growth by LPCVD (Low Pressure Chemical Vapor Deposition) at a transition temperature at which an amorphous silicon film changes into a polysilicon film. The obtained film can be applied to the lower electrode of a stacked capacitor to greatly increase the surface area of the electrode and the storage charge amount.

Japanese Patent Laid-Open No. 3-263370 (reference 2) has disclosed a method of increasing the surface area of an electrode during LPCVD silicon film growth at a transition temperature at which an amorphous silicon film changes into a polysilicon film though the surface state is unknown.

Watanabe et al., "Device application and structure observation for hemispherical-grained Si", Journal of Applied Physics, Vol. 71, No. 7, pp. 3,538 3,543, April 1992 (reference 3) reveals the growth mechanism of hemispherical or mushroom-shaped grains.

That is, grains forming an uneven surface are formed not during CVD silicon film growth but during annealing just after silicon film growth.

More specifically, amorphous silicon is deposited during CVD growth. During annealing after the deposition, microcrystal nuclei are thermally formed on the surface of the amorphous silicon film. The " microcrystal nuclei capture silicon atoms migrating through the amorphous silicon surface, grow to a large size, and form hemispherical or mushroom-shaped grains.

According to reference 3, if the silicon film is exposed to air upon deposition of amorphous silicon, no hemispherical or mushroom-shaped grains are formed because the amorphous silicon surface changes into a thin oxide film to suppress the surface migration of silicon atoms.

In recent years, techniques of forming an uneven surface are further improved. For example, Japanese Patent Laid-Open No. 8-306646 (reference 4) has proposed a method of decreasing the grain density and size. According to reference 4, a gas e.g., silane gas is supplied to the surface of an amorphous silicon film processed into an electrode shape in advance without any native oxide film in order to supply silicon atoms serving as nuclei. Using the formed nuclei as a center, peripheral silicon atoms are collected to form large grains, i.e., hemispherical or mushroom-shaped grains on the surface.

In this method, the grain density is basically controlled by the silane gas supply time, while the grain size is controlled by the annealing time.

Reference 4 also proposes a method of exposing the substrate to an oxidizable gas during annealing after supply of the silane gas in order to control the grain density. At this time, the oxidizable gas is supplied at a pressure of about 0.01 Torr. At this pressure, supply of oxygen suppresses formation of nuclei on the surface of the amorphous silicon film.

However, grains continuously grow because migration of silicon atoms is not completely suppressed.

The grain size is basically controlled by the annealing time.

The stacked capacitor having an uneven electrode surface is manufactured as follows. First, an interlevel insulating film is formed on a substrate including a semiconductor device such as a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). In this interlevel insulating film, a contact hole is formed. A silicon film to be finally electrically connected to the semiconductor device via the contact hole is deposited.

This silicon film is patterned into a lower electrode.

The surface of this lower electrode is made uneven by the above-described technique and the like. After the lower electrode is made uneven, a capacitor insulating film and an upper electrode are sequentially stacked to obtain a stacked capacitor.

As described above, the size of hemispherical or mushroom-shaped grains constituting the uneven surface is controlled by the annealing time. If, however, the annealing time changes for each wafer, the grain size also varies for each wafer. As a result, the i storage charge amount of the capacitor changes, and device characteristics also vary.

For this reason, the annealing time is controlled as accurate as possible in order to unify the grain size. The present inventor, however, experimentally found that DRAMs cannot be mass-produced by controlling the grain size and shape which impart optimum device characteristics by only the annealing time due to the following reasons.

For example, when many hemispherical or mushroom-shaped grains are formed by a single-wafer apparatus, they must be grown within a relatively short time. To complete the growth of grains within a short time, the temperature is appropriately 5500C or more.

At this temperature, annealing is also performed. In the single-wafer apparatus, an annealed wafer is unloaded after the wafer temperature decreases to a certain degree. The decrease in wafer temperature depends on a film formed on the wafer or a difference in device structure.

In practice, reference 4 describes that the wafer cannot be quickly cooled to such a degree as to eliminate the influence of annealing upon supply of silane gas because the heat capacity of a silicon substrate, a heater, and the like have strong influences. In this manner, the annealing time is difficult to strictly control.

Also, when HSG is formed by a batch apparatus, the annealing time is difficult to strictly control. In the batch system, the annealing time may be relatively long because a larger number of wafers are processed.

Therefore, the difference in temperature decrease rate owing to the type of wafer and the difference in film quality hardly influences device characteristics.

However, the batch apparatus suffers the following problems. For example, in a growth method using a batch CVD system having a load-lock chamber, the grain growth annealing time varies because wafers are unloaded from a heated furnace and cooled.

In a general LPCVD apparatus, wafers are aligned in line on a boat, loaded into a furnace, and processed. When the wafers are unloaded to be cooled upon completion of the processing, a wafer at an inner portion of the furnaces stays longer in a heated zone, whereas a wafer near the exit of the furnace stays shorter in the heated zone.

In the load-lock system, since the furnace contains less oxygen and the like, grains continuously grow upon extracting the wafers. Consequently, the grain size changes due to a difference in thermal hysteresis upon unloading of the wafers.

Summarv of the Invention It is an object of the present invention to provide a method of manufacturing a semiconductor device having a stacked capacitor with desired characteristics by forming a lower electrode with good reproducibility.

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of forming crystal nuclei on an amorphous silicon surface of a wafer in a gas atmosphere under a predetermined condition, annealing the wafer for a predetermined time to grow the crystal nuclei and form hemispherical grains (HSGs), and supplying a gas for preventing surface migration of silicon atoms upon completion of annealing, thereby stopping HSG growth.

Brief Description of the Drawings The present invention will be described, by way of example, with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing the schematic arrangement of a first embodiment of a semiconductor manufacturing apparatus; Fig. 2 is a block diagram showing the detailed structure of the semiconductor manufacturing apparatus shown in Fig. 1; Fig. 3 is a block diagram showing the detailed structure of a second embodiment of a semiconductor manufacturing apparatus; Fig. 4 is a block diagram showing the operation state of the semiconductor manufacturing apparatus shown in Fig.

3; and Fig. 5 is a graph showing the electrode surface area increase rate of an HSG capacitor depending on the annealing time, the capacitance change rate of the HSG capacitor, and the grain shape in the use of the semiconductor manufacturing apparatus shown in Fig. 3.

DescriDtion of the Preferred Embodiments First Embodiment Fig. 1 shows the schematic arrangement of a first embodiment of semiconductor manufacturing apparatus.

Referring to Fig. 1, the semiconductor manufacturing apparatus comprises a wafer chamber 11 into which wafers are loaded, and a reaction chamber 12 for processing a wafer and generating an HSG-Si film on the wafer surface. A wafer transfer chamber 13 kept in vacuum is arranged between the wafer chamber 11 and the reaction chamber 12. A wafer is made of amorphous silicon before loading into the wafer chamber 11, and amorphous silicon forms the wafer surface. Reference numeral 14 denotes a door for opening/closing the wafer chamber 11.

More specifically, a wafer to be loaded into the wafer chamber 11 comprises a semiconductor substrate on which a semiconductor device such as a MOSFET is formed, an interlevel insulating film with a contact hole which is formed on the semiconductor substrate, and patterned amorphous silicon to be finally electrically connected to the semiconductor device via the contact hole. The upper and side surfaces of the amorphous silicon are exposed. The upper and side surfaces of the amorphous silicon and the upper surface of the interlevel insulating film form the wafer surface. The semiconductor substrate and the amorphous silicon that are processed in the above manner will be generally called a wafer. Hemispherical or mushroom-shaped grains on the surface of the silicon film will be called HSGs.

In Fig. 1, the wafer is loaded by a carriage via the door 14 attached to the wafer chamber 11 into the wafer chamber 11 kept by a vacuum pump (to be described later) at a vacuum degree equal to or lower than a partial pressure of water of about 1 x 10-6 Torr.

The native oxide film on the surface of the wafer loaded into the wafer chamber 11 is removed with an aqueous HF solution in advance.

In the semiconductor manufacturing apparatus having this arrangement, the wafer is guided from the wafer chamber 11 to the wafer transfer chamber 13 via a gate valve (not shown). The wafer transfer chamber 13 incorporates a transfer robot (to be described later).

The transfer robot in the wafer transfer chamber 13 transfers the wafer from the wafer transfer chamber 13 to the reaction chamber 12.

The reaction chamber 12 comprises a chamber portion formed of silica, SiC, or the like, and an air isolation bellows arranged below the chamber portion.

The isolation bellows can move the wafer from which an impurity gas is removed in a predetermined direction, e.g., a horizontal direction perpendicular to the transfer direction.

Fig. 2 shows the detailed structure of the semiconductor manufacturing apparatus shown in Fig. 1.

As shown in Fig. 2, a wafer boat 205 capable of storing a plurality of wafers 10 is arranged on a susceptor 204 in a reaction chamber 201. An inlet pipe 203 for introducing a silicon-containing gas such as silane (SiH4) gas and an inert gas such as N2 gas is connected to the reaction chamber 201. The susceptor 204 and the wafer boat 205 are fixed to isolation bellows 202 in the reaction chamber 201, and can move inside the reaction chamber 201 in a horizontal direction perpendicular to the transfer direction in response to the expansion and contraction of the isolation bellows 202.

The reaction chamber 12 is evacuated by a main vacuum pump 25 (and an auxiliary vacuum pump) and kept in vacuum. The reaction chamber 12 is surrounded by a heater 207 formed of a coil. Reference numeral 21 denotes a vacuum pump for keeping the wafer chamber 11 and the wafer transfer chamber 13 in vacuum; 22, a wafer transfer robot arranged in the wafer transfer chamber 13; 23, a cassette arranged in the wafer chamber 11 to store the wafers 10; 26, a dry pump connected to the main vacuum pump 25; and 206, a dummy wafer mounted on the wafer boat 705.

Before a wafer is loaded into the reaction chamber 201, silane gas as a silicon-containing gas is introduced into the reaction chamber 201 via the inlet pipe 203. At this time, the reaction chamber 201 is kept by the main vacuum pump 25 at a vacuum degree of about 1 x 10 Torr and a temperature equal to or higher than the silicon-containing gas decomposition temperature, e.g., 5600C. Note that the silicon-containing gas may be introduced at an HSG formation temperature.

In this atmosphere, the wafer 10 is guided from the wafer transfer chamber 13 to the reaction chamber 12. After the wafer temperature is stabilized, silane gas is supplied onto the wafer 10 at a flow rate of 50 sccm. The silane gas decomposes on the amorphous silicon surface of the wafer and forms crystal nuclei.

Upon the supply of the silane gas, each wafer 10 is annealed in vacuum for 10 min to form HSGs on the upper and side surfaces of the amorphous silicon.

That is, 50 wafers were set by the carrier cassette 23 shown in Fig. 2 in all the slots of the boat 205 from the top side (gas inlet pipe 203 side) to the bottom side (susceptor 204 side), and subjected to HSG growth. As a result, HSGs were formed on all the wafers 10 from the top to bottom of the boat 205, but their shapes and sizes were different depending on positions inside the boat 205. A grain size on the upper side of the boat 205 was larger than that on the lower side.

The grain shape on the upper side was nearly spherical, and its contact area with the lower electrode was narrow.

More specifically, the grain size on the upper side was about 800 , whereas the grain size on the lower side was about 700 A. However, the HSG density itself did not have a large difference.

To investigate the cause, the down rate of the boat 205 upon completion of annealing in the HSG formation process was changed. As a result of a comparison between down rates of 10 mm/min and 400 mm/min in the boat 205, the difference in grain size between boat positions was larger at the lower down rate. At the down rate of 10 mm/min, HSGs on the wafers 10 on the upper side of the boat 205 grew to a large size, and most of them were coupled to each other.

To the contrary, at the down rate of 400 mm/min, HSGs on wafers 10 growing on the upper side of the boat 205 were larger in grain size than HSGs on wafers 10 growing on the lower side of the boat 205, but most of them were not coupled to each other.

From these results, in the load-lock type manufacturing apparatus, HSGs continuously grow while the boat 205 moves down because the oxygen concentration and the partial pressure of water are low in the apparatus. The grains on the upper side of the boat 205 grow to a large size because the wafers 10 on the upper side pass through a zone heated by the heater 207 at a lower speed.

To solve this problem and form uniform HSGs independently of positions in the boat 205, the HSG growth is completely stopped at a proper size, and this effect is maintained even in moving down the boat 205.

For this reason, upon completion of annealing in the HSG formation process, oxygen gas was supplied to oxidize the wafer surface and suppress surface migration of silicon atoms.

More specifically, supply of silane and annealing were performed at 5600C, then oxygen gas was supplied, and the boat 205 was moved down at a boat down rate of 10 mm/min. At this time, the oxygen gas was supplied for 2 min and 5 min at three oxygen supply pressures, i.e., 0.005 Torr, 0.01 Torr, and 0.1 Torr.

Consequently, at 0.005 Torr, the positional dependency of the boat 205 hardly influenced the grain size, compared to the case of supplying no oxygen.

However, the grain growth degree was higher for the wafers 10 (grain size: 850 A) on the upper side of the boat 205 than for the wafers 10 (grain size: 750 ) on the lower side of the boat 205. The difference in grain size was smaller in supply for 5 min than in supply for 2 min.

Even when oxygen was supplied at 0.01 Torr for 2 min, grain sizes were slightly different between the upper and lower sides of the boat 205. When the boat 205 was moved down after oxygen was supplied for 5 min, the grain size was 700 regardless of positions in the boat 205. Further, the grain shape was also independent of positions in the boat 205. When oxygen was supplied at 0.1 Torr, uniform HSGs were obtained independently of the supply time and boat positions. In this case, the grain shape was almost equal to that obtained when oxygen was supplied at 0.01 Torr for 5 min.

From the above results, by supplying oxygen under appropriate conditions, the grain growth can be suppressed, and the influence in moving down the boat 205 can be completely eliminated.

Second Embodiment In the second embodiment, HSGs are formed by the method described in reference 1 using a vertical LPCVD apparatus shown in Fig. 3 in place of the load-lock type apparatus. In the apparatus shown in Fig. 3, the wafer chamber 11, the wafer transfer chamber 13, the vacuum pump 21, the main vacuum pump 25, and the bellows 202 are omitted from the apparatus shown in Fig. 2.

In this process, hemispherical grains are formed during LPCVD silicon film growth at a transition temperature at which an amorphous silicon film changes into a polysilicon film. The obtained film can be applied to the lower electrode of a stacked capacitor to greatly increase the surface area of the electrode and the storage charge amount.

The HSG growth temperature in the apparatus shown in Fig. 3 was measured to be 5900C by an internal thermocouple. On the other hand, the temperature by an external thermocouple was 5500C. At this temperature, silane gas was flowed at 500 sccm and a pressure of 1 Torr to deposit a 1,000- thick silicon film on a phosphorus-doped polysilicon film. The resultant structures were annealed in the reaction section for 10, 12, 14, 16, 18, 20, and 30 min.

After that, a capacitor insulating film was formed by thermal nitridation process + CVD nitride film growth + nitride film oxidization, and a polysilicon electrode was deposited as an upper electrode. An impurity was diffused in HSGs by thermally diffusing phosphorus-doped polysilicon below HSGs into the HSGs during heating in forming a capacitor film.

Wafers upon HSG growth were observed to find that HSGs were formed on the wafer surfaces regardless of the annealing time. However, the HSG shape depended on the annealing time, which influenced device characteristics. This is because a general LPCVD apparatus used in this experiment allowed air to enter the furnace to dxidize HSG surfaces in moving down a boat 205 upon HSG growth annealing. Therefore, the HSG shape and size hardly depended on positions in the boat 205. Fig. 4 shows the state wherein air enters the furnace in moving down the boat 205.

Fig. 5 shows an electrode surface area increase rate (maximum capacitance value of HSG capacitor/maximum capacitance value of general capacitor) A depending on the annealing time, a capacitance change rate (minimum capacitance value/maximum capacitance value of HSG capacitor) B of the HSG capacitor in accordance with the extension degree of the depletion layer of the capacitor, and a grain shape C. As is apparent from Fig. 5, the state optimum for device characteristics wherein the depletion layer does not extend, and the annealing time optimum for realizing a large capacitance are greatly limited.

In practice, the optimum annealing time is about 14 min.

This is because grains cannot satisfactorily grow for a short annealing time of 10 min or 12 min, and the capacitance increase rate A is low. If the annealing time increases to 16 min or 20 min, the capacitance increase rate A becomes higher, but grains constituting an uneven surface substantially spherically grow on the underlayer.

Accordingly, the contact area of HSGs with the polysilicon underlayer decreases, the path allowing phosphorus to diffuse into grains narrows, and the phosphorus concentration in grains cannot sufficiently increase. Consequently, the depletion layer extends to decrease the capacitance change rate B of the HSG capacitor.

As described above, 14-min annealing was an HSG formation condition optimum for device characteristics. However, a continuous HSG formation process employing 14-min annealing posed a new problem.

This problem is an increase in number of particles.

The process repeatedly performed five times generated about 500 particles on a 6" wafer. The generation cause was examined to find that, since the furnace could not be satisfactorily purged for a short evacuation time of 14 min after supply of silane gas, an organic substance or water in air entered the furnace in moving down the boat 205 and strongly reacted with the remaining silane gas to generate particles. In particular, dust was prominently generated at the exhaust pipe portion. Even if devices are manufactured under the particle generation conditions, the non-defective probability decreases due to dust.

For this reason, after silane gas was supplied, and annealing was subsequently performed for 14 min, oxygen gas was introduced into the furnace of a reaction section 201 at a pressure of 0.1 Torr for 2 min. While nitrogen gas was supplied at 500 sccm, the furnace was purged at 0.1 Torr for 20 min, and the boat 205 was moved down. As a result, generation of particles could be suppressed. In the furnace of the reaction chamber 12, uniform HSGs having a shape and size optimum for device characteristics could be formed.

The number of particles decreased because the furnace could be satisfactorily purged before being opened to air (the boat 205 was moved down). The HSG shape and size did not change during the purge because oxygen gas was supplied to oxidize the surface of the silicon film and suppress migration of the silicon film on its surface.

Note that the same effects can be obtained even with NzO gas or Q gas instead of oxygen gas. In addition, any type of gas can replace oxygen gas as far as the gas attaches to or reacts with the surface of the silicon film to suppress migration of the silicon film.

As has been described above, in forming hemispherical or mushroom-shaped grains by annealing in the furnace of the reaction chamber, e.g., oxygen gas is supplied when grains attain a shape and size optimum for devices.

Accordingly, migration of silicon atoms on the surface of the silicon film can be suppressed to obtain grains having an optimum shape.

Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.

Statements in this specification of the "objects of the invention" relate to preferred embodiments of the invention, but not necessarily to all embodiments of the invention falling within the claims.

The description of the invention with reference to the drawings is by way of example only.

The text of the abstract filed herewith is repeated here as part of the specification.

In a method of manufacturing a semiconductor device, crystal nuclei are formed on an amorphous silicon surface of a wafer in a gas atmosphere under predetermined conditions. The wafer is annealed for a predetermined time to grow the crystal nuclei and form hemispherical grains (HSGs). A gas for preventing surface migration of silicon atoms is supplied upon completion of annealing, thereby stopping HSG growth.

Claims (12)

1. A method of manufacturing a semiconductor device, characterized by comprising the steps of: forming crystal nuclei on an amorphous silicon surface of a wafer in a gas atmosphere under a predetermined condition; annealing said wafer for a predetermined time to grow the crystal nuclei and form hemispherical grains (HSGs); and supplying a gas for preventing surface migration of silicon atoms upon completion of annealing, thereby stopping HSG growth.

2. A method according to Claim 1, wherein the gas for preventing surface migration of silicon atoms comprises a gas containing oxygen atoms.

3. A method according to Claim 1 or 2, wherein the annealing of the wafer and the supply of the gas for preventing surface migration of silicon atoms are performed under the same conditions.

4. A method according to any preceding claim, wherein the gas for preventing surface migration of silicon atoms is selected from the group consisting of oxygen gas, N2O gas, and 03 gas.

5. A method according to any preceding claim, wherein annealing for HSG growth is performed in an atmosphere selected from the group consisting of vacuum, an inert gas atmosphere, and a nitrogen gas atmosphere.

6. A method according to any preceding claim, wherein the gas for preventing surface migration of silicon atoms is supplied at a pressure higher than 1 x 10-2 Torr.

7. A method according to any preceding claim, wherein the formed HSGs have either a hemispherical shape or a mushroom shape.

8. A method according to any preceding claim, wherein shapes of the HSGs are controlled by an annealing time, thereby controlling a concentration of an impurity diffused to the grains.

9. A method according to any preceding claim, wherein the predetermined annealing time is a time for the HSGs to reach a predetermined shape.

10. A method according to any preceding claim, wherein the step of growing crystal nuclei comprises the step of supplying a silicon-containing gas onto a surface of said wafer in a reaction chamber kept in vacuum at not less than a silicon-containing gas decomposition temperature.

11. A semiconductor device manufacturing method of growing microcrystal grains on an amorphous silicon surface by annealing to form hemispherical grains (HSGs), characterized by comprising the step of: stopping HSG growth by supplying a gas for preventing surface migration of silicon atoms when the grains reach a desired size.

12. A method of manufacturing a semiconductor substantially as herein described with reference to Figure 2 or Figure 3 of the accompanying drawings.