JPH1138957A - Vram-mapping method for image data and image data display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the circuit scale, to shorten the development period and speed up the development, by mapping display screen data for one line mapped by a display screen memory (VRAM) so that the display screen data become powers of 2, and mapping the upperleft corner of the display screen to agree with the upperleft corner of VRAM. SOLUTION: Image data displayed on a LCD monitor are mapped so as to be located in the upper central part of the VRAM space. The VRAM is arranged in rows of two banks of 1MB VRAMs, and in order to set one line to powers of 2, the LCD monitor display screen is devided in two to be scanned, and the mapping is carried out so that the scanning split point on the display screen agrees with the bank change-over point of the VRAM. Then, the lower region of the LCD monitor for 1600×176 pixels remains without being mapped by VRAM, and since the mapping is not done on the left of bank 1 and the right of bank 2, the region is left over. Therefore, the area of the above- mentioned 1600×176 pixels is mapped in this part.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for VR of image data.
The present invention relates to an AM mapping method and an image display system using the same.

[0002]

2. Description of the Related Art In the personal computer market, with the price reduction and the growing demand for networks such as e-mail and the Internet, which can be said to be the destruction of the price at present, business will be expanded more aggressively by using personal computers as a weapon. There are companies that aim to introduce more than one personal computer for each purpose.

Under such demands, naturally, the demands for space saving and energy saving are increasing for the equipment constituting the personal computer system, and especially for the display monitor which is the face of the man-machine interface. As a means to satisfy this, LCD monitors have spread,
Liquid crystal (LCD) with high visibility such as color TFT has been frequently used, and recently, SVGA, and furthermore, XGA
12 inch or higher resolution with high resolution that supports is now standard.

[0004] An LCD monitor is composed of many pixels, and image data is displayed by changing the state of each pixel. FIG. 10 shows the relationship between the LCD display screen and the VRAM. VRAM 20 is LCD
10 for storing image data to be displayed on the LCD
Scanned by the controller 30, the image data is transferred to the LCD monitor 10, and the LCD monitor 10 changes the state of each pixel and displays the transferred data as an image. In the figure, arrows in the VRAM 20 indicate areas where image data corresponding to the respective display rows 1 to 4 of the LCD monitor 10 are stored.

[0005]

The mapping of the image data to the VRAM 20 is as shown in FIG.
The processing is performed linearly in order from the first pixel of the first row of data displayed on the LCD monitor 10 to the right. LCD
The controller 30 reads these image data linearly from the VRAM 20 and transfers them to the LCD monitor 10 to display images.

According to the above-described conventional VRAM mapping method, since image data is stored linearly in the VRAM 20, an address of the VRAM 20 is calculated in an image display device in which the LCD monitor 10 can be used not only vertically but also horizontally. Required complicated address translation. Therefore, it is necessary to design hardware for that purpose, and the circuit design is complicated, the circuit scale is increased, and the processing speed is reduced.

The present invention has been made in view of the above circumstances, and by using a novel VRAM mapping method, it is possible to easily follow the vertical and horizontal use of an LCD and simplify address conversion for reading a VRAM. Accordingly, an object of the present invention is to provide a VRAM mapping method of image data capable of reducing a circuit scale, a development period, and speeding up, and an image display system using the method.

[0008]

According to the method of mapping image data of the present invention, in an image display system having a display screen memory (VRAM) having a larger capacity than the resolution of the display screen, one line mapped to the VRAM is provided. Are mapped so as to be a power of two, and the mapping is performed such that the upper left corner of the display screen matches the upper left corner of the VRAM.

When a display screen having a resolution of N × M dots is mapped to a VRAM by arranging k banks each composed of n × m (power of 2) Q bits, the display screen is divided into k and scanned. The mapping is performed so that the scan division point of the display screen matches the bank switching point of the VRAM, and the bit array of N × (M−m) dots that are out of the VRAM space is a higher order pixel address indicated by the Y coordinate. Q / 2 bits are upper Q / 2 bits of the converted X coordinate, lower Q / 2 bits indicating the Y coordinate are upper Q / 2 bits of the converted Y coordinate, and upper Q / 2 bits indicating the X coordinate. Is the lower Q / 2 bits indicating the converted Y coordinate.

The image display system of the present invention has a capacity larger than the resolution N × M dots of the display screen, and stores a VRAM for storing the display screen data and two rows of display screen data mapped to the VRAM. And a memory control device that performs mapping so that the upper left corner of the display screen matches the upper left corner of the VRAM, and reads and writes the display screen data. Also, k banks composed of n × m (power of 2) bits are arranged, and a VRAM to which display screen data having a resolution of N × M is mapped, and the display screen are divided into k and scanned and displayed. Mapping is performed so that the scan division point on the screen matches the bank switching point of the VRAM,
The bit array of N × (M−m) dots that are viewed from the space is the upper Q / 2 of the pixel address indicated by the Y coordinate.
The bits are set to the upper Q / 2 bits of the converted X coordinate, and the lower Q / 2 bits indicating the Y coordinate are set to the upper Q / bit of the converted Y coordinate.
A memory control device for reading and writing data, comprising 2 bits, upper Q / 2 bits indicating the X coordinate and lower Q / 2 bits indicating the converted Y coordinate.

As a result, it is possible to easily follow the vertical and horizontal use of the LCD, simplify the address conversion for reading the VRAM, reduce the circuit scale, shorten the development period, and realize high-speed processing.

[0012]

FIG. 1 is a block diagram showing a configuration example of an image display system according to the present invention. In the figure, 1 is L
The CD monitor and 2 are VRAMs. Reference numeral 3 denotes a VRAM controller, which supports a VRAM mapping method described later and reads and writes data stored in the VRAM 2. A graphic controller 4 generates image data for drawing image data in the VRAM 2.

Reference numeral 5 denotes an LCD controller, which is a VRA
M2 and LCD monitor 1 are interfaced. The LCD controller 5 includes a vertical clock latency circuit 51, F
IFO buffer 52, frame frequency control circuit 53, L
It comprises a CD drive circuit 54. The vertical clock latency circuit 51 and the frame frequency control circuit 53
The image data transferred to the FIFO buffer 52 under the control of the RAM controller 3 is stored in the LCD drive circuit 5.
4 to generate various control signals. The LCD drive circuit 54 performs XY driving of the LCD monitor 1 according to the image data written in the FIFO buffer 52, and performs color or gradation control.

FIGS. 2 to 4 are views cited for explaining the operation of the embodiment of the present invention, and show the screen configuration of the LCD monitor 1, the VRAM address space, and the address map of the VRAM 2, respectively. LC used in embodiments of the present invention
The D monitor 1 has a resolution of 1600 × 1200 pixels. VRAM2 has a capacity of 2M (mega) bytes,
A two-bank configuration in which 1 Mbyte VRAMs are arranged side by side is employed.

The LCD monitor 1 shown in FIG.
Mapping to the RAM 2 is performed by the method shown in FIG. That is, the image data displayed on the LCD monitor 1 is mapped so as to be located at the upper center of the VRAM space. Specifically, VRAM2 is
Since a 1 Mbyte VRAM 2 is arranged horizontally in two banks, the display screen of the LCD monitor 1 is divided into two and scanned, and the mapping is performed so that the scan division point of the display screen matches the bank switching point of the VRAM 2. Do.

With this mapping, the area of 1600 pixels × 176 pixels at the bottom of the LCD monitor 1 is not mapped to the VRAM 2 and is left behind. However, since the left side of the bank 1 and the right side of the bank 2 are not mapped, the area is left. Therefore, the area data of 1600 × 176 pixels is mapped to this portion. The mapping of this part can be realized by changing the bit arrangement of the pixel address.

1600 × 17 outside the VRAM space
In the bit array of 6 pixels, of the pixel address, the upper 5 bits indicated by the Y coordinate are set as the upper 5 bits of the converted X coordinate, and the lower 5 bits indicating the Y coordinate are converted to the converted Y coordinate.
This can be realized by setting the upper 5 bits of the coordinate and the upper 5 bits indicating the X coordinate as the lower 5 bits indicating the converted Y coordinate.

In the embodiment of the present invention, the operation of the vertical / horizontal conversion when the LCD is changed from the vertical use to the horizontal use will be described. In this case, various parameters such as coordinates in vertical use are converted into parameter values in horizontal use, and the transfer itself is
This is performed by the transfer mechanism in the horizontal use mode. FIG.
Shows the mechanism of parameter conversion. (A) shows various parameters for vertical use, and (b) shows various parameters for horizontal use.

In FIG. 5, the parameters (x, y) for the vertical use are the coordinates of the upper left vertex of the transfer source rectangular area,
(P, q) is the coordinates of the upper left vertex of the transfer destination rectangular area, w is the width of the transfer rectangular area, and h is the height of the transfer rectangular area. In the case of horizontal use, parameters (X, Y) are the coordinates of the upper left vertex of the transfer source rectangular area, (P, Q) are the coordinates of the upper left vertex of the transfer destination rectangular area, W is the width of the transfer rectangular area, and H is the width of the transfer rectangular area. Is the height of the transfer rectangular area. Since the parameter conversion is performed when changing from vertical use to horizontal use, parameter conversion in the present invention is executed by the following conversion formula. The execution of the conversion formula is performed by an arithmetic circuit built in the VRAM controller 3 shown in FIG.

(1) X = y (2) Y = 1200-xw (3) W = h (4) H = w (5) P = q (6) Q = 1200-pw From pixel address A method of restoring the XY coordinates of the VRAM 2 will be described with reference to FIG. VRAM2 space
Since one row is composed of 2048 pixels, the X coordinate is obtained from the lower 11 digits of the pixel address, and the Y coordinate is obtained from the upper 11 digits of the pixel address. Conversely, it is also easy to obtain the VRAM address. Also,
By performing mapping in this manner, a transfer address can be generated without worrying about the VRAM bank even at the center of the screen. That is, which bank of the VRAM2 is used is determined by the bit 10 of the pixel address.
Check to see. If bit 10 is "0", bank 1 is used, and if bit 10 is "1", bank 2 is used.

FIG. 7 is a flowchart showing the algorithm of VRAM mapping. Here, the Y coordinate is checked, and if it is smaller than 1024 pixels, the VRAM address is in the address configuration shown in FIG. 6 described above. If it is within the range of 1024 pixels, the VRAM address is shown in the address map shown in FIG. Mapping is performed through the indicated address translation. In FIG. 8, an example in which the hatched area is the resolution of the LCD monitor 1 and the memory capacity of the VRAM 2 is large both vertically and horizontally. The bit arrangement before and after the pixel address conversion in this case is shown in FIG.
Is shown in As described above, the top 5 indicated by the Y coordinate
The bits are the upper 5 bits of the converted X coordinate, the lower 5 bits indicating the Y coordinate are the upper 5 bits of the converted Y coordinate, and the upper 5 bits indicating the X coordinate are the lower 5 bits indicating the converted Y coordinate. And the lower 5 bits indicating the X coordinate are directly used as the lower 5 bits indicating the X coordinate.

The image transfer when the LCD monitor 1 is used vertically is performed by converting the transfer parameters into the parameters for the horizontal use, and is actually performed by a horizontal use mechanism.

As described above, according to the present invention, when mapping image data to the VRAM 2, the bank of the VRAM is constituted by one bank, and the image data is mapped to the LCD monitor 1.
When the mapping can be performed in the same manner as the display image for (i.e., does not protrude from the VRAM space), one row of the VRAM space is set to be a power of 2 so that the upper left corner of the display image matches the upper left corner of the VRAM space. It is to be mapped.

On the other hand, when mapping image data to the VRAM2, if one row in the VRAM space is set to a power of 2 and there are two banks in the VRAM space, the LCD
The monitor 1 is divided into left and right parts for scanning. At this time, L
If the image is mapped in the VRAM space in the same manner as the image displayed on the CD monitor 1, the lower image data to be displayed on the LCD monitor 1 protrudes and cannot be mapped. Are the upper 5 bits of the converted X coordinate, the lower 5 bits indicating the Y coordinate are the upper 5 bits of the converted Y coordinate, and the upper 5 bits indicating the X coordinate are the lower 5 bits indicating the converted Y coordinate. I do. As described above, the conversion of the pixel address is realized only by changing the dot position. At this time, the mapping to VRAM2 is performed by LC
The mapping is performed so that the division point of the scan of the D monitor 1 matches the division point of the bank of the VRAM 2, and the mapping is performed so that the first line of the image data coincides with the first line of the VRAM 2.

When an image is transferred using the LCD monitor 1 vertically, the coordinates (x, y) and (p, q) of the rectangular area before and after the transfer in the vertical use, the width w of the transfer area, and the height w H
Is converted into parameters of coordinates (X, Y) and (P, Q) of the rectangular area before and after transfer when the apparatus is used horizontally, and width W and height H of the transfer area, X = y, Y = M-x-
Using the equations of w, W = h, H = w, P = q, and Q = M−p−w, the transfer mechanism in horizontal use is also used in the case of vertical use using the parameters converted here. Things.

[0026]

As described above, according to the present invention, by using a novel VRAM mapping method, an LCD
VRAM mapping method of image data which can easily follow vertical and horizontal use of the image data, and simplifies the address conversion for reading the VRAM, thereby reducing the circuit scale, shortening the development period, and speeding up. , An image display system can be constructed. Further, the following effects can be obtained.

(1) By directly mapping the screen display image, the coordinates on the VRAM can be directly calculated.

(2) VRA that can map image data as displayed image by bank structure of VRAM
Even when the M space is not available, the coordinates on the VRAM can be easily calculated from the pixel address only by changing the bit arrangement of the pixel address.

(3) Even when the LCD monitor is used vertically, by utilizing the transfer mechanism in the horizontal use, circuit design and verification can be simplified, and bugs can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an image display system according to the present invention.

FIG. 2 is a diagram showing a configuration example of an LCD monitor used in the present invention.

FIG. 3 is a diagram showing a configuration of a VRAM space used in the present invention.

FIG. 4 is a diagram showing a VRAM mapping method used in the present invention expanded on a memory.

FIG. 5 is a diagram cited for explaining parameter conversion when the LCD monitor is used vertically.

FIG. 6 is a diagram showing a configuration of a pixel address used in the present invention.

FIG. 7 is a flowchart showing an algorithm for VRAM mapping used in the present invention.

FIG. 8 shows image data to be displayed on the LCD monitor as V
FIG. 4 is a diagram showing an area arrangement when mapping on a RAM.

FIG. 9 is a diagram cited for explaining a pixel address conversion operation;

FIG. 10 is a diagram cited for explaining a conventional VRAM mapping method.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... LCD monitor, 2 ... VRAM, 3 ... VRAM controller, 4 ... Graphic controller, 5 ... LCD controller, 51 ... Vertical clock latency circuit, 52
... FIFO buffer, 53 ... Frame frequency control circuit,
54 ... LCD drive circuit.

Claims (8)

[Claims] 1. An image display system having a display screen memory (VRAM) having a larger capacity than a resolution of a display screen, wherein one line of display screen data mapped to the VRAM is mapped to a power of two. And mapping the upper left corner of the display screen to the upper left corner of the VRAM. 2. A display screen having a resolution of N × M dots is represented by a bank constituted by n × m (power of 2 Q) bits.
When arranging and mapping to the VRAM, the display screen is divided into k and scanned, and the scan division point of the display screen is mapped so as to match the bank switching point of the VRAM, and N × (M−
m) VRAM of image data characterized by changing the bit arrangement of dots and mapping to a free area of VRAM
Mapping method. 3. N × (M−
m) The bit arrangement of the dots is the
The upper Q / 2 bits indicated by the Y coordinate are set as the upper Q / 2 bits of the converted X coordinate, the lower Q / 2 bits indicating the Y coordinate are set as the upper Q / 2 bits of the converted Y coordinate, and the X coordinate is indicated. 3. The VRAM mapping method for image data according to claim 2, wherein the upper Q / 2 bits are lower Q / 2 bits indicating the converted Y coordinate. 4. When the image information written in the VRAM is vertically and horizontally converted and transferred, the coordinates (x,
y), (p, q), the parameters of the transfer area width w and the height h, the coordinates (X, Y) and (P, Q) of the rectangular area before and after the transfer, the transfer area width W and the height H X =
y, Y = M−x−w, W = h, H = w, P = q, Q = M
4. The method according to claim 3, wherein each equation of -pw is used. 5. A VRA which has a capacity larger than a resolution N × M dots of a display screen and stores display screen data.
M, and one line of display screen data mapped to the VRAM is set to be a power of 2, and the upper left corner of the display screen is set to V
Map to match the upper left corner of the RAM,
A memory controller for reading and writing the display screen data. 6. A VRAM in which k banks composed of n × m (power of 2 Q) bits are arranged, and a display screen data having a resolution of N × M is mapped, and the display screen is divided by k and scanned. Then, mapping is performed so that the scan division point of the display screen matches the bank switching point of the VRAM, and N × (M−
m) a memory control device that performs reading and writing by mapping dots to a free area of the VRAM. 7. N × (M−
m) The bit arrangement of the dots is the
The upper Q / 2 bits indicated by the Y coordinate are set as the upper Q / 2 bits of the converted X coordinate, the lower Q / 2 bits indicating the Y coordinate are set as the upper Q / 2 bits of the converted Y coordinate, and the X coordinate is indicated. 7. The image display system according to claim 6, wherein the higher-order Q / 2 bits are subjected to coordinate conversion as lower-order Q / 2 bits indicating a converted Y coordinate, and read / write is performed. 8. The coordinates (x, y) and (p, q) of a rectangular area, which are parameters before vertical and horizontal conversion, the width w and the height h of the transfer area
With the coordinates (X, Y) of the rectangular area, which are the parameters after the change,
To convert (P, Q) and the width W and height H of the transfer area, X
= Y, Y = M−x−w, W = h, H = w, P = q, Q =
The image display system according to claim 7, further comprising a calculation device that calculates Mpw.