JPH1138086A - Semiconductor test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate high-precision differential signals by receiving a signal from a pattern generator, wave-form-shaping it and converting it into positive and negative differential signals with a frame processor, and driving tester pins connected to a differential input end via a delay means uniformly adjusting the phase timing. SOLUTION: The pattern signal of the channel 1 from a pattern generator is waveform-shaped and outputted by the FP1 of a frame processor, and the wave-form-shaped signal is received by a differential buffer 11 and is converted into positive and negative differential signals and outputted. Delay means 21, 22 are made of a fixed delay element or a semifixed delay element, receive the positive and negative differential signals outputted from the buffer 11, and adjust the phase timings of the positive and negative differential signals at the differential input end of a DUT to the same phase in advance. Tester pin drivers DR1, DR2 receive both positive and negative differential signals phase- corrected by the delay means 21, 22, voltage-convert them, and feed the in-phase signals. The fluctuation trouble of a clock edge is resolved, and high-precision signals can be generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-precision differential signal generator for a device under test having a differential input terminal in a semiconductor test apparatus.

[0002]

2. Description of the Related Art A prior art example will be described below with reference to FIG. 5 showing a main part configuration diagram relating to the generation of a highly accurate differential signal and FIG. 6 showing an example of a differential signal output timing diagram. As shown in FIG. 5, a configuration example for driving the pins of the DUT includes a pattern generator, a frame processor, a driver for a tester pin, and a device under test (DUT). Here, it is assumed that the DUT has a differential, for example, a clock input terminal, is an IC in which an internal circuit operates in synchronization with the clock, and that this clock requires high precision.

The pattern generator generates a test pattern such as a driver pattern applied to a pin of a DUT or an expected value pattern for a comparator, and supplies the test pattern to a frame processor. The frame processor has n channels of FP1 to FPn. Each of FP1 to FPn is a TG of a conventional semiconductor test device.
(Timing Generator) and FC (Format Control), which are used to shape and output a test waveform with a predetermined predetermined time-phase relationship using a reference clock. Among them, two channels, FP1 and FP2,
This is used to drive the differential clock input terminal CLK and the inverted CLK of the DUT. Tester pin driver DR1
DRn receive the shaping pattern signal from the frame processor, convert it to a test voltage having a predetermined amplitude, and
To each of the tester pins 1 to n. In order to supply a high-precision differential clock to the DUT, DR1 and DR2 use special ultra-high-speed devices such as gallium arsenide.

[0004]

By the way, the differential clock input terminal CLK of the DUT and the inverted CLK
However, this conventional configuration has the following practical difficulties. That is, first, the signals output from the pins 1 and 2 are output from the individual FP1 and FP2, so that there is a time lag between the two signals. Second, FP1, FP
2 is an individual circuit, each of which has a minute jitter of different characteristics. Due to these factors, pin 1 in FIG.
6B and the timing of the pin 2 in FIG. 6B, the cross point between the two signals deviates from the original position of 50% of the amplitude to cause a timing shift. As a result, the operation clock inside the DUT becomes a clock edge shifted from a predetermined timing position as shown in the output waveform of FIG. 6C. In particular, FIG.
In the jitter width of the output clock shown in FIG. 7, both jitters of FP1 and FP2 are added, resulting in a larger jitter width fluctuation. Along with this, there is a problem that the fluctuation of the duty ratio of the clock becomes large. As described above, in the conventional configuration, since there is a factor that deteriorates the timing accuracy of the differential signal, it is not preferable for a semiconductor test apparatus requiring high accuracy, and has a practical problem.

Accordingly, an object of the present invention is to provide a semiconductor test device capable of generating a more accurate differential signal in the generation of a differential signal requiring high-precision timing to be applied to a device under test. It is to provide a device.

[0006]

FIG. 1 shows a solution according to the present invention. First, in order to solve the above-mentioned problem, in the configuration of the present invention, in a semiconductor test apparatus that generates a highly accurate differential timing signal applied to a differential input terminal of a device under test, FP of frame processor receiving pattern signal of 1 channel
1 is a differential buffer 1 which receives a waveform-shaped signal which is shaped and output in a predetermined manner, converts the signal into a positive / negative differential signal, and outputs the signal.
Delay means 21 for receiving the positive and negative differential signals output from the differential buffer 11 and adjusting the phase timing of the positive and negative differential signals at the differential input terminal of the DUT to the same.
2 which are inserted in series and receive the positive and negative differential signals delayed by the delay means 21 and 22 to respectively drive the tester pins 1 and 2 connected to the differential input terminals of the DUT.
This is a configuration means including R1 and DR2. From the above,
In generating a differential signal requiring high-precision timing to be applied to a device under test, a semiconductor test apparatus capable of generating a higher-precision differential signal can be realized.

FIG. 2 shows a solution according to the present invention. Second, in order to solve the above-mentioned problem, in the configuration of the present invention, in a semiconductor test apparatus that generates a highly accurate differential timing signal applied to a differential input terminal of a device under test, The FP1 of the frame processor receives a one-channel pattern signal, receives a waveform-shaped signal output from the FP1, and converts the signal into a positive / negative differential signal. Upon receiving the positive and negative differential signals output from the buffer 11, the DU
There is a configuration unit including drivers DR1 and DR2 for driving the tester pins 1 and 2 connected to the differential input terminal of T, respectively.

FIG. 3 shows a solution according to the present invention. Third, in order to solve the above problem, in the configuration of the present invention, a semiconductor test apparatus that generates a highly accurate differential timing signal to be applied to a differential input terminal of a device under test is provided. Upon receiving a pattern signal of one channel, the FP1 of the frame processor performs a predetermined waveform shaping and receives a waveform shaping signal, and outputs one of the DUTs.
There is a configuration unit that includes a driver DR1 that buffers the pin 1 of the DUT as a positive differential signal and an inverting driver DR2 that inverts the pin 2 of the other DUT as a negative differential signal.

There is also a means for providing a plurality of systems for generating the above-mentioned differential timing signals.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings together with embodiments.

An embodiment of the present invention will be described below with reference to FIG. 1 showing a main part configuration diagram relating to the generation of a differential signal with high precision and FIG. 4 showing an example of an output timing diagram of the differential signal. The present invention is a method of generating a differential signal by splitting into two using one channel.

As shown in FIG. 1, the configuration is such that a differential buffer 11 and delay means 21 and 22 are provided for a conventional one-channel signal path. Elements corresponding to the conventional configuration are denoted by the same reference numerals.

The differential buffer 11 receives a waveform shaping signal which is obtained by shaping a 1-channel pattern signal from the pattern generator into a predetermined waveform by the frame processor FP1 and outputs the signal. It is converted into a motion signal and output. As a result, there is no jitter width associated with the differential signal as in the output clock of FIG. 4C. Since this is a circuit system in which the jitter of the same phase is branched, the jitter of both the differential signals is not added unlike the related art. As a result, there is obtained an advantage that the jitter of the output clock in FIG.

The delay means 21 and 22 are fixed delay elements or semi-fixed delay elements, receive the positive and negative differential signals output from the differential buffer 11, and receive the positive and negative differential signals at the differential input terminals of the DUT. The phase timing is adjusted in advance so as to have the same phase. As a result, as shown in the time difference between FIGS. 4A and 4B, the phase is always the same without being affected by the jitter of the FP1 of the frame processor.
The cross point is a stable 50% amplitude point. This has the advantage of making the output clock edge of FIG. 4C in the DUT more stable.

The tester pin drivers DR1 and DR
2 receives the positive and negative differential signals phase-corrected by the delay means 21 and 22 and converts the signals into test voltages having a predetermined amplitude to supply differential signals having the same phase to the differential input terminals of the DUT.

According to the above-described invention, a one-channel pattern signal is received from the pattern generator, the FP1 of the frame processor performs predetermined waveform shaping, and receives a waveform shaping signal which is output. With the configuration including the means for outputting differential signals of the same phase by converting the clock signal into a clock signal, it is possible to eliminate the problem of clock edge fluctuation caused by the use of the two-channel pattern signal as in the related art. The advantage that a differential signal can be generated is obtained.

In the description of the above embodiment, the delay means 2
Although the description has been given of the specific configuration example in which the delay means 21 and 22 are provided, if the difference between the two propagation delays of the tester pin drivers DR1 and DR2 is small, as shown in FIG. It is good also as composition which did.

In the configuration shown in FIG. 2, the differential buffer 1
Although an example of a configuration for generating positive and negative differential signals by 1 has been described,
If desired, as shown in FIG. 3, the configuration may be such that the differential buffer 11 is deleted and the driver DR2 of the tester pin is replaced with an inversion type driver.

In the description of the above-described embodiment, a specific example in which the high-precision differential signal supplied to the DUT is provided in one system has been described. A system may be provided.

[0020]

According to the present invention, the following effects can be obtained from the above description. According to the configuration of the invention described above, the one-channel pattern signal from the pattern generator is received, the waveform is shaped by the FP1 of the frame processor, and the waveform shaped signal is output and converted to a positive / negative differential signal. And a means for supplying a signal to the differential input terminal of the DUT, it is possible to eliminate the fluctuation of the clock edge due to the jitter of the two-channel pattern signal as in the prior art. The advantage that a signal can be generated is obtained.

[Brief description of the drawings]

FIG. 1 is a main part configuration diagram relating to generation of a highly accurate differential signal of the present invention.

FIG. 2 is a configuration diagram of another main part related to the generation of a highly accurate differential signal according to the present invention.

FIG. 3 is a configuration diagram of another main part according to the present invention relating to the generation of high-precision differential signals.

FIG. 4 is an output timing example of a differential signal according to the present invention.

FIG. 5 is a main part configuration diagram related to the generation of a high-precision differential signal.

FIG. 6 is an example of a conventional output timing of a differential signal.

[Explanation of symbols]

 DR1 to DRn Tester pin driver FP1 to FPn Frame processor 11 Differential buffer 21, 22 Delay means

Claims (3)

[Claims] 1. A semiconductor test apparatus for generating a high-precision differential timing signal to be applied to a differential input terminal of a device under test (DUT). A differential buffer that receives a waveform-shaped signal that is shaped and output, converts it into a positive / negative differential signal, and outputs the signal.
A delay means for making the phase timings of the positive and negative differential signals at the differential input terminal of the UT the same is provided by inserting in series.
A semiconductor test apparatus comprising: a driver for driving a tester pin connected to a differential input terminal of a UT; 2. A semiconductor test apparatus for generating a highly accurate differential timing signal to be applied to a differential input terminal of a device under test, receiving a one-channel pattern signal from a pattern generator and shaping the waveform in a predetermined manner. A differential buffer that receives the waveform shaping signal output and converts it into a positive and negative differential signal, and outputs the positive and negative differential signal output by the differential buffer.
A semiconductor test apparatus comprising: a driver for driving a tester pin connected to a differential input terminal of a UT; 3. A semiconductor test apparatus for generating a high-precision differential timing signal to be applied to a differential input terminal of a device under test, receiving a one-channel pattern signal from a pattern generator and shaping the waveform in a predetermined manner. A driver that receives a waveform shaping signal output as a buffer and drives a pin of one DUT in a buffer, and an inverting driver that inverts and drives a pin of the other DUT. Testing equipment.