JPH11355354A - Memory controller and data receiver using it - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the processing efficiency of packet data and to facilitate restoration of the memory controller on the occurrence of an error. SOLUTION: Received data in an IP packet form are transferred to a computer 103 from a reception port and the computer 103 stores temporarily the data to a buffer memory 143 via a driver 142. The driver 142 controls the memory 143 that is separated into pluralities of sectors whose size is more than a maximum IP packet size. The driver 142 updates a write pointer and a read pointer to/from the memory 143 in the unit of sector sizes attended with write/read of IP packets. The quantity of data required for pointer control and calculation of a buffer occupancy amount or the like is reduced by selecting the sector size to be a good place to leave off even when the packet size is a fragment and the processing efficiency is improved. Even on the occurrence of an error where a data size described in a header of an IP packet differs from an actual transmission size, the error does not propagate to succeeding packets from the write side.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory control device for controlling writing and reading of packet data to and from a buffer memory and a data receiving device using the same. Specifically, by dividing the buffer memory into a plurality of sectors having a sector size equal to or larger than the maximum value of the packet size, and updating the write pointer and the read pointer in units of the sector size with writing and reading of the packet data, The present invention relates to a memory control device and the like which can efficiently process packet data and can easily recover from an error.

[0002]

2. Description of the Related Art Hitherto, it has been proposed to transfer data such as programs and files received by a receiver to a personal computer for use. In this case, a bus in the computer, for example, a PCI (Peripheral Component I
A reception board is connected to the nterconnect) bus, and the above-described reception data is supplied to the PCI bus through the reception board. Here, the received data is, for example, IP (Internet
Protocol) The packet is transferred from the receiving board to the computer in the form of a packet and temporarily stored in a buffer memory in the computer.

[0003]

In the conventional control of the buffer memory 200, packet data is packed and written into the buffer memory 200 as shown in FIG. I have.

[0004] In this case, since the packet size is not always a good size to be divided, many bits are required for controlling the write pointer and the read pointer for the buffer memory 200 and calculating the buffer occupancy, and the like. The scale of hardware and software became large, and packet data processing could not be performed efficiently.

When an error occurs in packet data, the error propagates to other packet data,
Error recovery was not easy. For example, when the data size written in the header of the packet data is smaller than the size of the actually transferred data, as shown in FIG. 10, the processing of the next packet data starts from the beginning of the next correct packet data. And the error propagates to other packet data, making it difficult to recover from the error.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a memory control device and the like that can efficiently process packet data and can easily recover from an error.

[0007]

A memory control device according to the present invention includes a buffer memory, and a memory control unit that controls writing and reading of packet data to and from the buffer memory. Divided into a plurality of sectors having a sector size equal to or greater than the maximum packet size, and the memory control unit updates the write pointer and the read pointer to the buffer memory in units of the sector size as the packet data is written and read. It is.

In the present invention, the buffer memory is divided into a plurality of sectors having a sector size equal to or larger than the maximum value of the packet size relating to the packet data, and packet data is written and read in units of the sector size.

If the sector size is set to a good size for division, even if the packet size is an odd value, the data amount (bit) required for controlling the write pointer and the read pointer, calculating the buffer occupancy, etc. Number) is small. Therefore, the scale of hardware and software can be small, and packet data processing can be performed efficiently.

[0010] The write pointer and the read pointer for the buffer memory are updated in units of the sector size as the packet data is written and read. Therefore, even if an error occurs in which the data size written in the header of the packet data differs from the actual transmission size, the error does not propagate to the next data packet on the writing side. In addition, since a data packet exceeding the sector size cannot exist on the reading side, it is easy to detect the error packet and the next correct data packet.

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a digital broadcast receiving system 100 as an embodiment. The receiving system 100 includes, for example, an antenna 101 for receiving a digital broadcast signal from a broadcast satellite (not shown),
The digital broadcast signal received by the antenna 101 is subjected to reception processing, and a video signal SV of a desired channel is output.
And a receiver 102 for obtaining an audio signal SA, a computer (for example, a personal computer) 103,
MPEG2 (Moving Picture Experts Group 2) corresponding to a broadcast signal of a predetermined RF channel from the receiver 102
Computer 1 from transport stream TS
The receiving board 104 extracts data (program data, file data) according to the receiving instruction from the computer 03 and transfers the data to the computer 103. The receiving board 104 is connected to a bus in the computer 103, for example, a PCI bus 105.

The receiver 102 includes a microcomputer, and includes a controller 111 for controlling the entire operation and a plurality of RF signals received by the antenna 101.
And a tuner 113 for selecting a broadcast signal of a predetermined RF channel from the digital broadcast signals of the channel and outputting digital modulation data corresponding to the broadcast signal of the predetermined RF channel. The tuning operation of the tuner 113 is controlled by the controller 111 based on the operation of the key operation unit 112 by the user.

The receiver 102 is a demodulator 114 for demodulating digital modulated data output from the tuner 113 and an ECC (Error Correction) for performing error correction on the output data of the demodulator 114. C
ode) A decoder 115 and a descrambling process for the output data of the decoder 115 are performed so that the MPEG data corresponding to the selected predetermined RF channel broadcast signal is output.
Descrambler 1 for obtaining two transport streams (data obtained by time-division multiplexing of fixed-length packets such as video data, audio data, and service data) TS
16.

[0015] The receiver 102 includes a descrambler 1.
The video data stream and the audio data packet of the program number (channel) designated by the user's operation of the key operation unit 112 are separated from the transport stream TS output from the video stream TS, and the video data stream composed of those packets is separated. Demultiplexer 11 for outputting VDS and audio data stream ADS
And a video processing unit 1 for performing a data decompression process or the like on the video data stream VDS to obtain a video signal SV.
18 and an output terminal 119 for outputting the video signal SV.
And an audio processing unit 120 that obtains an audio signal SA by performing data decompression processing or the like on the audio data stream ADS, and an output terminal 121 that outputs the audio signal SA.

Next, the operation of the receiver 102 shown in FIG. 1 will be described. Digital television broadcast signals of a plurality of RF channels received by the antenna 101 are supplied to the tuner 113, a broadcast signal of a predetermined RF channel is selected, and digital modulated data corresponding to the broadcast signal is output from the tuner 113. The demodulator 114 performs demodulation processing on the digital modulation data output from the tuner 113, and performs error correction processing on the output data of the demodulator 114 with the ECC decoder 115. The descrambling process is performed on the output data by the descrambler 116 to obtain the MPEG2 transport stream TS corresponding to the above-described broadcast signal of the predetermined RF channel.

This transport stream TS is supplied to a demultiplexer 117, where video data and audio data packets of a program number (channel) designated by a user operation are separated, and a video data stream composed of those packets is separated. VDS and audio data stream ADS are obtained. Then, the video processing section 11 performs processing on the video data stream VDS.
In step 8, a process such as data expansion is performed to generate a video signal SV, and the video signal SV is output to the output terminal 119. Further, the audio data stream ADS is subjected to a process such as data decompression by the audio processing unit 120 to generate an audio signal SA, and the audio signal SA is output to the output terminal 121.

FIG. 2 shows the configuration of the receiving board 104.

The receiving board 104 has a CPU (central processing unit) as a controller for controlling the entire operation.
nit) 131 and a connector 132 to which the MPEG2 transport stream TS from the receiver 102 is supplied.
And a demultiplexer 133 for separating a data packet of a program number (channel) in accordance with a reception instruction from the computer 103 from the transport stream TS and outputting a data stream DS composed of the packets. RAM 1 as a buffer memory for temporarily storing stream DS
34.

The receiving board 104 extracts, from the data stream DS output from the demultiplexer 133, program data (data such as programs and files) DT according to the receiving command from the computer 103, and extracts the data DT. A filtering circuit 135 that converts DT into an IP packet and outputs the IP packet;
A connector 136 for connecting to the CI bus 105;
A bus control unit 137 for interfacing with the CI bus 105; and a working RAM (random access memory)
138.

FIG. 3 shows a main configuration of the computer 103. The computer 103 includes a PCI bus 105
And a connector 141 for connecting the receiving board 104 and a driver 1 connected to the PCI bus 105.
42, the buffer memory 143, and the application 1
44. The application 144 is software that runs on the computer 103, has a user interface, and can be directly operated by a user.

Next, the driver 142 is sent from the application 144 of the computer 103 by the operation of the user.
Will be described in the case where a receiving instruction RCM for data of a predetermined program (data of a program, a file, or the like) is supplied to the CPU.

In this case, the reception command RCM is
From 42, the signal is supplied to the CPU 131 of the receiving board 104 via the PCI bus 105, the connector 141, the connector 136 of the receiving board 104, and the bus control unit 137. Then, the separation operation of the demultiplexer 133 is controlled by the CPU 131 so as to separate the packet of the program number (channel) according to the reception command RCM.

Here, the packet separation operation in the demultiplexer 133 is performed by a PID (Packet Ide) included in a header (TS header) arranged at the head of the TS packet.
ntication: packet identification information).
For example, when the transport stream TS as shown in FIG. 4A is supplied to the demultiplexer 133 and the PID of the packet to be separated by the reception command RCM is PID # 1, the demultiplexer 133
3, only the packets with PID = PID # 1 are separated, so that a data stream DS relating to the separated packets is obtained as shown in FIG. 4B.

The data stream DS obtained by the demultiplexer 133 is temporarily stored in a RAM 134 as a buffer memory. And this RAM 134
The read data stream DS is supplied to the filtering circuit 135 via the demultiplexer 133. The filtering circuit 135 is controlled by the CPU 131 so as to extract program data (data of programs, files, etc.) DT in accordance with the reception command RCM.

Here, the extraction operation is performed using a program ID added for identifying a program.
For example, when the data stream DS as shown in FIG. 4B is supplied to the filtering circuit 135 and the program to be extracted by the reception command RCM is the program A, the filtering circuit 135 extracts only the program A. Therefore, as shown in FIG.
T is obtained.

The filtering circuit 135 further includes:
The data DT according to the reception command RCM extracted as described above is converted into an IP packet as shown in FIG. 4D. The data DT extracted by the filtering circuit 135 is transmitted in the form of an IP packet to the bus control unit 13.
7, connector 136, connector 1 of computer 103
41, the computer 103 via the PCI bus 105
And temporarily stored in the buffer memory 143.

The data DT read from the buffer memory 143 is supplied to the application 144 via the driver 142.
In step 4, programs and files are reconfigured. here,
The data DT is transmitted from the driver 142 to the application 14
In the process of being supplied to the IP packet 4, although not shown, a UDP (User Datagram Protocol) packet (FIG.
E) and further from this UDP packet to the application layer (FIG. 4F). The application 144 includes data DT in the form of an application layer.
Is supplied, and the programs and files are reconfigured as shown in FIG. 4G.

Next, the bus controller 13 of the receiving board 104
7 will be described. FIG. 5 shows a main configuration of the bus control unit 137.

The bus control section 137 converts the data DT supplied from the filtering circuit 135 (see FIG. 2) into a PCI
FIFO (first-in first) to supply to the bus 105
-out) It has a PCI controller 150 including a memory 151 and a control register 152 for holding data relating to the operation of the FIFO memory 151. The control register 152 stores the PCI bus 10 from the FIFO memory 151.
5 that controls the on / off of data transfer to
Threshold data indicating how much data should be stored in the O memory 151 before outputting the data, the FIFO memory 1
Address data in the buffer memory 143 (see FIG. 3) of the computer 103 to which the data output from the data transfer unit 51 is transferred, data indicating the operation status of the FIFO memory 151, and the like.

The bus control unit 137 should store the control register 152 in the access path 153 including a data line and a control line for accessing the control register 152 from the PCI bus 105 via the PCI controller, and the control register 152. A control data generator 154 for generating data, and an access path 155 including a data line and a control line for accessing the control register 152 from the control data generator 154 are provided.

The bus control unit 137 includes a switch circuit 156 for switching the access path 153 and the access path 155, and a select register 157 for holding data for controlling the operation of the switch circuit 156.
And The access path 153 and the access path 155 described above correspond to a
The movable terminal of the switch circuit 156 is connected to the control register 152.
The data setting for the select register 157 is P
This is performed via the PCI controller 150 from the CI bus 105 side.

In the bus control section 137 as shown in FIG. 5, among the accesses to the control register 152, infrequent accesses are performed from the PCI bus 105 side. For example, when the power of the computer 103 is turned on,
The data of the select register 157 is set from the PCI bus 105 so that the switch circuit 156 is connected to the a side. As a result, the switch circuit 156 is connected to the a side, and the control register 152 is connected from the PCI bus 105 side.
Can be accessed. Then, in this state, the control register 152 is accessed from the PCI bus 105 side, and the on / off data for data transfer is set to the on state, and the threshold data is also set.

Of the accesses to the control register 152, the most frequent access is to the external hardware side.
That is, the control is performed from the control data generator 154. For example,
As described above, the control register 1 is sent from the PCI bus 105 side.
After the ON / OFF data of 52 is set to the ON state, the data of the select register 157 is set from the PCI bus 105 so that the switch circuit 156 is connected to the b side. As a result, the switching circuit 156
, So that the control register 152 can access the control register 152.

In this case, the address data DA of the transfer destination is sent from the filtering circuit 135 to the control data generator 154.
Each time D is supplied, the address data DAD of the transfer destination is set in the control register 152 by the access of the control data generator 154. Although not described above, the control register 152 also stores data that is set to “0” every time transfer of data of a certain size ends. Therefore, this data is also set to “1” by the access of the control data generator 154 each time the transfer destination address data DAD is set in the control register 152 as described above.

Next, in the computer 103, the driver 1
The control of the buffer memory 143 secured by 42 will be described.

In this embodiment, the buffer memory 1
43 is controlled by being divided into a plurality of sectors as shown in FIG. As described above, the IP packets relating to the data DT transferred from the filtering circuit 135 of the receiving board 104 via the bus control unit 137 are sequentially written to the respective sectors of the buffer memory 143, and thereafter read. Even if not described above, the FI
The FO memory 151 outputs each IP packet related to the data DT with the address data of the transfer destination added thereto. The transfer destination address data is stored in the computer 10
3 indicates the sector address of the buffer memory 143.

The size of the sector is equal to or larger than the maximum value of the packet size of the IP packet. In FIG. 6, a hatched portion of each sector indicates an area in which an IP packet has been written, and the remaining blank area indicates an empty area. Driver 14 for receiving board 104 and computer 103
No. 2 updates the write pointer WPT and the read pointer RPT not in the actual packet size of the IP packet but in units of the sector size. If the sector size is set to a well-divided size such as 1 kbytes, the amount of data (number of bits) handled by pointer control and calculation of buffer occupancy is small even if the packet size is an odd value. And the size of hardware and software is small.

The receiving board 104 is connected to the computer 10
The writing to the buffer memory 143 is controlled so that the third buffer memory 143 does not overflow. That is, the reception board 104 stops the transfer of the IP packet as the data DT when the value of the write pointer WPT is one sector before the value of the read pointer RPT, as shown in FIG. 7B. This state is buffer memory 1
43 is a full state, and conversely, as shown in FIG.
When the value of the read pointer is equal to the value of the write pointer, the buffer is empty. Thus, when the buffer memory 143 is in the full state, the receiving board 1
04, the transfer of the IP packet to the buffer memory 143 is stopped, but the receiving board 104 is connected to the RAM 134 by the demultiplexer 133,
There is no problem because the AM 134 functions as a buffer memory.

Thus, when the driver 142 detects the presence or absence of data, it is possible to clearly determine whether the buffer memory 143 is full or empty. Note that when the receiving board 104 performs control to set a full state when the value of the write pointer WPT in the buffer memory 143 matches the value of the read pointer RPT, the driver 1
At 42, it cannot be easily determined whether the state is a full state or an empty state.

As described above, in the present embodiment, by connecting the switch circuit 156 to the a side,
The control register 152 of the PCI controller 150 can be accessed from the CI bus 105 side. Therefore, for example, at the time of debugging or occurrence of an error, the switch circuit 156 is connected to the a side so that the control register 152 can be accessed from the PCI bus 105 side.
By accessing the control register 152 from the CI bus 105 side, the situation can be grasped and the setting can be changed, and processing at the time of debugging or occurrence of an error can be easily performed.

Further, the buffer memory 143 of the computer 103 is divided into a plurality of sectors having a sector size equal to or larger than the maximum packet size of the IP packet, and the IP packet related to the data DT is written to and read from each sector. The write pointer WPT and the read pointer RPT are updated in units of a sector size.

For this reason, if the sector size is set to a good size for division, even if the packet size is an odd value, it is necessary for controlling the write pointer WPT and the read pointer RPT, calculating the buffer occupancy, and the like. The amount of data (the number of bits) is reduced, the scale of hardware and software can be reduced, and packet data processing can be performed efficiently.

Even if an error occurs in which the data size of the header of the IP packet is different from the actual transmission size, as long as the error is updated in units of the sector size,
The error does not propagate to the next packet on the writing side. Since the reading side cannot have a packet exceeding the sector size, the error packet can be easily detected and the next correct packet can be easily detected.

For example, in FIG. 8A, an IP packet is written in sector 1 and an IP packet to be written in the next sector is written.
This shows a state where the packet is an error packet and the error packet has been written over sectors 2 and 3. In this case, the IP packet to be written to the next sector is written from the beginning of the sector 3 as shown in FIG. Therefore, the error does not propagate to the next packet on the writing side.

In the above embodiment, the present invention is applied to the digital broadcast receiving system 100. The present invention has a buffer memory, and writes and reads packet data to and from this buffer memory. It is needless to say that the present invention can be similarly applied to the case where

[0047]

According to the present invention, the buffer memory is divided into a plurality of sectors having a sector size equal to or larger than the maximum value of the packet size, and the write pointer and the read pointer are changed in accordance with the writing and reading of the packet data. Is updated in units of.

Therefore, if the sector size is set to a size that is easy to separate, even if the packet size is an odd value, the data amount required for controlling the write pointer and the read pointer, calculating the buffer occupancy, etc. (The number of bits) can be reduced, thereby reducing the scale of hardware and software, and enabling efficient processing of packet data.

Further, for example, even if an error occurs in which the data size written in the header of the data packet differs from the actual transmission size, the error does not propagate to the next data packet on the writing side. Also,
Since no data packet exceeding the sector size can exist on the reading side, it is easy to detect the error packet and the next correct data packet.
Therefore, there is an effect that recovery from an error can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving system as an embodiment.

FIG. 2 is a block diagram illustrating a configuration of a receiving board included in the digital broadcast receiving system.

FIG. 3 is a block diagram showing a main configuration of a computer constituting the digital broadcast receiving system.

FIG. 4 is a diagram for explaining an operation of a receiving board and the like when a receiving command is issued from a computer.

FIG. 5 is a block diagram illustrating a main configuration of a bus control unit included in the receiving board.

FIG. 6 is a diagram for explaining control of a buffer memory;

FIG. 7 is a diagram illustrating an empty state and a full state of the buffer memory.

FIG. 8 is a diagram for explaining the operation of the buffer memory when an error occurs.

FIG. 9 is a diagram for explaining control of a conventional buffer memory.

FIG. 10 is a diagram for explaining conventional processing at the time of an error.

[Description of Signs] 100 ... Digital broadcast receiving system, 101 ...
・ Antenna, 102 ・ ・ ・ Receiver, 103 ・ ・ ・ Computer, 104 ・ ・ ・ Receiving Board, 105 ・ ・ ・ PCI
Bus, 111 ... System controller, 113 ...
・ Tuner, 114 ・ ・ ・ Demodulator, 115 ・ ・ ・ ECC
Decoder, 116, 133 ... descrambler, 11
7 ... demultiplexer, 118 ... video processing unit, 119, 121 ... output terminal, 120 ... audio processing unit, 131 ... CPU, 132, 136
141 ... connector, 134 ... RAM as buffer memory, 135 ... filtering circuit, 13
7 Bus control unit, 138 Work RAM, 1
42 ... driver, 143 ... buffer memory, 1
44 ・ ・ ・ Application

Claims (5)

[Claims] 1. A buffer memory, comprising: a memory control unit that controls writing and reading of packet data to and from the buffer memory, wherein the buffer memory has a sector size equal to or greater than a maximum value of a packet size of the packet data. The memory control unit is divided into a plurality of sectors, and the memory control unit updates a write pointer and a read pointer for the buffer memory in units of the sector size in accordance with writing and reading of the packet data. . 2. The memory controller according to claim 1, wherein when the value of the write pointer is one sector before the value of the read pointer, the memory controller determines that the buffer memory is in a full state. 3. The memory control device according to 1. 3. The memory controller according to claim 1, wherein the memory control unit determines that the buffer memory is empty when the value of the write pointer is equal to the value of the read pointer. Memory controller. 4. A receiving unit for receiving data used by a computer, connected to a bus in the computer,
A data receiving apparatus comprising: a receiving board configured to transfer received data from the receiving unit to the computer; wherein the receiving board includes a first buffer memory that temporarily stores the received data; Data transfer means for converting the received data from the buffer memory into packet data and transferring the packet data to the computer, wherein the computer temporarily stores the packet data transferred from the receiving board And a memory control means for controlling writing and reading of the packet data to and from the second buffer memory, wherein the second buffer memory is equal to or larger than a maximum value of a packet size related to the packet data. The memory control unit is divided into a plurality of sectors having a sector size. A data pointer that updates a write pointer and a read pointer for the second buffer memory in units of the sector size in accordance with writing and reading of the data. 5. The data transfer means of the receiving board, when the value of the write pointer is one sector before the value of the read pointer, determines that the second buffer memory is full, The data receiving apparatus according to claim 4, wherein transfer of packet data to the computer is stopped.