JP2000228759A - Hd/sd compatible decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the capacity of a memory of a HD/SD compatible decoder. SOLUTION: A stream type identification circuit 12 identifies a packetized elementary stream PES from a demultiplexer 1 as to whether the stream is a high definition(HD) stream or a standard definition(SD) stream. A write address generating circuit 2 and a read address generating circuit 3 select the memory map of a buffering memory 4 on the basis of a stream identification signal. In this case, the SD and the HD use a common memory area and change the start address and end address of a read pointer and a write pointer in response to the revision of the memory map so as to avoid data outputted to a decoder selection circuit 5 from becoming discontinuous. Thus, the capacity of the memory can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an HDISO / IE
The present invention relates to an HD / SD compatible decoding device suitable for decoding a broadcast signal compressed according to the MPEG2 standard defined in C13818.

[0002]

2. Description of the Related Art In recent years, digital signal processing technology for video and audio has been remarkably advanced, and with the progress of digital broadcasting and integration of broadcasting and communication, systems have been actively developed around the world. It has become One of the most important digital signal processing techniques is a video and audio compression technique.

In the fields of broadcasting, communication and storage media, ISO / IEC 13818 (MPEG: Moving P
The compression method proposed by the Picture Coding Experts Group) has become established as a worldwide standard method.

[0004] The MPEG system specified by ISO / IEC13818 is a technique for encoding a video signal by using a combination of DCT conversion, inter-frame prediction coding, run-length coding, and entropy coding. On the decoding side, the original video signal is restored by inverse processing during encoding.

[0005] The generated code amount of the encoded data differs depending on the picture, and even the same picture differs depending on the picture type. Therefore, a VBV buffer (Video Buffering Verifier) is defined as a reception buffer of the virtual decoder model in order to absorb the burstiness of the generated code amount and decode each picture in real time.

[0006] The VBV buffer temporarily holds the MPEG stream and outputs it at the decode timing. The output timing of the data from the VBV buffer is determined according to the ISO / IE
Vbv delay (vbv dela) included in the header of the picture layer of the MPEG stream defined by C13818
y). The vbv delay indicates the time from when the start code of each picture layer is input to the VBV buffer until it is decoded.

[0007] The VBV buffer holds the input stream in the buffer until the start of decoding. In this case, the stream rate is determined so that the VBV buffer does not overflow or underflow.

[0008] The MPEG stream is multi-channel, and a one-channel stream is separated using a demultiplexer. In an actual decoder, a buffering memory is provided between the demultiplexer and the MPEG decoder.

In recent years, research on digital broadcasting has been conducted. In digital broadcasting, a high definition HD (High Definition) signal and a relatively low resolution SD (Standard Definition) signal can be mixed and transmitted. The television receiver can also receive these HD and SD signals while switching.

[0010] However, the necessary V when receiving the HD signal.
BV buffer capacity and VBV required for SD signal reception
Different from buffer capacity. For this reason, in order to prevent the display from becoming discontinuous when switching between the HD broadcast signal and the SD broadcast signal, it is necessary to secure separate memory areas for HD and SD.

FIG. 11 is an explanatory diagram showing a memory map of a VBV buffer used in a television receiver capable of receiving a 5-channel SD broadcast and a 1-channel HD broadcast. As shown in FIG. 11, the memory is provided with one independent HD buffer area and five independent SD buffer areas. Since independent memory areas are required for HD and SD applications, the required memory capacity of the television receiver is large.

[0012]

As described above, conventionally, H
When receiving a broadcast in which a D broadcast signal and an SD broadcast signal are mixed, it is necessary to provide independent memory areas for HD and SD as reception buffers, and there is a problem that the required memory capacity is large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to reduce the required memory capacity by enabling the use of HD and SD on a memory map. It is an object of the present invention to provide an HD / SD compatible decoding device capable of performing the above.

[0014]

An HD / SD according to the present invention
The corresponding decoding device receives a stream including a variable-length packet of a standard broadcast signal and a variable-length packet of a high-definition broadcast signal, buffers the stream, and decodes the stream from the memory means. Decoding means for outputting a decoded output;
A memory control unit for buffering a variable length packet of the standard broadcast signal and a variable length packet of the high definition broadcast signal using a common memory area of the memory unit.

In the present invention, the input stream is supplied to a memory means. The memory control means buffers the variable length packet of the standard broadcast signal and the variable length packet of the high definition broadcast signal using a common memory area of the memory means. The stream from the memory means is provided to the decoding means and decoded.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of an HD / SD compatible decoding apparatus according to the present invention.

The input terminal 20 has, for example, ISO / IEC1
An MPEG transport stream (Transport Stream) defined in 3818 is input. The transport stream can transmit a plurality of programs in one stream. The transport stream is
It is composed of a fixed-length packet (transport packet) of 188 bytes including a 1-byte synchronization signal, and includes video data, audio data, and other data.

This transport stream is supplied to the demultiplexer 1. The demultiplexer 1 extracts a desired program from the input transport stream, and further extracts a compressed video stream or audio stream. The stream from the demultiplexer 1 is, for example, a PES (Pecketized Elementary Stream Packet) defined in ISO / IEC 13818.
It is a stream.

In the TS system of the MPEG2 standard, a PES packet is divided and transmitted by a plurality of TS packets. A PES packet is obtained by adding header information to data of an encoding unit such as video or audio. For example, in the case of video data, one PES packet may be constituted by encoded data for one frame. Many.

The PES stream composed of such PES packets is supplied to the stream type identification circuit 12. When extracting the PES stream, the demultiplexer 1 generates a select signal indicating which program the extracted PES stream is for, and outputs the write address generation circuit 2 and the read address generation circuit 3 And a decoder selection circuit 5.

The stream type identification circuit 12 analyzes the header of an ES (Elementary stream) defined by ISO / IEC 13818 from the input PES stream, and identifies the stream as HD or SD. Generate a signal. This stream identification signal is supplied to the write address generation circuit 2, the read address generation circuit 3, and the decoder selection circuit 5.

The PES stream from the demultiplexer 1 is supplied to the buffering memory 4 via the stream type identification circuit 12. Buffering memory 4
Has a buffer area for SD and a buffer area for HD, writes the input PES stream at an address based on the write address from the write address generation circuit 2 and writes the PES stream from the read address generation circuit 3. The PES stream stored at the address based on the read address is read and output to the decoder selection circuit 5.

The write address generation circuit 2 and the read address generation circuit 3 calculate addresses to be given to the buffering memory 4. In the present embodiment, the write address generation circuit 2 and the read address generation circuit 3 perform address control so that the memory area of the buffering memory 4 is shared for SD and HD.

That is, a plurality of settings can be made in the buffering memory 4 as a memory map indicating sections of the SD buffer area and the HD buffer area, and the write address generation circuit 2 and the read address generation circuit 3 The setting of the memory map is switched based on a stream identification signal indicating whether the PES stream is HD or SD. When changing the setting of the memory map of the buffering memory 4, the write address generation circuit 2 and the read address generation circuit 3 change the start address and the end address of the read pointer and the write pointer.

Thus, even when the received stream is switched between HD and SD, the write address generation circuit 2 and read address generation circuit 3 can output a continuous stream between HD and SD. Has become.

The PES stream from the buffering memory 4 is supplied to a decoder selection circuit 5. The decoder selection circuit 5 determines which program the PES stream belongs to based on the select signal given from the demultiplexer 1, and determines the type of the PES stream.
It is determined whether the PES stream is HD or SD based on the stream identification signal given from the PC, and based on the determination result, the input PES stream is converted into one of the SD depacket expansion circuits 6 to 10 and the HD depacket expansion circuit 11. Crabs are selectively output.

Each of the SD depacket expansion circuits 6 to 10 expands an SD PES stream inputted for each program and outputs an SD video output. The HD depacket expansion circuit 11 expands the input HD PES stream and outputs an HD video output.

It is clear that the number of decoders is not limited to that shown in FIG.

Next, the operation of the embodiment configured as described above will be described with reference to FIGS. FIG. 2 shows an example of a memory map of the buffering memory 4 in FIG. FIG. 3 to FIG. 10 are for explaining the transition process of the memory map setting.

Now, as shown in FIG. 2, the buffering memory 4 has five areas (first to fifth SD buffer areas (first to fifth SD buffer areas) as buffer areas for SD necessary for buffering the PES stream of the SD of one program. It is assumed that the capacitor has a capacity to provide sd1 to sd5)).
Therefore, the buffering memory 4 can simultaneously buffer five SD programs. In addition, H necessary for buffering the HD PES stream
The D buffer area (hd) has the same capacity as the four SD buffer areas. In the present embodiment, sd1 to sd4 are also used as hd. Therefore, as shown in FIG.
PES stream of SD of program and PES of HD of one program
The stream and the stream can be buffered simultaneously.

The input terminal 20 receives a transport stream obtained by receiving a broadcast signal from a broadcast station. Broadcast signals include HD signals and SD signals. The transport stream is supplied to the demultiplexer 1, is separated for each program, is converted into a PES stream, and is supplied to the stream type identification circuit 12. The demultiplexer 1 outputs a select signal indicating which program the output PES stream belongs to to the write address generation circuit 2, the read address generation circuit 3, and the decoder selection circuit 5.

The stream type identification circuit 12 identifies whether the PES stream is HD or SD, and outputs a stream identification signal indicating the identification result to the write address generation circuit 2, the read address generation circuit 3, and the decoder selection. Output to the circuit 5. Stream type identification circuit 12
Is supplied to the buffering memory 4.

Now, assume that the broadcast signal is switched from SD broadcast to HD broadcast. FIGS. 3 and 4 show a method of controlling the read and write pointers of the address generation circuits 2 and 3 in this case. 3 and 4 show the setting of the memory map of the buffering memory 4. FIG. FIG. 3 shows an example in which the position of the read pointer R is closer to the sd1 end address than the write pointer W when switching from the SD broadcast to the HD broadcast. FIG. 4 shows an example in which the position of the write pointer W is closer to the sd1 end address than the read pointer R when switching from the SD broadcast to the HD broadcast.

When receiving an SD broadcast, the SD PES
The stream is stored in the 1SD buffer area of the buffering memory 4. For example, it is assumed that writing is performed in the first SD buffer area (sd1) indicated by the hatched portion in FIG. In this case, the write address generation circuit 2 sets the write start address of the write pointer W to sd.
1 and the end address is set to the end position of sd1.

The read address generation circuit 3 moves the read pointer R from the start address to the end address,
The written PES stream is buffered in memory 4
Are sequentially read from sd1.

P read from buffering memory 4
The ES stream is supplied to a decoder selection circuit 5, which recognizes the program by a select signal,
It is determined from the stream identification signal that the PES stream read is for SD broadcasting. In this case, the decoder selection circuit 5 selects one of the SD depacket expansion circuits 6 to 10 that expands the program of the input PES stream, and outputs the PES stream.
The SD depacket expansion circuit to which the PES stream is input decompresses the PES packet and then performs expansion processing.
Output SD video output.

Here, it is assumed that the reception is switched from the reception of the SD broadcast to the reception of the HD broadcast. Then, the write address generation circuit 2 and the read address generation circuit 3 change the setting of the memory map with sd1 to sd4 as hd, set the head position of the entire area of the buffering memory 4 to the hd start address, and end the sd4. Set position to hd end address. The write address generation circuit 2 and the read address generation circuit 3 provide the write pointer W and the read pointer R between the hd start address and the hd end address.
Is moved to perform writing and reading.

Now, as shown in FIG. 3A, the reception is switched from the reception of the SD broadcast to the reception of the HD broadcast at the timing when the read pointer R is located closer to the sd1 end address than the write pointer W. In this case, the SD PES stream is accumulated in sd1 of the buffering memory 4 in the area from the address indicated by the read pointer R to the end address and in the area from the start address to the address indicated by the write pointer W. ing.

The write pointer W is generated by the write address generation circuit 2 in the memory allocation of hd.
Moves to the end address in sequence, thereby
Following the S stream, an HD PES stream is stored. On the other hand, the read pointer R reaches the sd1 end address before the write pointer W, but the read address generation circuit 3 sets the read pointer from the sd1 end address to the sd1 end address in order to read the PES stream of SD.
Return to start address. When reading of all SD PES streams stored in the buffering memory 4 is completed (the state of FIG. 3B), the read address generation circuit 3 thereafter moves the read pointer to the hd end address sequentially, Read the HD PES stream.

In this manner, the PES streams of all the received SDs are output from the buffering memory 4 in the order of reception, and the received PES streams of the HD are sequentially output continuously from the start of reception.

The decoder selection circuit 5 receives a select signal indicating which program the PES stream belongs to and a stream identification signal indicating which stream of HD or SD. Accordingly, the decoder selection circuit 5 can reliably output all of the received SD PES stream to the corresponding SD depacket expansion circuit, and continuously from the head of the received HD PES stream. Can be output to

The SD depacket expansion circuit receives the input SD
Is depacketized and decompressed to output an SD video output. On the other hand, the HD depacket expansion circuit 11
Depackets and expands the input HD PES stream, and outputs an HD video output.

Thus, even when switching from SD broadcast to HD broadcast, it is possible to smoothly switch between SD video output and HD video output for output.

When switching from SD broadcast to HD broadcast, the write pointer W may be located closer to the sd1 end address than the read pointer R at the time of switching, as shown in FIG. In this case, P of SD
The ES stream is stored only in the area of the buffering memory 4 at the address indicated by the read pointer R and the write pointer W. Therefore, from the point of switching to the HD broadcast, the write address generation circuit 2 and the read address generation circuit 3 control the movement of the read pointer R and the write pointer W with the new memory allocation.

Other operations are the same as those in the example of FIG.

Next, a method of controlling the read and write pointers when switching from HD broadcast to SD broadcast will be described. 5 and 6 show address generation circuits 2 and 3 in this case.
The method of controlling the read and write pointers of FIG. FIG. 5 shows an example where the position of the write pointer W is closer to the hd end address than the read pointer R at the time of switching from HD broadcast to SD broadcast. FIG. 6 shows an example where the position of the read pointer R is closer to the hd end address than the write pointer W at the time of switching from HD broadcast to SD broadcast.

When receiving an HD broadcast, the HD PES
The stream is written into the HD buffer area (hd) of the buffering memory 4 (the hatched portion in FIG. 5A). In this case, the write address generation circuit 2 sets the write start address of the write pointer W to the head position of hd, and sets the end address to the end position of hd.

The read address generation circuit 3 moves the read pointer R from the hd start address to the hd end address, and sequentially reads the written PES stream from the hd of the buffering memory 4.

P read from buffering memory 4
The ES stream is supplied to a decoder selection circuit 5, which recognizes the program by a select signal,
It is determined from the stream identification signal that the read PES stream is for HD broadcasting. In this case, the decoder selection circuit 5 supplies the input PES stream to the HD depacket expansion circuit 11. The HD depacket decompression circuit 11 depackets the PES packet, decompresses the PES packet, and outputs an HD video output.

Here, it is assumed that the reception is switched from HD broadcast reception to SD broadcast reception. Then, the write address generation circuit 2 and the read address generation circuit 3 set hd to sd
The setting of the memory map is changed as 1 to sd4, the start position of sd1 in the buffering memory 4 is set to the sd1 start address, and the end position of sd1 is set to the sd1 end address. The write address generation circuit 2 and the read address generation circuit 3 perform writing and reading by moving the write pointer W and the read pointer R between the sd1 start address and the sd1 end address.

Now, as shown in FIG. 5A, the reception is switched from the HD broadcast to the SD broadcast at the timing when the write pointer W is located closer to the hd end address than the read pointer R. In this case, the HD PES stream is stored in the hd of the buffering memory 4 in the area from the address indicated by the read pointer R to the address indicated by the read pointer W.

The write pointer W is output by the write address generation circuit 2 in the hd memory allocation.
It sequentially moves to the end address and stores the PES stream of SD. On the other hand, the read pointer R is moved by the read address generation circuit 3 to the hd end address, and sequentially reads the HD PES stream and then the SD PES stream.

Thereafter, the write address generation circuit 2 and the read address generation circuit 3 move the write pointer W and the read pointer R between the sd1 start address and the sd1 end address, and read the HD PES stream.

In this way, all the received HD PES streams are output from the buffering memory 4 in the order of reception, and the received SD PES streams are sequentially output sequentially from the start of reception.

The decoder selection circuit 5 receives the P of the received HD.
HD depacket decompression circuit for all ES streams
11 and output to the corresponding SD depacket decompression circuit continuously from the beginning of the received SD PES stream.

The HD depacket expansion circuit 11 receives the input H
The PES stream of D is depacketized and expanded, and an HD video output is output. On the other hand, the SD depacket expansion circuit depackets and expands the input SD PES stream, and outputs an SD video output.

In this way, even when switching from HD broadcasting to SD broadcasting, it is possible to smoothly switch between HD video output and SD video output.

When switching from HD broadcasting to SD broadcasting, the read pointer R may be located closer to the hd end address than the write pointer W at the time of the switching, as shown in FIG. In this case, the HD PE
The S stream is stored in an area between the address indicated by the read pointer R and the hd end address and an area between the hd start address and the address indicated by the write pointer W in the buffering memory 4.
Therefore, after the switch to the SD broadcast, after the read pointer R moves to the hd end address, the write address generation circuit 2 and the read address generation circuit 3 control the movement of the read pointer R and the write pointer W with the new memory allocation. I do.

Further, one H from reception of a plurality of SD broadcasts
It is also possible to switch to reception of D broadcast. FIGS. 7 and 8 show a method of controlling the read and write pointers of the address generation circuits 2 and 3 in this case. 7 and 8 show the setting of the memory map of the buffering memory 4. FIG. FIG. 7 shows that when the SD broadcast is switched to the HD broadcast, the position of the read pointer R is sd1 more than the write pointer W.
An example of a case near the end address is shown. FIG. 8 shows S
An example is shown in which the position of the write pointer W is closer to the sd1 end address than the read pointer R when switching from the D broadcast to the HD broadcast.

In this case, the same operation as in FIGS. 3 and 4 is performed. That is, in the case of FIG.
Arrives at the sd1 end address before the write pointer W, but the continuous data of the PES stream of SD is the area between the address indicated by the read pointer R and the sd1 end address, and the sd1 start address and the write pointer W. Immediately after switching to the HD broadcast, the read pointer R is set to sd
After moving to the 1 end address, the process returns to the sd1 start address. Thereafter, the read and write pointers R and W move within the newly set memory allocation.

In the case of FIG. 8, the position of the write pointer R is changed to the read pointer W at the time of the broadcast switching.
Sd1 end address side. In this case, the read / write pointers R and W can be moved at the newly set memory allocation immediately after the start of the broadcast.

[0062] In addition, a plurality of S
It is also possible to switch to reception of D broadcast. FIGS. 9 and 10 show a method of controlling the read and write pointers of the address generation circuits 2 and 3 in this case. FIG. 9 shows an example where the position of the write pointer W is closer to the hd end address side than the read pointer R at the time of switching from HD broadcast to a plurality of SD broadcasts. FIG. 10 shows an example where the position of the read pointer R is closer to the hd end address than the write pointer W at the time of switching from the HD broadcast to a plurality of SD broadcasts.

In this case, the same operation as in FIGS. 5 and 6 is performed. sd1 is used as the main buffer of SD, and sd
The pointers for read / write 1 and hd are common. FIG.
In this case, the write pointer reaches the hd end address before the read pointer, and returns to the sd1 start address (FIG. 9A). Next, the read pointer R reaches the hd end address and returns to the sd1 start address (FIG. 9).
(B)). Thereafter, the read / write pointers R and W of sd1 are moved within the newly set memory allocation, and the buffering of sd2 is also started (FIG. 9).
(C)).

In the case of FIG. 10, the read pointer R reaches the hd end address before the write pointer W, and returns to the sd1 start address (FIG. 10B). Thereafter, sd1 in the newly set memory allocation
Then, the read / write pointers R and W are moved to start buffering sd2 (FIG. 10C).

As described above, in the present embodiment, a plurality of memory maps can be set in the buffering memory 4 so that when the SD broadcast and the HD broadcast are switched,
By changing the start address and end address of the read pointer and the write pointer and changing the setting of the memory map, a smooth display is enabled even at the time of switching between the SD broadcast and the HD broadcast.

[0066]

As described above, according to the present invention, H
It is possible to reduce the required memory capacity by enabling the D and SD memories to be used in a superimposed manner on the memory map.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of an HD / SD compatible decoding device according to the present invention.

FIG. 2 is an explanatory diagram for explaining operation of the embodiment;

FIG. 3 is an explanatory diagram for explaining operation of the embodiment;

FIG. 4 is an explanatory diagram for explaining operation of the embodiment;

FIG. 5 is an explanatory diagram for explaining operation of the embodiment;

FIG. 6 is an explanatory diagram for explaining operation of the embodiment;

FIG. 7 is an explanatory diagram for explaining operation of the embodiment;

FIG. 8 is an explanatory diagram for explaining operation of the embodiment;

FIG. 9 is an explanatory diagram illustrating an operation of the embodiment.

FIG. 10 is an explanatory diagram for explaining operation of the embodiment;

FIG. 11 is an explanatory diagram for explaining a memory map of a conventional example.

[Explanation of symbols]

1 demultiplexer, 2 write address generation circuit,
3: Read address generation circuit, 4: Buffering memory, 5: Decoder selection circuit, 6-10: SD depacket expansion circuit, 11: HD depacket expansion circuit, 12: Stream type identification circuit

Claims (4)

[Claims] 1. A stream including a variable length packet of a standard broadcast signal and a variable length packet of a high definition broadcast signal is input, a memory means for buffering and outputting the stream, and decoding a stream from the memory means. Decoding means for outputting a decode output, and memory control means for buffering a variable length packet of the standard broadcast signal and a variable length packet of the high definition broadcast signal using a common memory area of the memory means. An HD / SD compatible decoding device, comprising: 2. A stream including a variable-length packet of a standard broadcast signal and a variable-length packet of a high-definition broadcast signal is input, and a memory means for buffering and outputting the stream; and decoding a stream from the memory means Decoding means for outputting a decode output, and a memory map for a variable length packet of the standard broadcast signal and a memory map for a variable length packet of the high definition broadcast signal can be respectively set in a common area of the memory means, An HD / SD compatible decoder comprising: a read pointer for controlling writing and reading of the memory means in response to a change in setting of a memory map; and an address generating means for changing a start address and an end address of a write pointer. apparatus. 3. The read pointer and the read pointer according to claim 1, wherein, when switching from the reception of the standard broadcast signal to the reception of the high definition broadcast signal, the address output unit does not discontinue the decode output output to the decode unit. 3. The H according to claim 2, wherein the write pointer is controlled.
D / SD compatible decoding device. 4. The read pointer and the read pointer according to claim 1, wherein, when switching from the reception of the high-definition broadcast signal to the reception of the standard broadcast signal, the address generation means does not discontinue the decode output output to the decode means. 3. The H according to claim 2, wherein the write pointer is controlled.
D / SD compatible decoding device.