JP2000165816A - Signal decoding method and device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously decode a plurality of MPEG-coded bit streams while suppressing the increase in the scale and in the production cost. SOLUTION: A multi-coding data input terminal 81 receives a standard definition SD stream (or MP 'at' HL single high definition HD stream) that is subjected to time division multiplexing with MPEG-coded MP 'at' ML as an input stream 1. A control signal input terminal 82 receives a control signal 2 to distinguish the SD stream subjected to time division multiplexing. A coded data changeover device 3 branches the SD stream subjected to time division multiplexing depending on the control signal 2 and a video buffering verifier VBV memory 5 stores each of the branched SD streams independently. Each of the SD stream stored in the VBV memory 5 is read by a stream changeover device 7 and an expansion decoding means after a variable length decoder 8 applies expansion decoding to the stream.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called M
PEG (Moving Picture image coding Experts Group)
The present invention relates to a signal decoding method and apparatus for decoding a compressed image signal or the like compressed by encoding.

[0002]

2. Description of the Related Art FIG. 9 shows a schematic configuration example of a conventional MPEG image decoding device for decoding a compressed image which has been MPEG-encoded.

In FIG. 9, a bit stream of MPEG-encoded data input through an input terminal 99 is supplied to a buffer 100 and accumulated in a fixed amount. The buffer 100 is provided so that when the input MPEG encoded bit stream has a variable rate, constant data can be supplied to the variable length decoder 101 at the subsequent stage.

[0004] The variable length decoder 101 includes a buffer 100.
Is read out, and each data is decoded by a method specified in MPEG. That is,
The variable-length decoder 101 decodes coding information of a macroblock, which is a unit obtained by dividing an image into small sections, and decodes the coding mode, motion vector, quantization information, and quantization DC.
The T coefficient and the like are separated. The variable length decoder 1
The encoded information of the macroblock decoded in 01 is further divided into 8 × 8 small block blocks. This 8x8
Are restored to DCT coefficients by the inverse quantization process in the inverse quantizer 102, and the pixel data in the pixel space is further restored by the inverse DCT process in the inverse DCT device 103. Is converted to

[0005] The adder 104 adds the pixel data output from the inverse DCT unit 103 and the output of a motion compensation predictor 105 described later, which operates according to the motion compensation control data output from the variable length decoder 101, and finally adds the result. Video data.

[0006] The motion compensation predictor 105 according to the motion compensation control data output from the variable length decoder 101,
A signal obtained by subjecting predetermined pixel data stored in an image memory 106, which will be described later, to arithmetic processing, or a no signal is supplied to the adder 104.

The image memory 106 stores, in the video data output from the adder 104, an I
Image (Intra-Picture) and P image (Predictive-Pictur)
e) two frame images and a B image (bidirectionally
-Picture) is an image memory for holding one field image used when performing field conversion on a frame image in a macroblock when outputting (Picture).

The video data output from the image memory 106 is output from an output terminal 107 and sent to a motion compensation predictor 105.

[0009]

As described above, in the conventional MPEG image decoding apparatus, one MPEG encoded bit stream is generated for one apparatus. In order to simultaneously decode MPEG-encoded bit streams, a plurality of MPEG image decoding devices are required.

As described above, in response to a request to simultaneously decode a plurality of MPEG encoded bit streams,
Multiple MPEG image decoding devices are required, and as a result,
There is a problem that the processing scale of the MPEG image decoding apparatus increases in proportion to the number of the bit streams to be simultaneously decoded, thereby increasing the production cost.

Accordingly, the present invention has been made in view of such a situation, and a demand for simultaneously decoding a plurality of bit streams encoded by, for example, MPEG is made while suppressing an increase in scale and an increase in production cost. An object of the present invention is to provide a signal decoding method and apparatus which can be realized.

[0012]

According to the signal decoding method of the present invention, a bit stream obtained by time-division multiplexing a plurality of compression-encoded bit streams and a control signal for distinguishing the plurality of bit streams are provided. The above-described problem is obtained by inputting at least a bit stream, dividing the time-division multiplexed bit stream in accordance with the control signal, storing each bit stream, reading out the stored bit stream by switching to time division, and performing decompression decoding. Solve.

In the signal decoding method of the present invention, a time-division multiplexed bit stream and a single bit stream are switched and input, and when a time-division multiplexed bit stream is input, each divided The bit streams are stored independently, and when a single bit stream is input, each data obtained by dividing the single bit stream is stored.

Next, the signal decoding apparatus of the present invention distinguishes each of the plurality of bit streams from the first input means for inputting a bit stream in which a plurality of compression-encoded bit streams are time-division multiplexed. Input means for inputting a control signal for the control, a dividing means for dividing the time-division multiplexed bit stream according to the control signal, a storing means for storing the divided bit streams, and a storing means for storing the divided bit streams. The above-described problem is solved by having a reading unit that switches a bit stream to time division and reads the same, and a decompression decoding unit that decompresses and decodes the bit stream read in a time division manner.

In the signal decoding apparatus according to the present invention, the first input means switches and inputs a time-division multiplexed bit stream and a single bit stream, and the storage means secures a plurality of storage areas independently. When a time-division multiplexed bit stream is input, each divided bit stream is stored independently in each storage area, and when a single bit stream is input, the single bit stream is Is stored in each storage area.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a schematic configuration example of an MPEG image decoding apparatus as an embodiment to which the signal decoding method and apparatus of the present invention is applied.

The MPE according to the embodiment of the present invention shown in FIG.
The G image decoding apparatus includes a stream input unit, which is a first input unit capable of inputting a plurality of MPEG-encoded bit streams, and includes, for example, an SD (Standard Def.
MPitionML (Main Profil)
e at Main Level), when decoding an input stream obtained by time-division multiplexing a plurality of bit streams, a VB is set for each of the time-division multiplexed bit streams.
V (Video Buffering Verifier) buffer areas are allocated, the output of each VBV buffer area is switched in a time-division manner to perform MPEG decoding, and reference image data and display image data used in motion compensation prediction during the MPEG decoding are transmitted. By independently securing a frame memory area for storing the plurality of bit streams, it is possible to simultaneously decode a plurality of bit streams. In the following description, MP @ ML
A bit stream having a level of? Is set as an SD stream, and decoding of the time-division multiplexed SD stream by time division is referred to as multi-SD decoding.

The stream input unit of the MPEG image decoding apparatus according to the embodiment of the present invention includes not only the time-division multiplexed SD stream but also, for example, HD (High Definit
MP @ HL (Main Profile at ion) quality
High Level) and MP @ H-1440L (Main Profil
e at High-1440 Level), and a single bit stream can be input.
The PEG image decoding device uses the MP @ HL or MP @ H-1
It is also possible to decode a single bit stream of 440L. Note that in the following description, MP @ HL and MP
ビ ッ ト The bit stream of the level of H-1440L is defined as an HD stream, and decoding of the HD stream is defined as H
This is called D decoding.

Further, the MPEG image decoding apparatus according to the embodiment of the present invention can switch between the multi SD decoding and the HD decoding.

The basic operation of the MPEG image decoding apparatus according to the embodiment of the present invention will be described below.

In FIG. 1, for example, when multi SD decoding is performed, an input is provided to a multi-encoded data input terminal 81 which is the stream input section (first input means) of the MPEG image decoding apparatus of the present embodiment. The time-division multiplexed SD stream is input as stream 1,
The control signal input terminal 82 which is an input means of
A control signal 2 for switching and controlling the switch of the encoded data switch 3 at the subsequent stage is input.

Here, the input stream 1 when performing multi-SD decoding is a time-division multiplex of a plurality of (for example, n channels) MP @ ML bit streams (SD streams). When decoding, the data structure of the input stream 1 and the control signal 2 may be, for example, a data structure as shown in FIG. In the example of FIG. 2, the number of channels of the SD stream to be time-division multiplexed is set to three (SD streams S0, S1, S2). That is, the data structure of the input stream 1 when performing multi SD decoding is as shown in FIG.
, A data structure in which the SD stream of each channel indicated by S0, S1, S2, S0,... Is time-division multiplexed. As shown in FIG. 2B, the data structure of the control signal 2 when performing multi-SD decoding is an index number C0 for identifying the SD stream of each channel in FIG. , C1, C2, C3,...

On the other hand, when HD decoding is performed, the input stream 1 is a single bit stream (HD stream) of MP @ HL and MP @ H-1440L, and the control signal 2 is a fixed control signal and a fixed control signal. Become.

The coded data switch 3 is provided as dividing means according to the present invention, and includes a common terminal 30 to which the input stream 1 is supplied, a plurality of (for example, n) switched terminals 31 _{1 to} 31 _n . The connection between any _{one of the} plurality of switched terminals 31 _{1 to} 31 _n and the common terminal 30 is controlled to be switched in accordance with the control signal 2. That is, in the coded data switch 3, the multi coded data input terminal 8
1 has a function of branching (dividing) the bit stream of the input stream 1 supplied to 1 according to the control signal 2 from the control signal input terminal 82 and outputting the result. The details of the branch operation (divide operation) in the encoded data switch 3 will be described later.

The VBV memory 5 is provided as storage means according to the present invention, and functions as a so-called VBV buffer. Each bit stream branched (divided) from the input stream 1 by the coded data switch 3 is provided. 4 are stored independently. Also, VBV
The bit stream stored in the memory 5 is read as a bit stream 6 in accordance with a stream read control signal 22 for address control supplied from a variable length decoder 8 described later. The details of the bit stream writing and reading operations in the VBV memory 5 will be described later.

The stream switch 7 is provided as a reading means according to the present invention, and a plurality (for example, n) to which the bit stream stored in the VBV memory 5 is supplied.
) Switched terminals 70 ₁ to 70 _n and a common terminal 71, and the plurality of switched terminals 70 ₁ to 70 _n according to a switch control signal 21 from a switch (SW) control unit 19 described later. The connection between one of them and the common terminal 71 is switched and controlled. That is, the stream switch 7 has a function of selectively outputting the bit stream 6 read from the VBV memory 5 according to the switch control signal 21. The bit stream 6 selected by the stream switcher 7 according to the switch control signal 21
Is sent to the decompression decoding means according to the present invention having the configuration after the variable length decoder 8. The details of the operation of the selection output in the stream switcher 7 will be described later.

The variable length decoder 8 receives the bit stream (encoded data) selected and output by the stream switcher 7 and decodes (decodes) each data according to a method defined by MPEG. That is, the variable length decoder 8 decodes coding information of a macroblock, which is a unit obtained by dividing an image into small sections, and separates a coding mode, a motion vector, quantization information, a quantized DCT coefficient, and the like. Is done. The encoded information of the macroblock decoded by the variable length decoder 8 is further divided into 8 × 8 small section blocks and supplied to the inverse quantizer 9 at the subsequent stage.

The inverse quantizer 9 performs an inverse quantization process on the quantized DCT coefficients divided into 8 × 8 to restore the DCT coefficients.

The IDCT unit 10 performs an inverse DCT process on the DCT coefficient output from the inverse quantizer 9 to convert the DCT coefficient into pixel data in a pixel space.

The adder 11 converts the pixel data output from the IDCT unit 10 and the predicted image data output from a motion compensation predictor 8 described later, which operates according to the motion compensation control data 23 output from the variable length decoder 8. The image data is obtained by the addition. This video data is video data obtained by demodulating the bit stream 6 selected by the stream switch 7. The video data output from the adder 11 is supplied to a demodulation output switch 12.

The demodulated output switch 12 includes a common terminal 120 to which a video data from the adder 11 is supplied, a plurality (n respectively connected to the image memory 14 ₁ to 14 _n of the subsequent plurality of (for example, n pieces) ) Switched terminals 121 _1-
121 _n , and the connection between any _{one of the} plurality of switched terminals 121 _{1 to} 121 _n and the common terminal 120 is switched by a switch control signal 21 from the switch control unit 12. It is. That is, the demodulation output switch 12 converts the video data from the adder 11 into the switched terminals 121 _{1 to} 121 _n according to the same switch control signal 21 used for switching control of the stream switch 7.
And it has a function of dividing and outputting to one of (output by dividing the one of the image memories 14 ₁ ~14 _n).

By the processing up to this point, the bit stream sequentially selected by the stream switcher 7 is sequentially decoded by the MPEG decoding means from the variable length decoder 8 to the adder 11, and further sequentially by the decoding. Each of the obtained video data is transmitted to the demodulation output switch 12.
It will be sent by dividing (branch) to one of the image memories 14 ₁ to 14 _n by.

The image memory 14 ₁ to 14 _n are output in the image data output from the demodulator output switch 12, and the video 2 sheets equivalent to the I picture and P picture as referred to the MPEG system, the B picture Field video 1 used when performing field conversion on a frame image in a macroblock when performing
And a plurality of (n) video output terminals 151 to ₁ provided corresponding to each other.
_5n , the video data 15 finally decoded is output, and the I image and the P image as prediction reference images in the MPEG decoding are supplied to the image memory switch 17 as video data 16.

The image memory switch 17, the switch terminal 171 ₁ ~171 _n of a plurality (e.g., n) of which the video data 16 from the image memory 14 ₁ to 14 _n are supplied
And a common terminal 170, and the switch control unit 1
The connection control between any _{one of the} plurality of switched terminals 171 _{1 to} 171 _n and the common terminal 170 is controlled by the switch control signal 21 from 9. That is, the image memory switch 17 in accordance with the switch control signal 21 has a function for selecting and outputting the video data output from the image memory 14 ₁ to 14 _n. The video data selected by the image memory switch 17 is sent to the motion compensation predictor 18.

The motion compensation predictor 18 includes a variable length decoder 8
The image data output from the image memory switch 17 is supplied to the adder 11 in accordance with the control of the motion compensation control decoder 23 output from.

The switch control unit 19 includes the variable length decoder 8
The stream switching unit 7 and the demodulation output switching unit 1 according to the variable length decoding status data 20 supplied from
2. It outputs a switch control signal 21 for switching the switches of the image memory switch 17 in conjunction with each other. here,
As a method of determining the timing of switching these switches, for example, a method of switching each bit stream every time decoding of each bit stream is completed in units of macroblocks can be considered.

The above is the basic operation of the MPEG image decoding apparatus according to the present embodiment.

Next, the memory allocation of the VBV memory 5 in the MPEG image decoding apparatus according to the present embodiment will be described.

First, in the MPEG image decoding apparatus, for example, when performing the above-mentioned multi SD decoding, the storage area of the VBV memory 5 is divided into a plurality of VBV buffer areas as a first memory allocation,
The D stream is sequentially stored in the corresponding VBV buffer area and read out.

As a specific example of the first memory allocation, the three-channel SD shown in FIG.
As an example of decoding the input stream 1 in which the streams S0, S1, and S2 are time-division multiplexed, the entire storage area of the VBV memory 5 shown in FIG. 3A is shown in FIG. Thus, for example, the VBV buffer area Va0 in which the SD stream S0 in FIG.
And V in which the SD stream S1 of FIG.
The BV buffer area Va1 and the VBV buffer area Va2 in which the SD stream S2 of FIG. 2A is stored are divided into the VBV buffer areas Va1, Va2, and Va3. The data is sequentially written into each memory area in the access order indicated by A0 to AN, and then read out in the writing order.

That is, when writing the input stream 1 having the data structure shown in FIG. 2A into the VBV memory 5, for example, the first SD stream S0 is, for example, the first memory area (A0) of the VBV buffer area Va0. And the next SD stream S1 is stored in the first memory area (A0) of the VBV buffer area Va1, for example.
For example, the D stream S2 is stored in the first memory area (A0) of the VBV buffer area Va2, the next SD stream S1 is stored in the second memory area (A1) of the VBV buffer area Va0, and the next SD stream S1 is stored in the second memory area (A1). VBV
In the second memory area (A1) of the buffer area Va1,
The next SD stream S2 is a VBV buffer area Va.
In the second memory area (A1) of No. 2, the SD stream of each channel is stored from the first memory area of the corresponding VBV buffer area to the access order of symbols 0A to AN in FIG. Is done.

In order to realize such a write operation to the VBV memory 5, the coded data switch 3 in the preceding stage performs the first SD stream S0 in accordance with the control signal 2 shown in FIG. Is sent to the VBV buffer area Va0, and the next SD stream S1 is sent to the VBV buffer area Va0.
The next SD stream S2 is stored in the buffer area Va1, the next SD stream S1 is stored in the VBV buffer area Va0, and the next SD stream S2 is stored in the VBV buffer area Va0.
A branch operation such as sending the stream S1 to the VBV buffer area Va1, sending the next SD stream S2 to the VBV buffer area Va2, and so on is performed.

When reading the SD stream from the VBV memory 5 to which the writing has been performed as described above, first, for example, the SD stream S0 stored in the first memory area (A0) of the VBV buffer area Va0 is used.
Is read out, and then the SD stream S1 stored in, for example, the head memory area (A0) of the VBV buffer area Va1 is read out, and then the SD stream S1 is stored in the head memory area (A0) of the VBV buffer area Va2, for example. The stored SD stream S2 is read, and thereafter, similarly, the second memory area (A) of the VBV buffer area Va0
The SD stream S1 stored in 1) is
The SD stream S1 stored in the second memory area (A1) of the V buffer area Va1 is followed by the VBV
In the figure, the SD streams S2 stored in the second memory area (A1) of the buffer area Va2 are sequentially shifted from the head memory area of the corresponding VBV buffer area to the corresponding SD stream of each channel, as shown in FIG. They are read out in the order of access indicated by symbols A0 to AN.

When such a read operation from the VBV memory 5 is performed, the stream switch 7 at the subsequent stage first selects the SD stream S0 read from the VBV buffer area Va0, and then selects the VBV The SD stream S1 read from the buffer area Va1 is
Next, S read from the VBV buffer area Va2
Similarly, the D stream S2 is read from the SD stream S1 read from the VBV buffer area Va0, the SD stream S1 read from the VBV buffer area Va1, and then from the VBV buffer area Va2. The selection operation is performed in such a manner that the output SD stream S2 is selected. In other words, in this case,
The switch control signal 21 supplied to the stream switch 7 is a signal that realizes the above-described selection operation.

Further, the variable-length decoders 8 to adders 11 at the subsequent stage decompress and decode the supplied SD streams, and the demodulation output switching unit 12 converts the decompressed video data into the SD streams of the SD streams. corresponding to each channel to send to the image memory ₁₄ 1 to 14 _n and. As a result, the S of each channel is stored in each image memory.
The video data decoded from the D stream is held and read independently.

According to the MPEG image decoding apparatus shown in FIG. 1 as described above, a plurality of time-division multiplexed SD streams can be simultaneously processed by employing the first memory allocation when performing multi-SD decoding. Decoding and outputting are possible.

On the other hand, in the MPEG image decoding apparatus shown in FIG. 1, for example, when HD decoding is performed, the amount of data processing is increased as compared with the case where the SD stream is decoded, and the VBV buffer is compared with the case where the SD stream is decoded. As a result, the required capacity increases. Therefore, when performing HD decoding, the entire storage capacity of the VBV memory 5 is used.

As a method of memory allocation of the VBV memory 5 when HD decoding is performed in the MPEG image decoding apparatus, for example, the entire storage area of the VBV memory 5 is stored in one VBV buffer as in a second memory allocation described below. Treat linearly as an area, one H
A method of storing and reading out the D stream in the one VBV buffer area VA sequentially from the head address is conceivable.

More specifically, according to the second memory allocation, when the HD stream is written to the VBV memory 5, the first HD stream is added to the head memory area (A0) of the VBV buffer area VA, that is, the head address. The next HD stream is sequentially stored in the VBV buffer area VA in the second memory area (A1), the next HD stream is stored in the third memory area (A2), and so on. Region V
The data is stored in the order of access indicated by A0 to AM in FIG.

It should be noted that VBV at the time of such HD decoding is used.
When the writing operation to the memory 5 is realized, the encoded data switch 3 at the preceding stage operates to divide the HD stream and send the divided HD stream to the VBV buffer area VA as it is.

When reading the HD stream from the VBV memory 5 to which the writing has been performed as described above, first, for example, the HD stream stored in the head memory area (A0) of the VBV buffer area VA is read. Then, the VBV buffer area VA is read in such a manner that the HD stream stored in the second memory area (A1) is read, and then the VBV buffer area VA is read such that the HD stream stored in the third memory area (A2) is read. The HD stream stored in the buffer area VA is read out sequentially from the head address.

It should be noted that VBV at the time of such HD decoding is used.
When the read operation from the memory 5 is performed, the stream switch 7 at the subsequent stage directly converts the HD stream read from the VBV buffer area into a variable-length decoder 8.
Works to send to. In this case, the operation after the variable length decoder 8 is the same as the conventional example.

The MPEG image decoding apparatus according to the embodiment of the present invention can switch between the multi-SD decoding and the HD decoding, but in this case,
The first memory allocation and the second memory allocation described above are switched between each other. Therefore, at the time of the mutual switching, the first memory allocation is switched to the second memory allocation, or the second memory allocation is switched to the first memory allocation. An initialization operation to memory allocation is required.

For example, using the VBV memory 5 having the storage areas shown in FIGS. 3A and 4A, a multi SD card as shown in FIGS. 3B and 4B is used. It is assumed that the state of the first memory allocation at the time of decoding is switched to HD decoding at time t0 shown in FIG. 4C, for example, and the second memory allocation is performed. Note that t in each of the following drawings corresponds to the time required for one write or read access to the VBV memory 5.

In this case, in the VBV memory 5, FIG.
Immediately after the switching at the time t0 shown in (C), the second memory allocation is set and the VBV memory 5
Is used linearly as the VBV buffer area VA. That is, FIG.
After time t0, data is written sequentially from the head address of the VBV memory 5. Therefore, when time elapses from time t0 to time t2 (A0 to A
2 is performed), data is written in the VBV memory 5 in the third to third memory areas (A0 to A2) as shown in FIG. 4D. Further, when a time elapses from time t0 to, for example, time t5 (when access from A0 to A5 is performed), as shown in (E) of FIG.
When data is written in the memory areas up to the first memory area (A0 to A5) and, for example, time t11 has elapsed from time t0 (access to A0 to A11 has been performed), FIG. As described above, data is written in the VBV memory 5 in the twelfth memory area (A0 to A11) from the head.

Here, even when switching from the multi SD decoding to the HD decoding is performed, in order to decode all the SD streams stored in the VBV memory 5, as shown in FIG. At time t0, it is necessary to read out the data of all SD streams stored in each of the VBV buffer areas Va0 to Va2.

For example, when the writing of the data of the HD stream is started sequentially from the head address of the VBV memory 5, for example, each of the VBV buffer areas Va0 to V
If the data of the SD stream is alternately read from a2, the SD stream before decoding will not be overwritten until time t3. However, after time t4, the data of the SD stream before decoding is overwritten with the data of the HD stream, and a situation occurs in which the data of the SD stream that has not been decoded is erased.

Conversely, for example, the VBV memory 5 having the storage areas shown in FIG. 3A and FIG. 5A is used, and the second decoding at the time of HD decoding as shown in FIG. From the state of the memory allocation, for example, FIG.
It is assumed that the switching to the multi SD decoding is performed at time t0 shown in FIG.

In this case, the VBV memory 5
Immediately after the switching at the time t0 shown in (C), the first memory allocation is set and the VBV memory 5 is set.
Are divided and used alternately in the VBV buffer areas Va0 to Va2. That is, FIG.
After time t0, data is written alternately from the first memory area of each of the VBV buffer areas Va0 to Va2 of the VBV memory 5 in the access order indicated by the symbols A0 to AN in the drawing. Therefore, when, for example, time t2 has elapsed from time t0 (when each VBV buffer area has been accessed by A0), the VBV buffer area Va0 is stored in the VBV memory 5 as shown in FIG.
Memory area (A0) and VBV buffer area Va
1 memory area (A0) and VBV buffer area V
Data will be written to the first memory area (A0) of a2. Further, when e.g., time t5 has elapsed from time t0 (when A0 and A1 are accessed in each VBV buffer area), the VBV buffer area Va0 is stored in the VBV memory 5 as shown in FIG. The first and second memory areas (A0, A1) and the first and second memory areas (A0, A1) of the VBV buffer area Va1
1) and data are written to the first and second memory areas (A0, A1) of the VBV buffer area Va2,
For example, when a time elapses from time t0 to time t11 (each V
In the case where A0 to A3 are accessed in the BV buffer area), as shown in FIG.
The fourth to fourth memory areas (A0 to A3) of the BV buffer area Va0, the fourth to fourth memory areas (A0 to A3) of the VBV buffer area Va1, and the fourth to fourth memories of the VBV buffer area Va2. Data is written to the areas (A0 to A3).

Here, even when switching from HD decoding to multi-SD decoding is performed, in order to decode all HD streams stored in the VBV memory 5, the time shown in FIG. VB at time t0
It is necessary to read all HD stream data stored in the V buffer area VA.

However, when the writing of the data of the SD stream is started after the time t0, the data of the HD stream is sequentially read from each memory area of the VBV memory 5 (start address). At times t2 and t5 in (D) and (E), the data of the HD stream that has not been decoded is overwritten by the data of the SD stream,
A situation occurs in which the data of the D stream is erased.

As described above, if the second memory allocation that linearly uses the entire storage capacity of the VBV memory 5 is adopted as the memory allocation in the case of HD decoding, for example, the SD multi-decoding and the HD decoding can be mutually performed. There is a problem that the decoded video signal is always interrupted when switching to.

Therefore, in the embodiment of the present invention, the following third memory allocation is adopted as the memory allocation for HD decoding.

In the third memory allocation, as shown in FIG. 6, during HD decoding, the entire storage area of the VBV memory 5 shown in FIG.
6B, while maintaining the relationship of the VBV memory area at the time of the first memory allocation shown in FIG. 6B, as shown in FIG. A method of interleaving and accessing each VBV memory area is adopted.

That is, when HD decoding is performed, the entire storage area of the VBV memory 5 shown in FIG.
(C), the VBV buffer areas Va0 to Va
Use in two parts. However, in the case of the third memory allocation, each VBV buffer area Va1, Va1,
Writing and reading of HD stream data to and from Va2 are performed in an interleaving manner. That is, writing and reading of HD stream data to and from each of the VBV buffer areas Va1, Va2, and Va3 are performed in the access order indicated by A0 to AM in FIG. 6C.

More specifically, when writing HD stream data to the VBV memory 5 in the third memory allocation, at the first access A0, data is written to the head memory area of the VBV buffer area Va0, In the access A1, the next access A2 is stored in the first memory area of the VBV buffer area Va1.
In the first memory area of the VBV buffer area Va2,
Similarly, in the next access A3, in the second memory area of the VBV buffer area Va0 in the next access A4, in the second memory area of the VBV buffer area Va1 in the next access A4, and in the second memory A2 of the VBV buffer area Va2 in the next access A5.
In the third memory area, the HD stream data is stored in the corresponding VBV
The data is stored in order from the head memory area of the buffer area.

In order to realize such a write operation to the VBV memory 5, the preceding encoded data switch 3 sends the first HD stream to the VBV buffer area Va 0 and sends the next HD stream to the VBV buffer area. Va1, the next HD stream in the VBV buffer area Va2, and similarly, the next HD stream in the VBV buffer area Va2.
In the V buffer area Va0, the next HD stream is
In the buffer area Va1, the next HD stream is
A branch operation such as sending to the V buffer area Va2 is performed. In other words, the control signal 2 supplied to the encoded data switch 3 in this case is a fixed control signal for realizing the above-described branch operation.

When reading an HD stream from the VBV memory 5 to which writing has been performed as described above,
In the first access A0, the data stored in the head memory area of the VBV buffer area Va0 is read. In the next access A1, the data stored in the head memory area of the VBV buffer area Va1 is read. In the access A2, the data stored in the head memory area of the VBV buffer area Va2 is read. Similarly, in the next access A3, the VBV buffer area Va0 is read.
The data stored in the second memory area of the VBV buffer area Va1 in the next access A4 is the data stored in the second memory area of the VBV buffer area Va2 in the next access A4, and the data stored in the second memory area of the VBV buffer area Va2 in the next access A5. Are stored in the memory area of the HD stream in the order of...
The data is sequentially read from the head memory area of the V buffer area.

When such a read operation from the VBV memory 5 is performed, the stream switch 7 at the subsequent stage first selects the HD stream read from the VBV buffer area Va0, and then selects the HD stream read from the VBV buffer area Va0. The HD stream read from the area Va1, the HD stream read from the VBV buffer area Va2, the HD stream read from the VBV buffer area Va0, and the VBV buffer A selection operation is performed such as selecting the HD stream read from the area Va1, followed by the HD stream S2 read from the VBV buffer area Va2, and so on. In other words, the switch control signal 21 supplied to the stream switch 7 in this case is a signal for implementing the above-described selection operation.

Next, the operation of the VBV memory 5 when switching between the first memory allocation and the third memory allocation will be described below.

First, the VBV memory 5 having the storage area shown in FIG. 7A is used, and the state of the first memory allocation at the time of multi-SD decoding as shown in FIG. The operation when switching to HD decoding and performing third memory allocation at time t0 shown in FIG.

In this case, in the VBV memory 5, FIG.
Immediately after the switching of the time t0 shown in (C), the third memory allocation is set and the VBV memory 5 is set.
Are set in the order of access shown in FIG. Therefore, for example, at time t0, when switching from multi SD decoding to HD decoding is performed,
By the first access A0, the data of the HD stream is written to the head memory area of the VBV buffer area Va0 shown in FIG. 7C. Next, at time t1, the access A1 writes the data of the HD stream into the head memory area of the VBV buffer area Va1 shown in FIG. 7D, and at time t2, the access A2 causes ((A) in FIG. 7). VBV buffer area V shown in E)
HD stream data is written to the head memory area of a2. Further, when the process proceeds to time t10 and the writing up to the access A10 is performed, as shown in FIG. 7F, the HDB is stored in the VBV memory 5 in the fourth to fourth memory areas of the VBV buffer area Va0.
The stream data is written, and the HD stream data is stored in the first to third memory areas of the VBV buffer area Va2 in the first to fourth memory areas of the VBV buffer area Va1.

Here, from the multi SD decoding, the HD
In the case of switching to decoding, if the third memory allocation is adopted at the time of HD decoding, even if data of the HD stream is written to each of the VBV buffer areas Va0 to Va2 of the VBV memory 5, the first memory allocation is performed at the same time. Since the data of the SD stream is alternately read from each of the VBV buffer areas Va0 to Va2 by the memory allocation, the SD stream before decoding is not overwritten by the HD stream.
Therefore, even when switching from multi SD decoding to HD decoding is performed, all SD streams stored in the VBV memory 5 can be decoded, and the problem that the decoded video signal is interrupted at the time of the switching does not occur.

Next, the VBV memory 5 having the storage area shown in FIG. 8A is used, and the HD decoding is started from the third memory allocation state at the time of HD decoding as shown in FIG. 8B. The operation in the case where the first memory allocation is performed by switching to the first memory allocation will be described.

In this case, in the VBV memory 5, immediately after switching from HD decoding to multi SD decoding, the first memory allocation is set, and access to the VBV memory 5 is shown in FIG. They are set in the order of access. Therefore, for example, after elapse of time t2 (after access to A0 is performed in each VBV buffer area), as shown in FIG.
The data of the SD stream is stored in the first memory area (A0) of each of the V buffer areas Va0 to Va2. Thereafter, for example, at time t5 (after the access of A0 and A1 is performed in each VBV buffer area), as shown in FIG.
The first and second memory areas of Va2 (A0,
A1) stores the data of the SD stream. For example, at time t8 (after the access of A0 to A2 is performed in each VBV buffer area), as shown in FIG. 3E, the VBV buffer area Va0 The data of the SD stream is stored in the first to third memory areas (A0, A1, A2) of the first to third Va2.
In (after the access of A0 to A3 in each VBV buffer area), as shown in FIG. 3F, the first to fourth memory areas (A0, A1) of the VBV buffer areas Va0 to Va2, respectively. , A2, A3) store the data of the SD stream.

Also in the case of switching from the HD decoding to the multi SD decoding, the third memory allocation is adopted for the HD stream, so that each of the VBV buffer areas Va0 to Va2 of the VBV memory 5 is stored in the SD memory by the first memory allocation. Even if the data of the stream is written, the HD stream data before decoding is overwritten by the SD stream by reading the HD stream data alternately from the VBV buffer areas Va0 to Va2 by the third memory allocation at the same time. It won't. Therefore, even when switching from HD decoding to multi-SD decoding is performed, it is possible to decode all HD streams stored in the VBV memory 5, and there is no problem that the decoded video signal is interrupted at the time of the switching.

The above-mentioned block unit is a fixed arbitrary data length, for example, 8 bytes or 64 bytes,
56 bytes or the like can be considered.

Through the above processing steps, the MP according to the present invention
The EG image decoding device relates to a transition between a state of decoding a plurality of streams and a state of decoding a single stream,
Video can be seamlessly connected without interruption.

That is, M of the above-described embodiment of the present invention
According to the PEG image decoding device, a plurality of MPs of MP @ ML
EG encoded bit stream (SD stream)
Can be simultaneously decoded (multi-SD decoding) and output.
Single MP @ HL and MP @ H-1440L MPEG
Even when switching to a state in which the coded bit stream (HD stream) is being decoded (HD decoded), seamless switching is possible because there is no need to initialize the VBV memory 5.

[0081]

As is apparent from the above description, in the signal decoding method and apparatus according to the present invention, a bit stream obtained by time-division multiplexing a plurality of compression-encoded bit streams is converted into a plurality of bit streams. Each bit stream is divided according to a control signal for distinction, each bit stream is stored, and the stored bit stream is switched to time division to be read out and decompressed and decoded. Can be simultaneously realized while suppressing an increase in scale and an increase in production cost.

In the signal decoding method and apparatus of the present invention, a time-division multiplexed bit stream and a single bit stream are switched and input, and when a time-division multiplexed bit stream is input, the When each divided bit stream is stored independently, and when a single bit stream is input, each data obtained by dividing the single bit stream is stored. Stream and VBV consumed by the bit streams
It is possible to seamlessly switch between a single bit stream consuming the same area as the capacity.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram illustrating a schematic configuration of an MPEG image decoding device according to an embodiment of the present invention.

FIG. 2 shows time-division multiplexed S in the embodiment of the present invention.
FIG. 4 is a diagram used to explain a data format of a D stream and a control signal.

FIG. 3 is a diagram used to explain first and second memory allocations;

FIG. 4 is a diagram used to explain transition of the contents of a VBV memory when switching from multi SD decoding using a first memory allocation to HD decoding using a second memory allocation;

FIG. 5 is a diagram used to describe transition of contents of a VBV memory when switching from HD decoding using the second memory allocation to multi-SD decoding using the first memory allocation.

FIG. 6 is a diagram used to explain first and third memory allocations;

FIG. 7 is a diagram used to describe transition of the contents of a VBV memory when switching from multi SD decoding using a first memory allocation to HD decoding using a third memory allocation.

FIG. 8 is a diagram used to explain the transition of the contents of the VBV memory when switching from HD decoding using the third memory allocation to multi-SD decoding using the first memory allocation.

FIG. 9 is a block circuit diagram illustrating a schematic configuration of an MPEG image decoding device according to a conventional technique.

[Explanation of symbols]

81 multi-coded data input terminal, 82 control signal input terminal, 3 coded data switcher, 5
VBV memory, 7 stream switcher, 8
Variable length encoder, 9 inverse quantizer, 10 IDCT
Device, 11 adder, 12 demodulation output switching device, 1
4 image memory, 17 image memory switcher, 1
8 motion compensation predictor, 19 switch controller, 20
Variable length decoding status data, 21 switch control signal, 22 stream read control signal, 23
Motion compensation control data, 90 video output terminal

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5C053 FA20 GA11 GB05 GB22 GB26 GB30 GB32 GB38 HA29 HA33 KA04 KA24 LA06 5C059 KK07 KK12 MA00 MA05 MA14 MA23 MC11 ME01 RA06 RB01 SS02 UA33 UA34 UA35 UA36 5J064 AA04 BA0203 BC08 BC25 BD02

Claims (8)

[Claims] At least a bit stream in which a plurality of compression-encoded bit streams are time-division multiplexed on one data bus and a control signal for distinguishing each of the plurality of time-division multiplexed bit streams are included. Input, divide the time-division multiplexed bit stream according to the control signal, store the divided bit streams, read out the stored bit stream by switching to time division, and read in the time division A signal decoding method characterized by expanding and decoding the bit stream obtained. 2. When the time-division multiplexed bit stream and a single bit stream are switched and input, and when the time-division multiplexed bit stream is input, the time-division multiplexed bit stream is divided. 2. The signal decoding method according to claim 1, wherein each bit stream is stored independently, and when the single bit stream is input, each data obtained by dividing the single bit stream is stored. . 3. The plurality of bit streams are MPE
A bit stream of a layer below MP @ ML defined by G2 encoding, and the single bit stream is MPE
3. The signal decoding method according to claim 2, wherein MP @ H-1440L and MP @ HL defined by G2 encoding are indicated. 4. The signal decoding method according to claim 1, wherein, at the time of said decompression decoding, each decoded signal obtained by decompressing said plurality of streams is independently held. 5. A first input means for inputting a bit stream in which a plurality of compression-encoded bit streams are time-division multiplexed to one data bus, and distinguishing each of the plurality of time-division multiplexed bit streams. Second input means for inputting a control signal for performing the control, a dividing means for dividing the time-division multiplexed bit stream according to the control signal, a storage means for storing the divided bit streams, respectively, A signal decoding apparatus comprising: a reading unit that switches a bit stream stored in a storage unit to time division and reads the same; and a decompression decoding unit that decompresses and decodes the bit stream read in a time division manner. 6. The first input means switches and inputs the time-division multiplexed bit stream and a single bit stream, and the storage means secures a plurality of storage areas independently. When a division multiplexed bit stream is input, each bit stream obtained by dividing the time division multiplexed bit stream is stored independently in each storage area of the storage unit, and the single bit stream is input. 6. The signal decoding apparatus according to claim 5, wherein when the data is divided, each data obtained by dividing the single bit stream is stored in each storage area of the storage unit. 7. The plurality of bit streams are MPE
A bit stream of a layer below MP @ ML defined by G2 coding, and the single bit stream is MPE
7. The signal decoding method according to claim 6, wherein MP @ H-1440L and MP @ HL defined by G2 encoding are indicated. 8. The signal decoding apparatus according to claim 5, wherein said decompression decoding means includes holding means for independently holding each decoded signal obtained by decompressing and decoding said plurality of streams.