JPH11341489A - Image decoder and its method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out MPEG 2 decoding at a high speed. SOLUTION: A coded bit stream inputted to an image decoder 200 is stored once in an input buffer BUF 202, read by a pre-decoder (Pre-VLD) 204 by which the data length of each variable length code and an EOB are detected and the break of quantized DCT coefficients for every DCT block are detected. The bit stream read from the input buffer BUF 202 is distributed and outputted to a 1st variable length decoding section VLD 206 and a 2nd variable length decoding section VLD 212 so that the quantized DCT coefficients of the same DCT block are inputted to the same variable length decoding section based on the break. The distributed bit streams are decoded by the variable length decoding sections 206, 212 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to, for example, MEPG
Image decoding that can decode image data encoded by an encoding method including variable-length encoding processing, such as the two-method (high-quality moving image encoding method by the Moving Picture coding Experts Group), at high speed Device and a method thereof.

[0002]

2. Description of the Related Art FIG. 10 shows a configuration of a conventional decoding apparatus for decoding image data encoded by the MPEG2 system.
Shown in In the image decoding apparatus 900 shown in FIG. 10, the bit stream of the input coded image data is temporarily stored in the input buffer (BUF) 902, and is sequentially read and decoded by the variable length decoding unit (VLD) 904. The motion vector and coding mode are output to a motion compensation prediction unit (MC) 914, and the quantized DCT coefficients and quantization information are output to an inverse quantization unit (IQ) 906.

[0003] The quantized DCT coefficient input to the inverse quantization unit (IQ) 906 is inversely quantized to restore the DCT coefficient, and inverse DCT is performed by the inverse DCT unit (IDCT) 908 to restore the pixel data. . If the pixel data is an error signal, reference motion prediction image data obtained by motion prediction in a motion compensation prediction unit (MC) 914 and the error signal are added by an adder 910 to obtain the original image. The data is restored and output. When the generated data is an I-picture or a P-picture, it is stored in the frame memory (MEM) 912 because it is used as a reference screen in a later decoding process.

Incidentally, such an image decoding apparatus 900
May be implemented by a configuration as shown in FIG.
In the image decoding device 900b shown in FIG. 11, encoded video data to be decoded is input to the image decoding device 900b via an interface (I / F) 918,
It is stored in the memory 916 via the bus 920. For the data stored in the memory 916, a variable length decoding unit (VLD) 904, an inverse quantization unit (IQ) 906, an inverse D
CT unit (IDCT) 908 and motion compensation prediction unit (M
C) 914 performs the above-described processing and performs decoding. Then, the generated video data is temporarily stored in the memory 916.
And output via an interface (I / F) 918. When the image decoding device 900 is configured in a normal computer device or the like, it is often implemented by such a configuration.

[0005]

In recent years, there has been an increasing demand for faster image decoding. Further, as one method for that, a method of performing such image decoding processing by using a parallel processing architecture such as VLIW (Very Long Instruction Word) has been proposed. However,
In the above-described image decoding process, it is difficult to apply the variable length decoding process to the parallel process, and as a result, there is a problem that the speed of the entire decoding process cannot be further increased.

Generally, in a variable-length code, codes are arranged in order from the head in a bit stream for each predetermined unit, and decoding must be performed sequentially from the head when decoding. For this reason, it is not possible to perform processing such as sequentially extracting each variable length code from the encoded bit stream and distributing it to a plurality of processing systems. In particular, in MPEG2, since a unit of a variable length code is composed of data of a plurality of DCT blocks, there is a problem that parallel processing in units of DCT blocks is difficult.

Accordingly, an object of the present invention is to provide an image decoding apparatus which enables variable-length decoding to be performed in parallel, thereby enabling high-speed image decoding. Another object of the present invention is to provide an image decoding method that enables variable-length decoding to be performed in parallel, thereby enabling high-speed image decoding.

[0008]

In order to solve the above-mentioned problems, an image decoding apparatus according to the present invention provides an image decoding apparatus for decoding video data encoded into encoded data having a continuous variable-length code sequence. A decoding device, comprising: a plurality of variable length decoding means for performing variable length decoding on the variable length code; and a code for detecting a range of each of the variable length codes included in the encoded data from the encoded data. Coded data distribution for sequentially extracting coded data for each predetermined unit from the coded data based on the detected range, and allocating the coded data to each of the plurality of variable length coding means. Means, and the plurality of variable-length decoding means each performs variable-length decoding on the allocated encoded data for each of the predetermined units.

In the image decoding apparatus having such a configuration, the code range detecting means detects a range of each variable length code included in the coded data from the coded data, and based on the detected range. Then, the coded data distribution means sequentially extracts coded data for each predetermined unit from the coded data, and distributes the coded data for each predetermined unit to any of the plurality of variable length coding means. Then, the plurality of variable length decoding units perform variable length decoding on the distributed encoded data for each predetermined unit. That is, the plurality of prefectural office encoding units perform the variable length decoding processing in parallel.

[0010] Further, an image decoding method according to the present invention is an image decoding method for decoding video data which has been encoded into encoded data having a continuous variable length code sequence. Detecting a range of each of the variable-length codes included in the encoded data, extracting encoded data for each predetermined unit from the encoded data, based on the detected range, Variable-length decoding is performed in parallel on the encoded data for each of the predetermined units.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to FIGS. In the present embodiment, an image decoding device according to the present invention and an image encoding device suitable for generating encoded image data to be decoded in the image decoding device will be described.

First, an image coding apparatus is shown in FIGS.
This will be described with reference to FIG. This image coding apparatus converts input video data into a moving picture coding (MPEG2) format.
A video recording device for recording video data including video data, video data in the form of a television signal, and the like. Is a device applied to a transmission device or the like for distributing a.

FIG. 1 is a block diagram showing the configuration of the image coding apparatus 100. The image coding apparatus 100 includes an adder 102, a DCT unit (DCT) 104, a quantization unit (Q) 106, a variable length coding unit (VLC) 108, an output buffer (BUF) 110, and an inverse quantization unit (IQ). 11
2. It has an inverse DCT unit (IDCT) 114, an adder 116, a frame memory (MEM) 118, and a motion compensation prediction unit (MC) 120.

The image coding apparatus 100 performs analog / digital (A / D) conversion, performs format conversion processing to a predetermined spatial resolution suitable for coding, and further performs I (Intra coded) processing for performing predictive coding. ) Picture, P (Pr
edictive coded picture, B (Bidirectionally pred)
Video data resulting from rearranging pictures according to each picture type of (ictive coded) pictures is sequentially input. The image encoding device 100 sequentially encodes each picture in the input order. It should be noted that encoding of each picture is performed on a macroblock basis.

When each macroblock of the input picture is in the motion compensation prediction mode, the adder 102 receives the macroblock image data obtained by the motion prediction processing on the reference screen in the motion compensation prediction unit (MC) 120. The difference is taken, and a DCT unit (DCT) 1 is used as a prediction error.
04. When the macroblock to be processed is in the intra-coding mode, the input image data is output to the DCT unit (DCT) 104 as it is.

The DCT unit (DCT) 104 includes an adder 10
2 is a discrete cosine transform (DCT: Discret) in units of blocks of 8 pixels × 8 lines.
e Cosine Transform), and transforms the signal into the spatial frequency domain, and outputs the obtained transform coefficient to the quantization unit (Q) 106.

The quantization unit (Q) 106 includes a DCT unit (DC
T) 104, the 8 × 8 DCT coefficient is quantized according to the target bit and visual characteristics, and the generated quantized DCT coefficient is sent to the variable length coding unit (VLC) 108 and the inverse quantization unit (IQ) 112. Output.

The variable length coding unit (VLC) 108 includes quantized DCT coefficient data input from the quantization unit (Q) 106, a prediction coding mode input from the motion compensation prediction unit (MC) 120, and the like. Macroblock coding information such as a motion vector is coded by a variable length code and output to an output buffer (BUF) 110.

A method of coding the quantized DCT coefficients in the variable length coding unit (VLC) 108 will be described in detail. In the variable length coding unit (VLC) 108, first, the 8 × 8 quantized by the quantization unit (Q) 106
As shown in FIG. 2, the DCT coefficients of each DCT block are zigzag scanned from the upper left and rearranged. In the rearranged quantized coefficients, variable-length coding is performed by a method different from the DC component, which is the first data of the intra block, and the other components.

As for the DC component, the luminance signal Y sequentially traces the luminance signal component of each DCT block in the macroblock, the chrominance signal traces each of Cr and Cb separately, and the difference value of each signal is represented by its size. And the actual value following it. At this time, each size is
It is indicated by a predetermined variable length code (VLC) separately provided for the luminance signal Y and the color difference signals Cr and Cb.

For the AC component, a variable length code (V) is used for a combination of the number of zero coefficients (run) and the value of a non-zero quantization coefficient (level).
LC), two-dimensional variable length coding (two-dimensional VLC) is performed. For this pair of run and level, the frequently occurring 11
For three, VLC as shown in FIG. 3 is defined in advance and used. Also, EOB (End Of Block) is added as a code indicating the end of the non-zero coefficient.

Runs (ru) other than 113 shown in FIG.
For the combination of n) and level,
It is expressed by a combination of a run and a level following a code defined as an escape in the VLC shown in FIG. The run at this time is a fixed-length code (F) as shown in FIG.
LC), and a fixed-length code (FLC) as shown in FIG. Therefore,
When the absolute value of the level (level) is 127 or less, escape (escape) 6 bits, run (run) 6
The absolute value of the level is from 128 to 2 in the form of 20 bits of 8 bits and a level.
Up to 55, escape 6 bits,
It is represented in a 28-bit format with a run of 6 bits and a level of 16 bits.

The variable length coding unit (VLC) 108 performs such variable length coding.

The output buffer (BUF) 110 accumulates variable-length encoded data input from the variable-length encoding unit (VLC) 108. Output buffer (BUF) 11
The coded video data stored in 0 is at a predetermined rate,
Alternatively, it is output from the image encoding device 100 as an MPEG bit stream as required.

An inverse quantization unit (IQ) 112 inversely quantizes the quantized DCT coefficient data input from the quantization unit (Q) 106, generates a DCT coefficient, and generates an inverse DCT unit (IDC).
T) 114.

The inverse DCT unit (IDCT) 114 performs an inverse discrete cosine transform (IDCT) of the DCT coefficient input from the inverse quantization unit (IQ) 112, generates pixel space data, and outputs it to the adder 116. .

The adder 116 has an inverse DCT unit (IDCT)
When the pixel data input from 114 is differential data that has been subjected to inter-frame prediction coding, a macroblock obtained by performing motion prediction processing on a reference screen input from the motion compensation prediction unit (MC) 120 The difference data is added to the image data to generate original pixel data. The generated image data is stored in a frame memory (MEM) 118.
Output to

The frame memory (MEM) 118 is a memory for storing the image data generated by the adder 116. The image data stored in the frame memory (MEM) 118 is referred to by the motion compensation prediction unit (MC) 120.

The motion compensation prediction unit (MC) 120 performs a motion prediction process using the image data stored in the frame memory (MEM) 118 as a reference screen, and
And output to the adder 116.

The operation of the image coding apparatus 100 having such a configuration will be described. As described above, video data that has been subjected to predetermined pre-processing such as A / D conversion, format conversion, and picture rearrangement is input to the image coding apparatus 100, and processing is performed in macroblock units. .
That is, when the macro block is in the motion compensation prediction mode, the adder 102 sets the frame memory (M
A difference between the reference image stored in the EM 118 and macroblock image data obtained by performing motion prediction in the motion compensation prediction unit (MC) 120 is obtained to obtain a prediction error.

The pixel data of the macroblock in the case of the intra coding mode and the prediction error data in the case of the motion compensation prediction mode are converted by a DCT (DCT) 104.
DC in units of DCT blocks of 8 pixels x 8 lines
T is generated to generate a DCT coefficient, and the quantization unit (Q) 106
, And a quantized DCT coefficient is generated, is subjected to variable-length coding by a variable-length coding unit (VLC) 108, and is stored in an output buffer (BUF) 110.

Since the data of the I and P pictures need to be used as a reference screen in the subsequent motion compensation prediction processing, the data is inversely quantized by an inverse quantization unit (IQ) 112 and an inverse DCT unit (IDCT) The inverse DCT is performed at 114, the original image data is generated from the difference data at the adder 116, and stored in the frame memory (MEM) 118. The image data stored in the frame memory (MEM) 118 is subjected to a motion prediction process in a motion compensation prediction unit (MC) 120, and the macroblock image data generated by the motion prediction process is further added to an adder 102 and an adder 102. It is used for generating difference data in the unit 116 and for generating original pixel data from the difference data.

The coded data generated by such processing and stored in the output buffer (BUF) 110 is output from the image coding apparatus 100 as an MPEG bit stream at a predetermined rate or on demand. Is done.

Next, an image decoding apparatus according to the present invention will be described with reference to FIGS. This image decoding apparatus decodes, for example, MPEG2-encoded video data encoded by, for example, the above-described image encoding apparatus 100, which is reproduced from a data recording apparatus or transmitted via a transmission path, for example. Is a device for restoring the image data and outputting it so that it can be displayed on a display device, for example.

FIG. 5 is a block diagram showing the configuration of the image decoding apparatus 200. The image decoding device 200 includes an input buffer (BUF) 202, a pre-variable-length decoding unit (P
re-VLD) 204, a first variable length decoding unit (VL)
D) 206, first inverse quantization section (IQ) 208, first inverse DCT section (IDCT) 210, second variable length decoding section (VLD) 212, second inverse quantization section (IQ) 214,
It has a second inverse DCT unit (IDCT) 216, a first changeover switch 218, a second changeover switch 220, an adder 222, a frame memory (MEM) 224, and a motion compensation prediction unit (MC) 226.

First, the configuration of the image decoding device 200 will be described. The input buffer (BUF) 202 temporarily stores an input coded bit stream. If the input encoded data is fixed-rate data,
Data is input to the input buffer (BUF) 2020 at a constant rate. The data stored in the input buffer (BUF) 202 is transmitted to a pre-variable-length decoding unit (Pre-
VLD) 204.

Pre-variable length decoding unit (Pre-VLD)
(Hereinafter, referred to as a predecoder.) 204 sequentially reads the coded bit stream stored in the input buffer (BUF) 202, and outputs the first variable length decoding unit (VL).
D) 206 and second variable length decoder (VLD) 21
2 and output. For this distribution, the pre-decoder (Pre-VLD) 204 detects a code break of each code included in the bit stream, and further detects a break of the quantized DCT coefficient for each DCT block from the break. I do.

For this purpose, a pre-decoder (Pre-VL)
D) 204 is a quantization DC of the AC component of the DCT block.
Regarding the variable length code (VLC) as shown in FIGS. 3 and 4 for the T coefficient, its code length and EOB (En
d Of Block). However, at this time, since the pre-decoder (Pre-VLD) 204 only needs to obtain the code length, it does not have a function until the decoded data is generated.

Pre-decoder (Pre-VLD) 204
The input buffer (BUF) 2 is configured to output the quantized DCT coefficients of at least one DCT block to the same variable-length coding unit based on the detected delimiter.
The bit stream read out from H.02 is distributed to a first variable length decoding unit (VLD) 206 and a second variable length decoding unit (VLD) 212 and output.

First variable length decoding unit (VLD) 206
Decodes the bit stream input from the pre-decoder (Pre-VLD) 204. The first variable length decoding unit (VLD) 206 decodes macroblock coding information of the input bit stream, and sets the coding mode,
A motion vector, quantization information, a quantized DCT coefficient, and the like are separated and decoded. The coding mode and the motion vector information are sent to the motion compensation prediction unit (MC) 226 via the second changeover switch 220, and the quantization information and the decoded quantized DCT coefficient are sent to the first inverse quantization Output to the conversion unit (IQ) 208.

The first inverse quantization unit (IQ) 208 has a first
, The quantized DCT coefficient input from the variable length decoding unit (VLD) 206 is inversely quantized, restored to the DCT coefficient,
To the inverse DCT unit (IDCT) 210.

The first inverse DCT unit (IDCT) 210
DCT input from first inverse quantization section (IQ) 208
The coefficients are subjected to inverse discrete cosine transform (IDCT) to generate pixel space data, and output to the adder 222 via the first switch 218.

Second variable length decoding section (VLD) 212
Is similar to the first variable length decoding unit (VLD) 206,
The bit stream input from the pre-decoder (Pre-VLD) 204 is decoded. That is, the macroblock coding information of the input bit stream is decoded, the coding mode, the motion vector, the quantization information, the quantized DCT coefficients, and the like are separated and decoded. Then, the information on the coding mode and the motion vector is sent to the motion compensation prediction unit (MC) 226 via the second switch 220.
Then, the quantized information and the decoded quantized DCT coefficient are output to a second inverse quantization unit (IQ) 214.

The second inverse quantization unit (IQ) 214 has a second
, The quantized DCT coefficient input from the variable length decoding unit (VLD) 212 is inversely quantized, restored to the DCT coefficient,
To the inverse DCT unit (IDCT) 216.

The second inverse DCT unit (IDCT) 216
DCT input from second inverse quantization section (IQ) 214
The coefficients are subjected to inverse discrete cosine transform (IDCT) to generate pixel space data, and output to the adder 222 via the first switch 218.

The first changeover switch 218 switches between pixel data output from the first inverse DCT unit (IDCT) 210 and pixel data output from the second inverse DCT unit (IDCT) 216. This is a switch for selection, and the selected pixel data is output to the adder 222. Note that the first changeover switch 218 operates so that the data that has been distributed by the pre-decoder (Pre-VLD) 204 in units of data for each DCT block and subjected to parallel processing becomes the original sequential data again. It is appropriately switched based on the distribution state in the pre-decoder (Pre-VLD) 204. This switching signal is generated by a control unit (not shown) of the image decoding device 200 and applied to the first switch 218.

The second changeover switch 220 includes information on the coding mode and the motion vector output from the first variable length decoding unit (VLD) 206 and the second variable length decoding unit (VLD) 212. A switch for selecting any of the encoding mode and the motion vector information output from the motion compensation prediction unit (M
C) Input to 226. Second changeover switch 22
0 operates in conjunction with the first changeover switch 218. That is, based on a switching signal generated by a control unit (not shown) of the image decoding device 200, each information is stored in the motion compensation prediction unit (MC) 226 in the order of the input data.
Is switched to be input to.

The adder 222 is input from the motion compensation prediction unit (MC) 226 when the pixel data selected and input by the first changeover switch 218 is differential data that has been subjected to inter-frame prediction coding. The difference data is added to macroblock image data obtained by performing a motion prediction process on the reference screen to generate original pixel data, which is output to the image decoding device 200. The data generated by the adder 222 is stored in a frame memory (M
EM) 224.

The frame memory (MEM) 224 is a memory for storing the image data generated by the adder 222, and stores the stored image data in the motion compensation prediction unit (MC) 2.
26.

The motion compensation prediction unit (MC) 226 uses the image data stored in the frame memory (MEM) 224 as a reference screen, and sets the coding mode and the motion vector input through the second switch 220. Based on this, the motion prediction processing is performed, and the result is output to the adder 222.

Next, the operation of the image decoding apparatus 200 will be described. The bit stream of the encoded image data input to the image decoding device 200 is temporarily stored in an input buffer (BUF) 202, and is stored in a pre-decoder (Pr).
e-VLD) 204 as appropriate. The pre-decoder (Pre-VLD) 204 includes an input buffer (BU).
F) The data length of each variable length code is detected from the bit stream read from 202.

In particular, regarding the quantized DCT coefficient subjected to variable length coding, the data length and EOB (End Of
Block) and quantized DCT for each DCT block
Detect coefficient breaks. The bit stream read from the input buffer (BUF) 202 is subjected to the first variable length decoding so that the quantized DCT coefficients of the same DCT block are input to the same variable length decoding device based on this delimiter. Unit (VLD) 206 and a second variable length decoding unit (VLD) 212 for output. In other words, the input buffer (BUF) 202 and the first variable length decoding unit (VLD) 206 are switched at every break of the DCT block, for example, and each bit stream is output.

The bit streams distributed by the pre-decoder (Pre-VLD) 204 are decoded by a first variable length decoding unit (VLD) 206 and a second variable length decoding unit (VLD) 212, respectively. The generated motion vector and coding mode data are sent to the motion compensation prediction unit (MC) 226 via the second switch 220.
In addition, the generated quantized DCT coefficients and quantization information are output to the first inverse quantization unit (IQ) 208 and the second inverse quantization unit (IQ) 214.

The quantized DC input to the first inverse quantization unit (IQ) 208 and the second inverse quantization unit (IQ) 214
The T coefficients are each dequantized to restore DCT coefficients,
First inverse DCT section (IDCT) 210 and second inverse D
In the CT unit (IDCT) 216, pixel data is decoded by inverse DCT. Then, the first inverse DCT unit (IDCT) 210 and the second inverse DCT unit (IDC)
T) The pixel data respectively generated in 216 are selected by the first changeover switch 218 in the order in which they are input to the image decoding device 200, and are converted into sequential data. If the converted data is an error signal, the adder 222 adds the data to the reference motion prediction image data, and the original image data is restored and output. In the case of an I picture or a P picture, the picture is stored in the frame memory (MEM) 224 because it is used as a reference screen in later decoding processing.

In the video data decoded in this way, in a post-processing unit (not shown), decoded data of all macroblocks in the picture are collected to reconstruct the original picture, and each picture is It is rearranged to the original input order, the image size is converted if necessary,
It is output from the image decoding device 200.

As described above, in the image decoding apparatus 200 of the present embodiment, the pre-decoder (Pre-VLD)
204, whereby DCT can be performed from the variable-length coded video data, which is a bit stream that is continuously continuous.
A break of data for each block is detected, and based on the break, the data is converted to a first variable length decoding unit (VLD) 2.
06 to the first processing system of the first inverse DCT unit (IDCT) 210, and the second variable length decoding unit (VLD) 212 to the second
, And the decoding processing is performed in parallel by each processing system. That is, it is possible to set a delimiter based on the DCT block with respect to the bit stream that has been subjected to the variable-length coding, and thereby to distribute data. Therefore, it is possible to perform parallel processing of the processing of variable length decoding and below, and it is possible to perform the MPEG decoding processing at high speed.

Since the break of the DCT block can be detected without decoding, special processing such as skipping of the DCT block can be easily performed at high speed. Therefore, it is possible to perform processing such as selectively extracting and processing only a part of DCT blocks from a bit stream. For example, an image decoding apparatus having a new function such as thinning-out reproduction of encoded image data can be provided. Can be provided.

The present invention is not limited to the present embodiment, and various modifications are possible. For example, the above-described image decoding device 200 includes a pre-decoder (Pre-
VLD) 204 divides the encoded data into two systems, and performs each processing of a variable length decoding unit, inverse quantization, and inverse DCT.
First variable length decoding unit (VLD) 206 to first inverse DC
A first processing system of a T unit (IDCT) 210, a second variable length decoding unit (VLD) 212 to a second inverse DCT unit (ID
CT) 216 in parallel with the second processing system. However, the range in which the parallel processing is performed may be set as appropriate.

The present invention relates to a pre-decoder (Pre-VL).
D) The provision of 204 allows a data segment to be detected without performing normal decoding on an encoded bit stream, thereby performing variable-length decoding in parallel. I do. Therefore, there is no limitation on the parallelism of the processing subsequent to the variable length decoding processing. For example, the image decoding device 2 shown in FIG.
00b, only the variable-length coding process is performed in parallel, and the subsequent inverse quantization and inverse DCT processes are performed only by the inverse quantization unit (IQ) 228 and the inverse DCT unit (IDC).
T) 230. Inverse quantization unit (IQ) 228 and inverse DCT unit (IDCT) 2
Such a configuration is preferable, for example, when the configuration is such that the processing can be performed at a high speed.

The specific configuration of the image decoding apparatus according to the present invention can be implemented in various forms other than the configurations shown in FIGS. For example, a configuration as shown in FIG. 7 may be used. The image decoding device 200c shown in FIG.
In this configuration, the respective processing units are connected via the control unit 36.

In the image decoding device 200c,
Encoded video data to be decoded is input via an interface (I / F) 234 and stored in a memory 232 via a bus 236. For the data stored in memory 232, a pre-decoder (Pre-V) having substantially the same configuration and function as the configuration shown in FIG.
LD) 204, first variable length decoding unit (VLD) 20
6. The second variable length decoding unit (VLD) 212, the inverse quantization unit (IQ) 228, the inverse DCT unit (IDCT) 230, and the motion compensation prediction unit (MC) 238 operate and perform decoding. Then, the generated video data is temporarily stored in the memory 232.
And output via the interface (I / F) 234.

In the image decoding device 200c, the reference image used for the motion prediction in the motion compensation prediction unit (MC) 238 is also stored in the memory 232. Also, a motion compensation prediction unit (MC) of the image decoding device 200c.
238 performs the motion prediction process and the process of adding the error signal obtained by the inverse DCT unit (IDCT) 230 to the reference image data, that is, the motion of the image decoding device 200b shown in FIG. Compensation prediction unit (MC) 226
And the function of the adder 222. Also, a pre-decoder (Pre-VLD) of the image decoding device 200c
204 to each processing unit of the motion compensation prediction unit (MC) 238
For example, the operation is controlled by a controller (not shown) connected to the bus 236.

For example, when the image decoding device of the present invention is mounted on a normal computer device, or when the image decoding device of the present invention is implemented by using such an architecture of the computer device, FIG. Although a configuration as shown in FIG. 7 is conceivable, such a configuration is clearly within the scope of the present invention.

In any of the cases shown in FIGS. 5 to 7, the pre-decoder (Pre-VLD) 204 to the first variable-length decoder (VLD) 206 and the second variable-length decoder (VLD) The distribution of data to 212 has been described as being performed by transferring data to be actually distributed.

Therefore, normally, as shown in FIG. 8A, a pre-decoder (Pre-VLD) 204, a first variable length decoding unit (VLD) 206, and a second variable length decoding unit (VLD) ) 212 and a buffer (BUF)
240, 242 are provided. The pre-decoder (Pre-VLD) 204 stores the appropriately extracted data in a buffer (BUF) 240 and a buffer (BUF) 242.
The first variable-length decoding unit (VLD) 206 and the second variable-length decoding unit (VLD) 212 read data from the buffers (BUF) 240 and 242 in accordance with the decoding speed. At this time, the buffer (BU)
F) 240 and 242, a pre-decoder (Pre-VL)
D) From 204, the variable length codes may be sequentially recorded, or a plurality of variable length codes may be recorded collectively. The latter is preferred for faster processing.

However, the data may be distributed simply by transferring the address on the memory indicating the data. In such a case, the pre-decoder (Pre-VLD) 204, the first variable length decoding unit (VLD) 206, and the second variable length decoding unit (VL)
D) It is preferable that the configuration of 212 is a configuration as shown in FIG. That is, with the same configuration as that shown in FIG.
In addition, the memory 23 which can be accessed from any component
2 is also connected to the bus 236.

In such a configuration, the pre-decoder (Pre-VLD) 204 accesses the coded bit stream stored in the memory 232, detects a desired data segment, and determines a data area to be sorted. I do. The pre-decoder (Pre-VLD) 204 transfers the address of each of the allocated data on the memory 232 to the first variable-length decoding unit (VLD) 2 via a bus 236.
06 and the second variable-length decoding unit (VLD) 212. The first variable-length decoding unit (VLD) 206 and the second variable-length decoding unit (VLD) 212 access the memory 232 based on the transferred address, and read out a bit stream to be processed. , The variable length decoding process as described above is performed.

The address of the data to be distributed is the first
In the variable length decoding unit (VLD) 206 and the second variable length decoding unit (VLD) 212,
The transfer of the address is not performed via the bus 236. For example, the predecoder (Pr
e-VLD) 204 to a first variable length decoding unit (VL
D) 206 and second variable length decoder (VLD) 21
2 may be directly forwarded. FIG.
8A and 8B, the predecoder (P
re-VLD) 204 and variable length decoding unit (VLD)
Although only the components related to the components 206 and 212 have been described, the other components are the same as those shown in FIGS.

In this embodiment, the pre-decoder (Pre-VLD) performs only bit stream distribution, and separates motion vectors, coding modes, and the like from variable-length coded data. First
And the second variable length decoding unit (VLD). However, for example, a predecoder (Pre-VL)
D), these are extracted and the predecoder (Pr) is extracted.
e-VLD) to the variable-length decoding unit (VLD) may output only the variable-length code of the quantized DCT coefficient. FIG. 9 shows an image decoding device 200d having such a configuration corresponding to the image decoding device 200b shown in FIG.

In the image decoding apparatus 200d shown in FIG. 9, the pre-decoder (Pre-VLD) 244 uses the bit stream read from the input buffer (BUF) 202 to extract the motion vector, coding mode, quantization information, Each data such as the quantized DCT coefficient is separated, the motion vector and the coding mode are further decoded and output to the motion compensation prediction unit (MC) 226, and the quantized information and the quantized DCT coefficient remain as the variable length code. The signal is distributed to a first variable length decoding unit (VLD) 246 and a second variable length decoding unit (VLD) 248 and output. Therefore, the first variable length decoding unit (VLD) 246 and the second
In the variable length decoding unit (VLD) 248, only the variable length decoding of the quantized DCT coefficient may be performed.
As described above, the processing between the predecoder (Pre-VLD) and the variable length decoding unit (VLD) may be shared.

In each of the above-described image decoding apparatuses, data is distributed to a plurality of subsequent processing systems such as a variable-length decoding unit in units of data for each DCT block. However, the unit for distributing this data may be arbitrary. For example, data may be distributed for each variable-length code, or data may be distributed for each macroblock larger than a DCT block.

Further, each of the above-described image decoding apparatuses has a configuration including two variable length decoding units (VLDs). However, the number of variable length decoding units (VLDs) is not limited to two, but may be three or more, and an arbitrary number may be provided.

Further, in the present embodiment, the MPE
Although the present invention has been described by exemplifying a G2 decoding apparatus, the encoding method is not limited to MPEG2. The present invention can be applied to any coding method that performs variable length coding.

[0074]

As described above, according to the image decoding apparatus and the image decoding method of the present invention, each code can be extracted from a bit stream of a variable-length code without complete decoding. Thus, each code can be distributed to a plurality of processing systems. Therefore, variable-length decoding can be performed in parallel, and image decoding can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an image encoding device according to the present invention.

FIG. 2 is a diagram illustrating a method of scanning data when outputting data from a quantization unit (Q) to a variable length coding unit (VLC) illustrated in FIG. 1;

FIG. 3 is a block diagram of a variable length coding unit (VL) shown in FIG. 1;
FIG. 9 is a diagram illustrating VLC defined for a frequently-occurring run and level pair used for encoding the AC component in C).

FIG. 4 is a diagram illustrating codes used for encoding a pair of a run and a level other than that shown in FIG. 3; FIG. 4A shows a fixed length of the run; It is a figure which shows a code | symbol (FLC), (B) level (level)
1) is a diagram showing a fixed-length code (FLC) of l).

FIG. 5 is a diagram showing a first modification of the image decoding device of the present invention.

FIG. 6 is a diagram showing a second modified example of the image decoding device of the present invention.

FIG. 7 is a diagram showing a third modified example of the image decoding apparatus of the present invention.

FIG. 8 is a diagram illustrating a predecoder (Pre-VLD) and a variable length decoding unit (VL) in the image decoding apparatus according to the present invention.
FIG. 4D is a diagram showing an example of a form of connection with D), FIG. 4A is a diagram showing a form in which a bit stream itself to be processed is transferred, and FIG. FIG. 4 is a diagram illustrating a transfer mode.

FIG. 9 is a diagram showing a fourth modification of the image decoding apparatus of the present invention.

FIG. 10 is a block diagram illustrating a configuration of a conventional image decoding device.

FIG. 11 is a diagram illustrating another configuration example of the image decoding device illustrated in FIG. 10;

[Explanation of symbols]

100: image encoding device, 102: adder, 104: D
CT unit (DCT), 106... Quantization unit (Q), 108.
Variable length coding unit (VLC), 110 ... output buffer (B
UF), 112: inverse quantization unit (IQ), 114: inverse DC
T unit (IDCT), 116: adder, 118: frame memory (MEM), 120: motion compensation prediction unit (MC),
200: image decoding device, 202: input buffer (BU
F), 204, 244... Predecoder (Pre-VL)
D), 206, 212, 246, 248... Variable length decoding section (VLD), 208, 214, 228... Inverse quantization section (IQ), 210, 216, 230.
CT), 218, 220 ... changeover switch, 222 ...
Adder, 224 ... frame memory (MEM), 226
238: motion compensation prediction unit (MC), 232: memory, 2
34 interface (I / F), 236 bus, 2
40, 242: buffer (BUF), 900: image decoding device, 902: input buffer (BUF), 904: variable length decoding unit (VLD), 906: inverse quantization unit (I
Q), 908: inverse DCT unit (IDCT), 910: adder, 912: frame memory (MEM), 914: motion compensation prediction unit (MC), 916: memory, 918: interface (I / F), 920 ... bus

Claims (15)

[Claims] 1. An image decoding apparatus for decoding video data encoded into encoded data having a continuous variable length code sequence, comprising: a plurality of variable length decoding means for variable length decoding the variable length code. Decoding means; code range detecting means for detecting a range of each of the variable length codes included in the encoded data from the encoded data; and a predetermined unit from the encoded data based on the detected range. And coded data distribution means for sequentially extracting encoded data for each of the plurality of variable-length decoding means, and allocating the encoded data to any one of the plurality of variable-length decoding means. An image decoding device for performing variable-length decoding on each of the encoded data for each predetermined unit. 2. The coded data is obtained by performing variable length coding on a transform coefficient obtained by performing a predetermined transform coding for each predetermined block of each picture of video data. The encoded data distribution means, based on the encoded data,
Sequentially extracting the encoded data for each of the predetermined blocks,
Respectively allocating to any of the plurality of variable-length decoding means, wherein each of the variable-length decoding means performs variable-length decoding on the allocated encoded data for each of the predetermined blocks, 2. The image decoding apparatus according to claim 1, further comprising an inverse transform unit that inversely transforms and decodes the encoded data based on the predetermined transform encoding. 3. The transform coding method according to claim 1, wherein the discrete cosine transform (D
CT: Discrete Cosine Transform), wherein the coded data distribution means is:
The coded data for each DCT block is sequentially extracted and distributed to any one of the plurality of variable length decoding means.
The image decoding apparatus according to claim 2, wherein the encoded data for each block is variable-length decoded, and the inverse transform unit performs inverse DCT on the variable-length decoded encoded data to decode. 4. A code range detecting means for sequentially detecting the length of each of the variable length codes from the coded data, and detecting an EOB (end of block) code for each DCT block. Means for allocating encoded data for each DCT block from the encoded data based on the length of the sequentially detected variable length code and the detected EOB code. 4. The image decoding apparatus according to claim 3, wherein the image decoding apparatus sequentially extracts and distributes the extracted data to any one of the plurality of variable length decoding units. 5. A plurality of buffer means provided corresponding to said plurality of variable length decoding means and storing said coded data distributed to said plurality of variable length decoding means by said coded data distribution means. The variable-length decoding means for allocating each of the variable-length codes, which is the coded data for each of the predetermined units and whose range is detected by the code-range detecting means, 5. The image decoding apparatus according to claim 4, wherein the image is sequentially recorded in the buffer means provided corresponding to the image data. 6. The variable length decoding means for allocating a plurality of variable length codes which are the coded data for each of the predetermined units and whose range is detected by the code range detecting means. 5. The image decoding apparatus according to claim 4, wherein the image data is collectively and sequentially recorded in the buffer means provided corresponding to the decoding means. 7. A memory device for recording the coded data, wherein the coded data distribution unit stores address information in the memory unit of the extracted coded data to be distributed, and stores the coded data in the coded data. 5. The image decoding apparatus according to claim 4, wherein the image decoding apparatus outputs the variable length code to the variable length coding unit. 8. The encoded data is obtained by quantizing a transform coefficient obtained by performing a predetermined transform coding for each predetermined block of each picture of the video data and performing variable length coding. And further comprising an inverse quantization means for inversely quantizing the variable-length-decoded encoded data, wherein the inverse transform means converts the inverse-quantized encoded data to the predetermined transform code. 3. The image decoding apparatus according to claim 2, wherein decoding is performed by performing inverse conversion based on the conversion. 9. The image decoding apparatus according to claim 8, wherein a plurality of said inverse quantization means and said inverse transform means are provided respectively corresponding to said plurality of variable length decoding means. 10. An image decoding method for decoding video data encoded into encoded data having a sequence of continuous variable length codes, comprising: Detecting a range of the variable-length code, extracting coded data for each predetermined unit from the coded data based on the detected range, and extracting the coded data for each of the plurality of extracted predetermined units. On the other hand, an image decoding method for performing variable length decoding in parallel. 11. The coded data is coded data obtained by performing variable-length coding on transform coefficients obtained by performing predetermined transform coding for each predetermined block of each picture of video data. The extracting of the encoded data sequentially extracts encoded data of each of the predetermined blocks from the encoded data, and the variable length decoding performs the extraction of the encoded data of each of the plurality of extracted predetermined blocks. The image decoding method according to claim 10, wherein the inverse transform of the predetermined transform encoding is performed on the encoded data in parallel and on each of the variable-length-decoded encoded data. 12. The transform coding is a discrete cosine transform (DCT), and the extraction of the coded data is performed by using D
Coded data for each CT block are sequentially extracted, and the variable length decoding is performed by using the plurality of extracted DCTs.
Performs in parallel on the coded data for each block, and applies the inverse D to each of the coded data subjected to the variable length decoding.
The image decoding method according to claim 11, wherein CT is performed. 13. In the detection of the range of the variable length code, the length of each of the variable length codes is sequentially detected from the coded data, and the EOB (end / end) of each DCT block is detected.
Of blocks) code, and the extraction of the encoded data is performed based on the length of the sequentially detected variable length code and the detected EOB code,
The image decoding method according to claim 12, wherein encoded data for each DCT block is sequentially extracted from the encoded data. 14. The coded data obtained by quantizing a transform coefficient obtained by performing a predetermined transform coding for each predetermined block of each picture of the video data and performing variable length coding. And performing inverse quantization on each of the variable-length-decoded encoded data, and inversely transforming and decoding each of the inversely-quantized encoded data based on the predetermined transform encoding. The image decoding method according to claim 11, wherein the image is decoded. 15. The image decoding method according to claim 14, wherein said inverse quantization and said inverse transform are performed in parallel corresponding to said variable length decoding.