JPH11262002A - Device and method for analyzing data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously analyze plural streams without increasing the circuit scale by analyzing the plural streams with the use of a single analyzer by means of time division for each prescribed time and storing the analysis results for each stream. SOLUTION: Respective transport stream TS packets of a transport stream S10 in an input processor 15A are stored in a memory 10 for each packet identifying information PID. Memories M1-MN are arranged in a parser part 17 in accordance with the number of the stream ST1-STN to be analyzed, desired STK is read out from the memory 10 and analysis results till the previous time, which are stored in the memory MK, are loaded in the analyzer of the parser part 17 by a selector. After a prescribed time elapses, analysis is temporarily stopped, processings for saving the analysis results in the memory MK are successively repeated, and the streams ST1-STN are analyzed. The plural stream are analyzed by a single analyzer by time division so that plural analyzing circuits are not required, and at the same time, analysis is enabled.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[Table of Contents] The present invention will be described in the following order.

2. Description of the Related Art Prior Art (FIGS. 11 to 15) Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (1) Overall Configuration of Splicing Device (FIGS. 1 to 15) 3) (2) Configuration of input processor (FIGS. 4 to 6) (3) Configuration of parser section (FIGS. 7 and 8) (4) Operation and effect (5) Other embodiments (FIGS. 9 and 9) (Fig. 10) Effect of the invention

[0003]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data analyzing apparatus and a data analyzing method, and more particularly, to a data analyzing apparatus and a data analyzing method which are suitably applied to a splicing apparatus for switching and connecting video data in TS packets.

[0004]

2. Description of the Related Art In recent years, various compression coding systems have been proposed to reduce the amount of information of video and accompanying audio. A typical example is the ISO (Internationa
l MPEG2 (Moving) standardized by organizations such as the Organization for Standardization
There is a compression coding method called Picture Experts Group Phase 2). The MPEG2 system is standardized for transmitting video and audio, and is standardized for video and audio, respectively.

In recent years, a digital broadcasting system for compressing and encoding video and audio using the MPEG2 system and broadcasting it using terrestrial waves and satellite waves has been devised. In such a digital broadcasting system, coded video data and audio data are packetized for transmission at predetermined blocks, and the resulting packet sequence is transmitted (hereinafter, this packet sequence is transported). Each packet forming a transport stream is called a TS (Transport Stream) packet.)

The relationship between video data and audio data and TS packets will be described with reference to FIG. However, since the basic concept is the same for video and audio, only video data will be described here. As shown in FIGS. 11A and 11B, in the MPEG2 system, several pictures are defined as one GOP (Group Of Picture),
Video data is compression-encoded in P units. At this time, at least one of the pictures of the GOP is an I picture, the remaining pictures are P or B pictures, the I pictures are compression-coded by intra-frame coding, and the P pictures are I pictures or other P pictures.
Compression coding is performed by inter-frame predictive coding from a picture, and B-picture is compression-coded by bidirectional inter-frame predictive coding from preceding and succeeding pictures.

[0007] Encoded video data encoded in GOP units is generally called an elementary stream (ES) because it is a material element. As shown in FIGS. 11B and 11C, the coded video data is collected by a predetermined amount, and a PE is added by adding a header to the head of the coded video data.
It is packetized into S (Packetized Elementary Stream). Further, this PES packet is divided into 184 [bytes] as shown in FIGS. 11C and 11D, and is converted into a TS packet for transmission by adding a 4 [byte] header at the beginning. Is done. Thus, a packet generated from the video data in such a procedure is a TS packet.

The header structure of the PES packet indicates the start of the PES packet as shown in FIG.
24 [bit] packet start code, 8 [bit] stream ID indicating the type of stream data contained in the actual data portion of the PES packet (for example, type of video or audio, etc.), and the length of the following data 8 [bit] indicating the packet length of 16 [bit] indicating the length, code data indicating the value "10", the flag control unit storing various flag information, and the data length of the conditional coding unit PES header length and PTS (Presentation Time Stamp)
) And DTS (Decoding)
It is constituted by a variable-length conditional coding unit for storing time management information at the time of decoding called Time Stamp) or stuffing bytes for adjusting the data amount.

[0009] The header structure of the TS packet is as follows.
As shown in FIG. 13, 8 [bi] indicating the start of a TS packet
t] and an error indicator (error indicator) indicating the presence or absence of a bit error in the packet
And a unit start display section indicating whether or not the beginning of the PES packet exists in the TS packet, a transport packet priority section indicating the importance of the TS packet, and a payload section of the TS packet. A PID portion storing packet identification information PID indicating the type of stream data stored therein, a scramble control portion indicating whether or not the stream data stored in the payload portion is scrambled; And an adaptation field control unit indicating whether or not an adaptation field portion and a payload portion are present, and cyclic counter information indicating whether a TS packet having the same packet identification information PID is rejected on the way. A cyclic counter section to be stored and an adapter to store various control information Connexion composed of Manzanillo and Yong field unit.

The adaptation field section is
An adaptation field length indicating the length of the adaptation field portion, a discontinuity display portion indicating whether or not time information is reset in a TS packet of the same stream following this TS packet, and A random access display unit for indicating whether or not the packet is a random access entry point; a stream priority display unit for indicating whether or not an important part of the stream data is stored in the payload of the TS packet; A flag control unit for storing flag information relating to the coding unit;
ference) and OPCR (Origin
al Program Clock Reference) or a conditional coding section that stores information such as splice countdown indicating an index up to the data replacement point, and a stuffing byte section for adjusting the data amount. It is composed by

By the way, in data transmission using the MPEG2 system, data to be transmitted is transmitted as described above in TS.
Since the packets are converted into packets and transmitted, even if TS packets of other data are multiplexed, they can be handled and transmitted in the same manner. For this reason, in the digital broadcasting system, video data and audio data of each program are each compression-encoded by the MPEG2 system, and then these data are individually TS-packeted and multiplexed. A plurality of programs can be broadcast.

When a plurality of programs are multiplexed on one line, the receiving side extracts a TS packet storing video data and audio data of the program desired by the viewer from the transmitted TS packets. And decrypt it. Therefore, in the digital broadcasting system, PAT
(Program Association Table) and program information called PMT (Program Map Table)
S packets are formed, and these TS packets are also multiplexed and transmitted with TS packets relating to video and audio.

The program information PMT is information indicating, for each program, packet identification information PID of a TS packet in which video data and audio data constituting the program are stored. For example, the video of the program number "X" is packet identification information. P
The ID is “XV” and the voice is packet identification information PID is “X
"A". The program information PMT
Are generated for each program, so that there are as many as the number of programs multiplexed in one transport stream. The program information PAT is the program information PM generated for each program.
The packet identification information P of the TS packet in which T is stored
For example, a TS packet in which the program information PMT related to the program number “0” is stored and the packet identification information PID is “AA”, and the program information PMT related to the program number “1” is stored. The TS packet is information indicating that the packet identification information PID is “BB”. It should be noted that a predetermined packet identification information PID is added to the TS packet in which the program information PAT is stored.

When a transport stream in which a plurality of programs are multiplexed is received and a program desired by a viewer is displayed, first, the program information P
The TS packet storing the AT is received and the program information PA
T, and then, by referring to the program information PAT, a TS packet storing the program information PMT of the program desired by the viewer is received, and the program information PMT of the program is received.
Get. The receiving apparatus receives the TS packet storing the video data and audio data of the desired program by referring to the program information PMT, and obtains the video data and audio data constituting the program. This is subjected to decoding processing. Thus, even when a plurality of programs are multiplexed, the receiver can receive and display a program desired by the viewer.

[0015]

By the way, a transport stream multiplexed by the digital broadcasting system is received by a relay station, and video data of a predetermined program in the transport stream is, for example, advertisement video data (so-called advertisement video data). It is conceivable to insert a CM) and transmit again. Alternatively, it is conceivable that another video data is connected to video data of a desired program in a transport stream once generated in a transmission source broadcasting station and finally transmitted.

When performing such editing work, FIG.
As shown in FIG. 4, the original video data S1 and the video data S2 to be inserted or connected have to be switched and connected to generate video data S3 to be finally transmitted. Such video editing work is generally called splicing processing.

When transmitting a TS packetized transport stream, data transmission is controlled so that the STD (System Target Decorder) buffer provided at the input stage of the receiving apparatus does not break down.
If the first video data is simply switched to the second video data, the STD buffer may be broken. For example, as shown in FIG. 15, the first and the second are controlled so that the STD buffer does not fail.
When the third video data S3 is generated by simply switching the video data S1 and S2 at the time t1, the first
The time t2 from the last picture m of the video data S1 to the first picture n of the second video data S2 exceeds 1/30 second, and the first and second video data S1 before and after the connection point t1. , S2 becomes discontinuous.
If video data is extracted from the STD buffer at 1/30 second intervals in such a discontinuous state, the STD buffer causes an underflow.

Therefore, the splicing apparatus analyzes the video data to be spliced and simulates the behavior when the video data is input to the STD buffer based on the analysis result, thereby adjusting the output timing of the video data. Thus, the STD buffer of the receiving device is prevented from breaking down. In this case, the splicing device analyzes the video data to thereby analyze various parameters included in the video data, for example, a VBV (Video Buffering Verifier) delay, a repeat first field, a top field, and the like.
A parameter such as a first is extracted.

In this case, since the splicing apparatus performs splicing processing on a plurality of video data, it is necessary to analyze each of the plurality of video data streams. As a method of analyzing such a plurality of streams of video data, a method of providing a plurality of analyzers for analyzing video data and analyzing the plurality of video data simultaneously in parallel by a desired analyzer is used. Can be considered.

However, in the syntax of video data encoded according to the MPEG2 standard (rules of a data string), various data are stored in accordance with, for example, values of various flags. For this reason, the analyzer must analyze various video data in which data corresponding to various flag values is stored, and accordingly, a large circuit scale is required. Therefore, when a plurality of analyzers are connected in parallel as described above, there is a problem that the circuit scale of the entire analyzers cannot be avoided.

The present invention has been made in view of the above points, and has as its object to propose a data analysis apparatus and a data analysis method capable of analyzing a plurality of data simultaneously without increasing the circuit scale.

[0022]

According to the present invention, a plurality of streams each composed of packetized data are selected one by one at predetermined time intervals, and the selection is performed by the selection means. An analysis means for analyzing a plurality of streams in a time-division manner by analyzing the stream thus analyzed, and a storage means for storing, for each stream, an analysis result analyzed by the analysis means are provided.

Since a plurality of streams are analyzed in a time-division manner by using one analyzing means, the circuit scale can be reduced as compared with a case where a number of analyzing means corresponding to the number of streams to be analyzed are connected in parallel. Can be prevented from increasing.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Overall Structure of Splicing Device In FIG. 1, reference numeral 1 denotes a splicing device to which the present invention is applied as a whole, and a multi-program transport stream based on control information supplied from an external host computer 2. The splicing process is performed on the desired video data existing in S10 and S11. The splicing apparatus 1 is provided in a broadcasting station or a relay station of a digital broadcasting system, and performs splicing processing on video data that has already been converted into a transport stream.

Here, the principle of the splicing process performed in the splicing apparatus 1 will be briefly described. First, video data of three programs A, C, and E are multiplexed in the transport stream S10, and video data of three programs B, D, and F are multiplexed in the transport stream S11. It is assumed that the video data DB of the program _B is spliced with the video data DA of the program _A therein. When such transport streams S10 and S11 are input, the splicing apparatus 1 transmits the transport streams S10 and S11.
11 are arranged for each program based on the packet identification information PID. The packet identification information PID of each program is recognized by the program information PAT and the program information PMT.

[0027] At this time, as shown in FIG. 2 (A) and (B), the image data D _A of the program A and B, D _B is, STD buffer of each receiving apparatus is already controlled so as not to collapse Shall be. Thus when the splicing process to the video data D _B from the image data D _A at time t1 in a state, rather than simply switching to the video data D _B from the video data D _A, as shown in FIG. 2 (C) Then, for example, three blanking data B1 to B3 are inserted after the video data D _{A and} the stuffing data SF is inserted, so that the video data D _A and the video data D _B are connected before and after the connection point t1. The combined video data D _AB that is continuous is generated. Thus, if such combined video data D _AB is transmitted after being multiplexed with the video data of other programs C and E, even if the video data D _AB is taken out at 1/30 second intervals from the STD buffer in the receiving device, The STD buffer does not break down as in the prior art. In the case of this example, so that the blanking data for three sheets is displayed between the first picture n of the last picture m and the video data D _B of the video data D _A. Since the stuffing data SF is dummy data for time adjustment, it is discarded after being taken out of the STD buffer.

[0028] Here, for clarity of description, the image data D _A and D _B are described as if they were elementary stream, in practice, each image data D _A and D _B Transport Stream S1
0, since the data is multiplexed in S11, it is TS packetized data. Incidentally although each TS packet in the video data D _A and D _B can perform the splicing process in TS packet units if they are stored one by one, the byte amount of actually TS packet is 188 [by
te], one video data D _A and D _B is stored across a plurality of TS packets. Therefore, after all, in order to perform the splicing process, the process cannot be performed without returning to the state of the elementary stream. However, the video data D _A and D _B
Is completely returned to the elementary stream state, the processing becomes complicated because it must be returned to the TS packet again at the time of output. Therefore, in the splicing apparatus 1, the video data D _A composed of TS packets is used.
And it is adapted to convert the data format as if handled as if it were an elementary stream of D _B. Processing means for this data format conversion,
This is the input processing unit 3 shown in FIG.

Here, returning to FIG. 1, the description of the splicing apparatus 1 will be continued. As shown in FIG. 1, the splicing apparatus 1 is roughly divided into an input processing unit 3, a data analysis unit 4, a data processing unit 5, an output process 6, and a C as a control unit.
PU (Central Process Unite) 7, Command bus 8,
Data bus 9, memory 10, and interface unit 11
It is composed of

The CPU 7 controls the operation of each circuit block (3 to 6, 10) of the splicing apparatus 1. The CPU 7 receives a splicing command from the host computer 2 via the interface unit 11 and the command bus 8. Then, based on the splicing command, an operation command for each circuit block (3-6, 10) is generated, and this is given to each circuit block (3-6, 10) via the command data bus 8, thereby The splicing process instructed by the host computer 2 is performed. The CPU 7 operates based on an operation program stored in the memory 10 to control the operation of each of these circuit blocks. Incidentally, the operation program is externally downloaded to the memory 10 via the host computer 2.

In the splicing apparatus 1, each circuit block (3 to 7) is connected to the memory 1 via the data bus 9.
0 so that desired data can be written to the memory 10 and desired data can be read from the memory 10. The data bus 9 is provided with an arbitration function. Arbitration of the right to use the data bus 9 by the arbitration function prevents access to the memory 10 from colliding.

The input processing unit 3 is a circuit block for performing predetermined input processing on transport streams S10 and S11 supplied from the outside, and storing them in the memory 10. The input processing unit 3 includes input processors 15A and 15B and a PID lookup table 16
A, 16B, and transport streams S10, S11 supplied from the outside are received by the input processors 15A, 15B, respectively.

The input processor 15A converts each TS packet of the input transport stream S10 into a PI.
The memory 1 is referred to while referring to the D lookup table 16A.
0, the packet identification information PI
D for each T in the transport stream S10.
The S packet is written in the memory 10. At this time, the input processor 15A performs a predetermined data conversion process on each TS packet and records it so that it can be handled as if it were an elementary stream as described above.

The PID lookup table 16A stores address information for organizing and writing each TS packet for each packet identification information PID. The address information can be read using the packet identification information PID as a keyword. ing. As a result, the input processor 15A can obtain the write address for the memory 10 by accessing the PID look-up table 16A using the packet identification information PID as a keyword.

Note that the input processors 15B and P
The ID lookup table 16B has substantially the same configuration, and the input processor 15B writes each TS packet of the transport stream S11 into the memory 10 with reference to the PID lookup table 16B, thereby obtaining packet identification information. Each TS packet in the transport stream S11 is written in the memory 10 in an organized manner for each PID.

The data analysis unit 4, a TS packet in which the video data D _A and D _B to be spliced processing of each TS packet written in the memory 10 is stored, during the time of compression coding and packetized read the added various parameters, a circuit block for analyzing the generated code amount of video data D _a and D _B on the basis of the various parameters.

The data processing section 4 comprises a parser section 17 and a buffer / simulator section 18. Those parser unit 17 analyzes the TS packet in which the video data D _A and D _B to be spliced target by accessing the memory 10 is stored, to retrieve the various parameters that are added at the time of compression coding and packetized It is. The buffer-Shimiyureta unit 18, based on the analysis result of the analysis by the parser unit 17 analyzes the generated code amount in the STD buffer at the receiving apparatus when the image data D _A and D _B are input, the analysis results To CPU7
Notify The CPU 7 receives this analysis result, determines what data combining process should be performed to prevent the STD buffer from breaking down, and notifies the data processing unit 5 described below of the determination as a data combining command. By the way,
The analysis result output from the buffer / simulator section 18 and the content of the determination of the data combination by the CPU 7 are also supplied to a scheduler circuit 24 of the output processing section 6 described later.

The data processing unit 5 is a circuit block that receives a data combination command from the CPU 7 and actually connects the video data D _A and D _B to execute a splicing process. The data processing unit 5 includes a data connection circuit 1
9, a blanking generator 20 and a stuffing generator 21. The data connection circuit 19 receives a data connection command from the CPU 7 and
The video data D _A and D _B are processed by the splicing process to generate the combined video data D _AB by coupling it to read from the memory 10. At this time, if it is necessary to insert blanking data or stuffing data to prevent the STD buffer from breaking down, the data linking circuit 19 generates the blanking data generated by the blanking generator 20 and the stuffing generator 21. and static Zuph queuing data desired amount inserted into the connection point of the video data D _a and D _B.

[0039] The data connecting circuit 19, rather than reading all the video data D _A and D _B are summer and the target splicing process, as shown in FIG. 3 (A) ~ (C) , actually Only the video data D _A1 and D _B1 near the connection point required for the connection processing are read out, and the video data D _A1
And D _B1 and their video data D _A1 and D _B1
Blanking and stuffing data are inserted between _B1 to generate connected video data DA _{+ B} , which is stored in the memory 10 again in the form of a TS packet. By performing such a connection process, the combined video data _DAB can be easily generated by reading the video data in a desired order at the time of output as described later.

The output processing section 6 reads out and outputs a desired portion of the video data in the memory 10 and outputs the spliced combined video data D _AB and, for example, programs C and E which are not subjected to the spicing process. This is a circuit block for multiplexing video data and finally outputting it as a transport stream S _OUT . More specifically, the output processing unit 6 applies the video data D to the spliced video data as shown in FIG.
Reading the portion of the video data D _A2 of _A, followed by reading a portion of the coupling the video data D _{A + B,} followed by reading a portion of the video data D _B2 of the video data D _B, the spliced processed bond The video data D _AB is output. In parallel with this processing, the output processing section 6 reads out TS packets of the video data of the programs C and E to be multiplexed together with the spliced combined video data D _AB , and reads them out of the combined video data D _AB . By inserting at a predetermined timing between TS packets, a transport stream S _OUT in which the combined video data D _AB and the video data of other programs C and E are finally multiplexed is output. I do.

The output processing unit 6 specifically includes:
It is composed of a time stamp generator 22, an output processor 23, a scheduler circuit 24, and a PCR generator 25. Timestamp Rijienereta 22, the time stamp (time information PTS to the video data D _B1 and D _B2 connected after coupling point by Sutatsufuingu treatment, DTS and the reference time information PC
R, etc.). Essentially, for the video data D _A and D _B, unique time stamp so as not to collapse the STD buffer is added.
However, the time stamp is the video data D
Since those granted to each _A and D _B, not necessarily the time axis is coincident. For this reason, the time stamp may not be continuous before and after the connection point.
For this reason, the time stamp generator 22 converts the time stamp added up to the connection point into the video data D.
_A , and a time stamp that is continuous with the time stamp is added to the video data _DB1 and _DB2 .

The scheduler circuit 24 estimates the generated code amount of the spliced data based on the analysis result output from the buffer / simulator 18 and the content of the data combination judgment by the CPU 7, and based on the estimation result, the memory 10 Video data D _A2 , D stored in
Reads the TS packet of _{A + B} and D _B2 are to Sukeji Yu ring output timing to output. If the scheduler circuit 24 also outputs video data of other programs C and E that have not been subjected to the stuffing process, it also schedules the output timing when outputting these video data. Then, the scheduling circuit 24 outputs the scheduling result to the output processor 23 as a scheduling list.

The scheduling list includes:
Entry information for specifying the TS packet to be output and its T
It consists of output time information indicating the output timing of the S packet, and these are arranged in a list. Incidentally, since most of the TS packets are output as they are, the scheduler circuit 24 sets the output time to the time at the time of input (that is, the system time clock STC added at the time of input) in order to simplify the processing. Value). However, of the TS packets that have undergone the splicing process, the TS packets after the connection point are assumed to have been input to the splicing apparatus 1 following the TS packets before the connection point, and added at the time of input based on the assumption. The value of the system time clock STC which would have been calculated is calculated, and the output time is designated using the calculated value.

The output processor 23 sequentially reads out the TS packets of the spliced video data D _AB and the video data of the other programs C and E based on the scheduling list output from the scheduling circuit 24. This is defined as a transport stream S _OUT '
Output to the CR regenerator 25.

The PCR regenerator 23 is a circuit block for re-adding the reference time information PCR added to the TS packet in the transport stream S _OUT 'so as to be continuous. Originally, if a TS packet is output based on the scheduling list of the scheduling circuit 24, the reference time information PCR in the transport stream S _OUT ′ should be continuous. However, when the output processor 23 is operated by an external operation clock, the timing at which the TS packet is actually output to the scheduling list may be shifted, and the reference time information PCR may not be continuous. . Therefore, in the splicing apparatus 1, the transport stream S _OUT ′ is generated by the PCR regenerator 25.
Is corrected. The PCR regenerator 25 stores the reference time information P currently added to the transport stream S _OUT '.
CR is PCR _old , the time to be output by scheduling is STC _ideal , the time actually output is ST
If C _real is given by

[0046]

(Equation 1)

The value of PCR _new shown in FIG.
Add it again as R. Thus, the transport stream S _OUT to which the reference time information PCR is added again is finally output from the splicing apparatus 1.

(2) Configuration of Input Processor Next, the configuration of the input processors 15A and 15B will be described. However, since the input processors 15A and 15B have the same configuration, only the input processor 15A will be described here. As shown in FIG. 4, the input processor 15A comprises a PID detection circuit 30 and a format conversion circuit 31, and converts the supplied transport stream S10 into a PID detection circuit 30.
And a format conversion circuit 31.

When the transport stream S10 is input, the PID detection circuit 30 detects the packet identification information PID stored in each TS packet of the transport stream S10, and outputs this to the lookup table 16A. . PID Look Up Table 1
6A generates address information S _ADS based on the supplied packet identification information PID and outputs it to the format conversion circuit 31.

That is, the PID lookup table 1
6A, when the packet identification information PID is input, generates a head address for storing the TS packet storing the packet identification information PID in the memory 10,
Thereafter, the address information S _ADS is incremented each time the packet identification information PID is given.

The format conversion circuit 31 stores each TS packet at an address position indicated by the supplied address information S _ADS while converting each TS packet of the transport stream S10 into a predetermined data format. As described above, the format conversion circuit 31 arranges each TS packet of the transport stream S10 for each packet identification information PID and stores it in a predetermined area of the memory 10.

For example, as shown in FIG. 5, the transport stream S10 is generated by multiplexing the video data of three programs A, C, and E. TS packet is input processor 1
5A is randomly input. In this case, as shown in FIG. 6, the input processor 15A sends the address information S _ADS supplied from the PID lookup table 16A.
, The TS packets of the program A are sequentially stored in the first area F1, the TS packets of the program C are sequentially stored in the second area F2, and the TS packets of the program E are sequentially stored in the third area F3. It is made to go.

(3) Configuration of the Parser Unit Next, the configuration of the parser unit 17 is shown in FIG. Here, there are N streams to be analyzed, and the TS packets of those streams have PIDs as packet identification information PIDs.
= “1”, “2”,..., “N” are added. The parser unit 17 inputs a control signal S40 supplied from the CPU 7 via the data bus 9 for selecting a stream to be analyzed to the address generation circuit 40 and the selector 41. The address generation circuit 40 generates address data S41 based on the supplied control signal S40, and supplies the generated address data S41 to the memory 10 via the data bus 9, thereby obtaining the stream ST to which the desired packet identification information PID is added. Is read. On the other hand, the selector 41 switches its connection state in accordance with the supplied control signal S40.

First, the address generation circuit 40 supplies the stream ST1 having the packet identification information PID of "1" to the memory 1 by supplying the address data S41 to the memory 10.
0 is read out and input to the analyzer 42. At the same time, the selector 41 switches the connection state to the memory M1. In this state, the analyzer 42 analyzes the stream ST1 to extract parameter information such as a VBV delay, a repeat first field, a top field first, and the like, and also obtains values such as flags included in the stream ST1. (Hereinafter referred to as internal state information). After analyzing the stream ST1 for a predetermined time, the analyzer 42 temporarily stops its operation,
The analysis result including the parameter information and the internal state information obtained so far is saved in the memory M1.

Subsequently, the address generation circuit 40 supplies the address data S41 to the memory 10 and outputs the packet identification information P.
The stream ST2 having the ID “2” is read from the memory 10 and input to the analyzer 42. At the same time, the selector 41 switches the connection state to the memory M2.
In this state, the analyzer 42 extracts the above-mentioned parameter information and internal state information by analyzing the stream ST2. After analyzing the stream ST2 for a predetermined time, the analyzer 42 temporarily stops its operation, and stores the analysis result up to that time in the memory M2. Thereafter, the analyzer 42 performs the above-described processing at predetermined timings in a similar manner, so that the analyzer 42 performs the time-sharing on the streams ST1 to S1.
Analyze the TN.

When it is time to analyze the stream ST1 whose packet identification information PID is "1" again, the address generation circuit 40 stores the stream ST1 in the memory 10
And input it to the analyzer 42. At the same time, the selector 41 switches the connection state to the memory M1. In this state, the analyzer 42 loads the analysis result up to the previous time from the memory 1 and analyzes the stream ST1 from the continuation to extract the parameter information and the internal state information. The analyzer 42 temporarily stops its operation after a predetermined time elapses, and saves the analysis result including the parameter information and the internal state information obtained so far to the memory M1.

By repeating such processing sequentially, the analyzer 42 makes time-division streams ST1 to STN.
Are analyzed, and when all the analysis is finally completed, the analysis results SR1 to SRN obtained for each packet identification information PID are obtained.
Is output to the buffer / simulator section 18.

The procedure for analyzing the stream ST will be described with reference to the flowchart shown in FIG. First step S
In step SP2 entered from P1, the parser unit 17
Performs initialization by setting the stream number K to “1”. In step SP3, the parser unit 17 determines whether or not the stream number K has reached the number of streams N. As a result, if it is determined that the stream number K matches the number of streams N, the process proceeds to step SP4. If it is determined that they do not match, the process proceeds to step SP5.

In step SP5, the parser unit 17
Is a stream ST whose packet identification information PID is “K”.
K is read from the memory 10 and input to the analyzer 42, and the connection state of the selector 41 is switched to the memory MK side. Next, in step SP6, the parser unit 1
7 is an analyzer 42 for analyzing the analysis results from the memory MK to the previous time.
To load. In step SP7, the parser unit 17
Restarts the operation of the analyzer 42 and analyzes the stream STK from the previous continuation. In step SP8, the parser unit 17 suspends the operation of the analyzer 42 after a predetermined time has elapsed. In step SP9, the parser unit 17
Saves the analysis result including the analyzed parameter information and internal state information in the memory MK.

In step SP10, the parser unit 17
Adds “1” to the stream number K and increments the stream number K. When this process ends, the process returns to step SP3 to repeat the operation. By the way, in step SP4, the parser unit 17
It is determined whether or not all the analyzes from T1 to STN have been completed. As a result, if it is determined that all the analyzes have not been completed, the process returns to step SP2 to repeat the operation, and it is determined that all the analysis has been completed. Moves to step SP11 and ends the process.

(4) Operation and Effect In the above configuration, the input processor 15A
Each TS packet of the transport stream S10 is arranged for each packet identification information PID and stored in the memory 10. The parser unit 17 analyzes the streams ST1 to S
The memories M1 to MN are provided according to the number of TNs,
When analyzing a desired stream STK among T1 to STN, the stream STK whose packet identification information PID is “K” is read from the memory 10 and the connection state of the selector 41 is switched to the memory MK side, and the memory MK is switched to the memory MK side. The stored analysis results up to the previous time are analyzed by the analyzer 42.
To load.

In this state, the parser 17 operates the analyzer 42 to analyze the stream STK from the continuation of the previous time. After a predetermined time has elapsed, the parser unit 17
2 is temporarily stopped, and the analysis result analyzed so far is saved in the memory MK. The parser unit 17 repeats such processing sequentially to form the streams ST1 to ST
Analyze TN.

As described above, a plurality of streams ST1 to STN are analyzed in a time-division manner using one analyzer 42, so that a number of analyzers corresponding to the number of streams to be analyzed are connected in parallel. As described above, it is possible to avoid an increase in circuit scale.

According to the above configuration, a plurality of streams ST1 to STN are analyzed in a time-division manner by using one analyzer 42, so that the number of analyzers corresponding to the number of streams to be analyzed is parallelized. Can be prevented from increasing in circuit size as compared with the case of connecting to a plurality of streams ST1 to S1 at the same time without increasing the circuit size.
The TN can be analyzed.

(5) Other Embodiments In the above embodiment, the address generation circuit 4
The address data S41 is generated by giving the address data S41 to the memory 10 using the address data S4.
The case where the stream ST of the packet identification information PID based on No. 1 is read has been described. However, the present invention is not limited to this. For example, as shown in FIG. The selector 51 is connected to the preceding stage of the device 42, and the stream ST1
To STN are input in parallel, and the connection state of the selector 51 is changed based on the supplied control signal S40.
The same effect as in the case described above can be obtained even when the desired stream ST is input to the analyzer 42 by switching in conjunction with the selector 41 connected to the memories M1 to MN.

In the above-described embodiment, the memories M1 to M1 are set in accordance with the number of streams ST1 to STN to be analyzed.
Although the MN is provided and the analysis result of each of the streams ST1 to STN is stored in the corresponding memory M1 to MN, the present invention is not limited to this. For example, the same reference numerals are given to portions corresponding to FIG. As shown in FIG.
The analysis results of the streams ST1 to STN are stored in one memory 5
6 and the address generation circuit 57
By performing address management based on the address data S50 generated by the above, the same effect as in the above case can be obtained.

In the above embodiment, the case where the analyzer 42 is constituted by hardware has been described.
The present invention is not limited to this. For example, a CPU or a ROM (Read O
nlyMemory) and may be configured by software.

Further, in the above-described embodiment, a case has been described in which a plurality of streams ST1 to STN are analyzed. However, the present invention is not limited to this, and one transport stream is defined as a transport stream, a packetized stream. Even when the elementary stream and the elementary stream are analyzed in a time-division manner in each layer, the same effect as in the above case can be obtained.

[0069]

As described above, according to the present invention, a plurality of streams are analyzed in a time-division manner using one analyzing means, so that the number of analyzing means corresponding to the number of streams to be analyzed is increased. As compared with the case of connecting in parallel, it is possible to avoid an increase in circuit scale, and therefore, it is possible to analyze a plurality of streams at the same time without increasing the circuit scale.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a splicing device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram for describing a splicing process;

FIG. 3 is a schematic diagram for describing a splicing process;

FIG. 4 is a block diagram showing a configuration of an input processor.

FIG. 5 is a schematic diagram illustrating a structure of a transport stream.

FIG. 6 is a schematic diagram illustrating a state where a transport stream is stored in a memory.

FIG. 7 is a block diagram showing a configuration of a parser unit.

FIG. 8 is a flowchart showing a procedure of analyzing a stream.

FIG. 9 is a block diagram showing a parser unit according to another embodiment.

FIG. 10 is a block diagram showing a parser unit according to another embodiment.

FIG. 11 is a schematic diagram used for describing video data and TS packets.

FIG. 12 is a schematic diagram showing the structure of a PES packet.

FIG. 13 is a schematic diagram showing the structure of a TS packet.

FIG. 14 is a schematic diagram used to explain the concept of the splicing process.

FIG. 15 is a schematic diagram for explaining a problem of a conventional splicing process.

[Explanation of symbols]

1 ... splicing device, 3 ... input processing unit, 4 ...
Data analysis unit, 5 ... Data processing unit, 6 ... Output processing unit, 7 ... CPU, 8 ... Command bus, 9 ... Data bus, 10 ... Memory, 11 ... Interface unit,
15A, 15B ... Input processor, 16A, 1
6B: PID look-up table, 17: Parser section, 18: Buffer simulator section.

Claims (10)

[Claims] 1. A selecting means for selecting a plurality of streams each consisting of packetized data one by one at predetermined time intervals, and analyzing the streams selected by the selecting means to convert the plurality of streams. A data analysis device, comprising: analysis means for performing time-division analysis; and storage means for storing, for each stream, an analysis result analyzed by the analysis means. 2. The data according to claim 1, wherein said analysis means reads out the analysis result stored in said storage means as needed, and analyzes said stream based on said analysis result. Analysis device. 3. The selection means generates an address at which the stream to be selected is stored in an external stream storage means, and based on the generated address, divides the plurality of streams one by one at predetermined time intervals. 2. The data analysis device according to claim 1, wherein the data is selectively read. 4. The storage means is provided corresponding to the plurality of streams, and includes a plurality of storage areas for storing the analysis result, and a storage area among the plurality of storage areas corresponding to the selection means. 2. The data analysis device according to claim 1, further comprising a storage area selection unit that selects a desired storage area. 5. The storage area selecting means generates an address at which the stream to be analyzed is stored in the storage area, and gives the address to the storage area, thereby providing a desired one of the plurality of storage areas. The data analysis apparatus according to claim 4, wherein the storage area is selected. 6. A plurality of streams each consisting of packetized data are selected one by one at predetermined time intervals, and the selected streams are analyzed, so that the plurality of streams are analyzed in a time-sharing manner and analyzed. A data analysis method, wherein an analysis result is stored in a predetermined storage unit for each stream. 7. The data analysis method according to claim 6, wherein the analysis result stored in the storage means is read out as needed, and the stream is analyzed based on the analysis result. 8. An external stream storage means for generating an address at which the stream to be selected is stored, and selecting and reading out the plurality of streams one by one at predetermined time intervals based on the generated address. 7. The data analysis method according to claim 6, wherein: 9. A method of selecting a desired storage area from the plurality of storage areas provided corresponding to the plurality of streams so as to correspond to selecting a plurality of streams one by one. The data analysis method according to claim 6. 10. A desired storage area is selected from the plurality of storage areas by generating an address at which the stream to be analyzed is stored in the storage area and giving the address to the storage area. The data analysis method according to claim 9, wherein: