JPH11345176A - Device and method for controlling bus, board and data reception equipment using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate processing at debugging or error occurrence. SOLUTION: A bus control part 137 has a peripheral component interconnect(PCI) controller 150, provided with a FIFO memory 151 for supplying data DT supplied from a filtering circuit 135 to a PCI bus 105 and a register 152 for holding data related to that operation. Corresponding to the setting of data in a register 157, access to the control register 152 can be selectively performed from the side of the PCI bus 105 or from the side of an external hardware (control data generating section 154). For the access to the register 152, high-frequency access is performed from the side of the external hardware, and low-frequency access is performed from the side of the PCI bus 105. Access can be made from the side of the PCI bus 105 as well and at debugging or error occurrence, the register 152 is accessed from the side of the PCI bus 105, so that conditions can be comprehended or setting can be changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control device and a bus control method for interfacing with a bus in a computer, for example, and a board and a data receiving device using the same. In detail, the register that holds the data related to the operation of the device connected to the bus can be accessed not only from the external hardware side but also from the bus side, so that processing at the time of debugging or error occurrence is easy. The present invention relates to a bus control device and the like.

[0002]

2. Description of the Related Art Hitherto, it has been proposed to transfer data such as programs and files received by a receiver to a personal computer for use. In this case, a bus in the computer, for example, a PCI (Peripheral Component I
A reception board is connected to the nterconnect) bus, and the above-described reception data is supplied to the PCI bus through the reception board.

Here, the receiving board has a bus control device for interfacing with a PCI bus. The bus control device includes a register for holding data relating to the operation of a bus controller connected to the PCI bus. have. The register includes, for example, a FIFO that exists in the bus controller and supplies received data to the PCI bus.
(First-in first-out) Data related to the operation of the memory is held.

[0004]

Conventionally, the setting of data in the above-described register is usually performed from external hardware such as an external microcomputer. For this reason, when the external hardware does not operate normally, the PCI side cannot grasp the situation and cannot change the setting. For this reason, there is a problem that it takes time to study at the time of debugging, and that recovery from an error occurrence becomes complicated.

Accordingly, an object of the present invention is to provide a bus control device or the like which facilitates processing at the time of debugging or when an error occurs.

[0006]

A bus control device according to the present invention comprises a device connected to a bus, a register for holding data relating to the operation of the device, and a first device for accessing the register from the bus side. , A second access path for accessing the register from the external hardware side, and a selecting means for selecting one of the first and second access paths from the bus side.

This bus control device is applied to, for example, a receiving board connected to a bus in a computer. The register holds data related to the operation of the device connected to the bus. For example, data related to the operation of the FIFO memory for supplying the received data to the bus is held. The access to this register can be made from the external hardware side or from the bus side. This access route is selected from the bus side. For example, among the accesses to the registers, the access paths are switched such that the frequent access is performed from the external hardware side and the infrequent access is performed from the bus side.

As described above, the register can be accessed not only from the external hardware side but also from the bus side. For example, when the external hardware does not operate normally, the status can be grasped from the bus side. However, the setting can be changed, and processing at the time of debugging or when an error occurs becomes easy.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a configuration of a digital broadcast receiving system 100 as an embodiment. The receiving system 100 includes, for example, an antenna 101 for receiving a digital broadcast signal from a broadcast satellite (not shown),
The digital broadcast signal received by the antenna 101 is subjected to reception processing, and a video signal SV of a desired channel is output.
And a receiver 102 for obtaining an audio signal SA, a computer (for example, a personal computer) 103,
MPEG2 (Moving Picture Experts Group 2) corresponding to a broadcast signal of a predetermined RF channel from the receiver 102
Computer 1 from transport stream TS
The receiving board 104 extracts data (program data, file data) according to the receiving instruction from the computer 03 and transfers the data to the computer 103. The receiving board 104 is connected to a bus in the computer 103, for example, a PCI bus 105.

The receiver 102 includes a microcomputer, and includes a controller 111 for controlling the entire operation and a plurality of RF signals received by the antenna 101.
And a tuner 113 for selecting a broadcast signal of a predetermined RF channel from the digital broadcast signals of the channel and outputting digital modulation data corresponding to the broadcast signal of the predetermined RF channel. The tuning operation of the tuner 113 is controlled by the controller 111 based on the operation of the key operation unit 112 by the user.

The receiver 102 demodulates digital modulated data output from the tuner 113 and demodulates the data. The ECC (Error Correction) performs error correction on the output data of the demodulator 114. C
ode) A decoder 115 and a descrambling process for the output data of the decoder 115 are performed so that the MPEG data corresponding to the selected predetermined RF channel broadcast signal is output.
Descrambler 1 for obtaining two transport streams (data obtained by time-division multiplexing of fixed-length packets such as video data, audio data, and service data) TS
16.

The receiver 102 includes a descrambler 1
The video data stream and the audio data packet of the program number (channel) designated by the user's operation of the key operation unit 112 are separated from the transport stream TS output from the video stream TS, and the video data stream composed of those packets is separated. Demultiplexer 11 for outputting VDS and audio data stream ADS
And a video processing unit 1 for performing a data decompression process or the like on the video data stream VDS to obtain a video signal SV.
18 and an output terminal 119 for outputting the video signal SV.
And an audio processing unit 120 that obtains an audio signal SA by performing data decompression processing or the like on the audio data stream ADS, and an output terminal 121 that outputs the audio signal SA.

Next, the operation of the receiver 102 shown in FIG. 1 will be described. Digital television broadcast signals of a plurality of RF channels received by the antenna 101 are supplied to the tuner 113, a broadcast signal of a predetermined RF channel is selected, and digital modulated data corresponding to the broadcast signal is output from the tuner 113. The demodulator 114 performs demodulation processing on the digital modulation data output from the tuner 113, and performs error correction processing on the output data of the demodulator 114 with the ECC decoder 115. The descrambling process is performed on the output data by the descrambler 116 to obtain the MPEG2 transport stream TS corresponding to the above-described broadcast signal of the predetermined RF channel.

The transport stream TS is supplied to a demultiplexer 117, where video data and audio data packets of a program number (channel) designated by a user operation are separated, and a video data stream composed of those packets is separated. VDS and audio data stream ADS are obtained. Then, the video processing section 11 performs processing on the video data stream VDS.
In step 8, a process such as data expansion is performed to generate a video signal SV, and the video signal SV is output to the output terminal 119. Further, the audio data stream ADS is subjected to a process such as data decompression by the audio processing unit 120 to generate an audio signal SA, and the audio signal SA is output to the output terminal 121.

FIG. 2 shows the configuration of the receiving board 104.

The receiving board 104 has a CPU (central processing unit) as a controller for controlling the entire operation.
nit) 131 and a connector 132 to which the MPEG2 transport stream TS from the receiver 102 is supplied.
And a demultiplexer 133 for separating a data packet of a program number (channel) in accordance with a reception instruction from the computer 103 from the transport stream TS and outputting a data stream DS composed of the packets. RAM 1 as a buffer memory for temporarily storing stream DS
34.

The receiving board 104 extracts, from the data stream DS output from the demultiplexer 133, program data (data such as programs and files) DT according to the receiving command from the computer 103, and extracts the data DT. A filtering circuit 135 that converts the DT into an IP (Internet Protocol) packet and outputs the packet;
A connector 136 for connecting to the PCI bus 105 of the computer 103; a bus control unit 137 for interfacing with the PCI bus 105;
(Random access memory) 138.

FIG. 3 shows a main configuration of the computer 103. The computer 103 includes a PCI bus 105
And a connector 141 for connecting the receiving board 104 and a driver 1 connected to the PCI bus 105.
42, the buffer memory 143, and the application 1
44. The application 144 is software that runs on the computer 103, has a user interface, and can be directly operated by a user.

Next, the driver 142 is transmitted from the application 144 of the computer 103 by a user operation.
Will be described in the case where a receiving instruction RCM for data of a predetermined program (data of a program, a file, or the like) is supplied to the CPU.

In this case, the reception command RCM is the driver 1
From 42, the signal is supplied to the CPU 131 of the receiving board 104 via the PCI bus 105, the connector 141, the connector 136 of the receiving board 104, and the bus control unit 137. Then, the separation operation of the demultiplexer 133 is controlled by the CPU 131 so as to separate the packet of the program number (channel) according to the reception command RCM.

Here, the packet separation operation in the demultiplexer 133 is performed by a PID (Packet Ide) included in a header (TS header) arranged at the head of the TS packet.
ntication: packet identification information).
For example, when the transport stream TS as shown in FIG. 4A is supplied to the demultiplexer 133 and the PID of the packet to be separated by the reception command RCM is PID # 1, the demultiplexer 133
3, only the packets with PID = PID # 1 are separated, so that a data stream DS relating to the separated packets is obtained as shown in FIG. 4B.

The data stream DS obtained by the demultiplexer 133 is temporarily stored in a RAM 134 as a buffer memory. And this RAM 134
The read data stream DS is supplied to the filtering circuit 135 via the demultiplexer 133. The filtering circuit 135 is controlled by the CPU 131 so as to extract program data (data of programs, files, etc.) DT in accordance with the reception command RCM.

Here, the extraction operation is performed using a program ID added to identify a program.
For example, when the data stream DS as shown in FIG. 4B is supplied to the filtering circuit 135 and the program to be extracted by the reception command RCM is the program A, the filtering circuit 135 extracts only the program A. Therefore, as shown in FIG.
T is obtained.

The filtering circuit 135 further includes:
The data DT according to the reception command RCM extracted as described above is converted into an IP packet as shown in FIG. 4D. The data DT extracted by the filtering circuit 135 is transmitted in the form of an IP packet to the bus control unit 13.
7, connector 136, connector 1 of computer 103
41, the computer 103 via the PCI bus 105
Is temporarily transferred to the buffer memory 143.

The data DT read from the buffer memory 143 is supplied to the application 144 via the driver 142.
In step 4, programs and files are reconfigured. here,
The data DT is transmitted from the driver 142 to the application 14
In the process of being supplied to the IP packet 4, although not shown, a UDP (User Datagram Protocol) packet (FIG.
E) and further from this UDP packet to the application layer (FIG. 4F). The application 144 includes data DT in the form of an application layer.
Is supplied, and the programs and files are reconfigured as shown in FIG. 4G.

Next, the bus control unit 13 of the receiving board 104
7 will be described. FIG. 5 shows a main configuration of the bus control unit 137.

The bus control unit 137 converts the data DT supplied from the filtering circuit 135 (see FIG. 2) into a PCI
A PCI controller 15 including a FIFO memory 151 for supplying to the bus 105 and a control register 152 for holding data related to the operation of the FIFO memory 151
It has 0. The control register 152 includes data for controlling ON / OFF of data transfer from the FIFO memory 151 to the PCI bus 105, threshold data indicating how much data is stored in the FIFO memory 151, and data to be output. Address data in the buffer memory 143 (see FIG. 3) of the computer 103 to which the output data is transferred, data indicating the operation status (status) of the FIFO memory 151, and the like.

The bus control unit 137 should store the control register 152 in the access path 153 including a data line and a control line for accessing the control register 152 from the PCI bus 105 via the PCI controller, and the control register 152. A control data generator 154 for generating data, and an access path 155 including a data line and a control line for accessing the control register 152 from the control data generator 154 are provided.

The bus control unit 137 includes a switch circuit 156 for switching the access path 153 and the access path 155, and a select register 157 for holding data for controlling the operation of the switch circuit 156.
And The access path 153 and the access path 155 described above correspond to a
The movable terminal of the switch circuit 156 is connected to the control register 152.
The data setting for the select register 157 is P
This is performed via the PCI controller 150 from the CI bus 105 side.

In the bus control section 137 as shown in FIG. 5, of the accesses to the control register 152, the access with low frequency is performed from the PCI bus 105 side. For example, when the power of the computer 103 is turned on,
The data of the select register 157 is set from the PCI bus 105 so that the switch circuit 156 is connected to the a side. As a result, the switch circuit 156 is connected to the a side, and the control register 152 is connected from the PCI bus 105 side.
Can be accessed. Then, in this state, the control register 152 is accessed from the PCI bus 105 side, and the on / off data for data transfer is set to the on state, and the threshold data is also set.

Of the accesses to the control register 152, the most frequent access is to the external hardware side,
That is, the control is performed from the control data generator 154. For example,
As described above, the control register 1 is sent from the PCI bus 105 side.
After the ON / OFF data of 52 is set to the ON state, the data of the select register 157 is set from the PCI bus 105 so that the switch circuit 156 is connected to the b side. As a result, the switching circuit 156
, So that the control register 152 can access the control register 152.

In this case, the destination address data DA is transmitted from the filtering circuit 135 to the control data generator 154.
Each time D is supplied, the address data DAD of the transfer destination is set in the control register 152 by the access of the control data generator 154. Although not described above, the control register 152 also stores data that is set to “0” every time transfer of data of a certain size ends. Therefore, this data is also set to “1” by the access of the control data generator 154 each time the transfer destination address data DAD is set in the control register 152 as described above.

Next, in the computer 103, the driver 1
The control of the buffer memory 143 secured by 42 will be described.

In this embodiment, the buffer memory 1
43 is controlled by being divided into a plurality of sectors as shown in FIG. As described above, the IP packets relating to the data DT transferred from the filtering circuit 135 of the receiving board 104 via the bus control unit 137 are sequentially written to the respective sectors of the buffer memory 143, and thereafter read. Even if not described above, the FI
The FO memory 151 outputs each IP packet related to the data DT with the address data of the transfer destination added thereto. The transfer destination address data is stored in the computer 10
3 indicates the sector address of the buffer memory 143.

The size of the sector is equal to or larger than the maximum value of the packet size of the IP packet. In FIG. 6, a hatched portion of each sector indicates an area in which an IP packet has been written, and the remaining blank area indicates an empty area. Driver 14 for receiving board 104 and computer 103
No. 2 updates the write pointer WPT and the read pointer RPT not in the actual packet size of the IP packet but in units of the sector size. If the sector size is set to a well-divided size such as 1 kbyte, the data amount required for controlling the write pointer and the read pointer, calculating the buffer occupancy, etc. (even if the packet size is an odd value) Bit number), and the scale of hardware and software is small.

The receiving board 104 is connected to the computer 10
The writing to the buffer memory 143 is controlled so that the third buffer memory 143 does not overflow. That is, the reception board 104 stops the transfer of the IP packet as the data DT when the value of the write pointer WPT is one sector before the value of the read pointer RPT, as shown in FIG. 7B. This state is buffer memory 1
43 is a full state, and conversely, as shown in FIG.
When the value of the read pointer is equal to the value of the write pointer, the buffer is empty. Thus, when the buffer memory 143 is in the full state, the receiving board 1
04, the transfer of the IP packet to the buffer memory 143 is stopped, but the receiving board 104 is connected to the RAM 134 by the demultiplexer 133,
There is no problem because the AM 134 functions as a buffer memory.

Thus, when the driver 142 detects the presence or absence of data, it is possible to clearly determine whether the buffer memory 143 is full or empty. Note that when the receiving board 104 performs control to set a full state when the value of the write pointer WPT in the buffer memory 143 matches the value of the read pointer RPT, the driver 1
At 42, it cannot be easily determined whether the state is a full state or an empty state.

As described above, in the present embodiment, by connecting the switch circuit 156 to the side a,
The control register 152 of the PCI controller 150 can be accessed from the CI bus 105 side. Therefore, for example, at the time of debugging or occurrence of an error, the switch circuit 156 is connected to the a side so that the control register 152 can be accessed from the PCI bus 105 side.
By accessing the control register 152 from the CI bus 105 side, the situation can be grasped and the setting can be changed, and processing at the time of debugging or occurrence of an error can be easily performed.

Further, the buffer memory 143 of the computer 103 is divided into a plurality of sectors having a sector size larger than the maximum value of the packet size of the IP packet, and the IP packet related to the data DT is written and read to and from each sector. The write pointer WPT and the read pointer RPT are updated in units of a sector size.

Therefore, if the sector size is set to a good size for division, even if the packet size is an odd value, it is necessary for controlling the write pointer WPT and the read pointer RPT, calculating the buffer occupancy, and the like. The amount of data (the number of bits) is reduced, the scale of hardware and software can be reduced, and packet data processing can be performed efficiently.

Even if an error occurs in which the data size of the header of the IP packet is different from the actual transmission size, as long as the error is updated in units of the sector size,
The error does not propagate to the next packet on the writing side. Since the reading side cannot have a packet exceeding the sector size, the error packet can be easily detected and the next correct packet can be easily detected.

For example, in FIG. 8A, an IP packet is written in sector 1 and an IP packet to be written in the next sector is written.
This shows a state where the packet is an error packet and the error packet has been written over sectors 2 and 3. In this case, the IP packet to be written to the next sector is written from the beginning of the sector 3 as shown in FIG. Therefore, the error does not propagate to the next packet on the writing side.

In the above-described embodiment, the present invention is applied to the digital broadcast receiving system 100. However, the present invention relates to a board connected to a computer bus, and further to a data having such a receiving board. Of course, it can be similarly applied to the receiver.

[0045]

According to the present invention, the register for holding the data relating to the operation of the device connected to the bus can be accessed not only from the external hardware but also from the bus. There is an advantage that processing when an error occurs or the like can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital broadcast receiving system as an embodiment.

FIG. 2 is a block diagram illustrating a configuration of a receiving board included in the digital broadcast receiving system.

FIG. 3 is a block diagram showing a main configuration of a computer constituting the digital broadcast receiving system.

FIG. 4 is a diagram for explaining an operation of a receiving board and the like when a receiving command is issued from a computer.

FIG. 5 is a block diagram illustrating a main configuration of a bus control unit included in the receiving board.

FIG. 6 is a diagram for explaining control of a buffer memory;

FIG. 7 is a diagram illustrating an empty state and a full state of the buffer memory.

FIG. 8 is a diagram for explaining the operation of the buffer memory when an error occurs.

[Explanation of symbols]

100 ... Digital broadcast receiving system, 101 ...
・ Antenna, 102 ・ ・ ・ Receiver, 103 ・ ・ ・ Computer, 104 ・ ・ ・ Receiving Board, 105 ・ ・ ・ PCI
Bus, 111 ... System controller, 113 ...
・ Tuner, 114 ・ ・ ・ Demodulator, 115 ・ ・ ・ ECC
Decoder, 116, 133 ... descrambler, 11
7 ... demultiplexer, 118 ... video processing unit, 119, 121 ... output terminal, 120 ... audio processing unit, 131 ... CPU, 132, 136
141 ... connector, 134 ... RAM as buffer memory, 135 ... filtering circuit, 13
7 Bus control unit, 138 Work RAM, 1
42 ... driver, 143 ... buffer memory, 1
44 ・ ・ ・ Application

Claims (8)

[Claims] 1. A device connected to a bus, a register holding data related to the operation of the device, a first access path for accessing the register from the bus side, and an external hardware for accessing the register. A bus control device comprising: a second access path performed from a hardware side; and a selection unit that selects one of the first and second access paths from the bus side. 2. The switching device according to claim 1, wherein the selection unit holds a switch circuit for selecting one of the first and second access paths, and data for controlling an operation of the switch circuit, and the data is set from the bus side. 2. The bus control device according to claim 1, further comprising a register adapted to be executed. 3. The bus control device according to claim 1, wherein the bus is provided in a computer. 4. A bus control method comprising a register for holding data relating to the operation of a device connected to a bus, and selectively accessing the register from the bus side or external hardware side. . 5. An access to the register,
5. The bus control method according to claim 4, wherein the frequent access is performed from the external hardware side, and the infrequent access is performed from the bus side. 6. A board connected to a bus in a computer, comprising: a bus controller for interfacing with the bus, wherein the bus controller comprises a device connected to the bus; A register for holding data relating to the operation of the device, a first access path for accessing the register from the bus side, a second access path for accessing the register from external hardware, And a selecting means for selecting any one of the second access paths from the bus side. 7. A data receiving apparatus, comprising: a receiving unit for receiving data used by a computer; and a receiving board connected to a bus in the computer and transferring received data from the receiving unit to the computer. The receiving board has a bus controller that interfaces with the bus, the bus controller includes a device connected to the bus, and a register that holds data related to the operation of the device. A first access path for accessing the register from the bus side, a second access path for accessing the register from external hardware, and one of the first and second access paths to the bus. A data receiving apparatus comprising: a selection unit for selecting from a side. 8. The device according to claim 7, wherein the device is a FIFO memory for supplying the received data to the bus, and the data held in the register is data relating to an operation of the FIFO memory. A data receiving device according to claim 1.