JP3848805B2 - Receiver - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a multiplexed audio data decoding apparatus for decoding a voice / acoustic (audio) signal encoded in a compressed format, and more particularly, a multiplexing suitable for use as a receiving apparatus for digital broadcasting in which multiple channels are multiplexed. The present invention relates to a generalized audio data decoding apparatus and a receiving apparatus.
[0002]
[Prior art]
As a standard method for compressing a digital audio signal, a method called MPEG (Moving Picture Experts Group) Audio and a method called AC-3 adopted in ATSC (United States Advanced Television Systems Committee) are known. Yes. Each of these methods converts information on the time axis into data on the frequency axis, divides it into frequency bands, uses psychoacoustic characteristics such as masking effects, or compresses information using correlation between audio channels. Based on technology.
[0003]
As a method for decoding (decoding) an audio bitstream compressed using these methods, a digital signal processor (DSP) is used as an audio decoder compatible with the AC-3 format, for example, “Design And Implementation of AC-3 Coders, Vol. 41, No. 3, August 1995 ”. As with a general microcontroller, the DSP is a format that interprets software program code sequentially, processes the data in the built-in registers, and stores the result in memory, so it can decode multiple formats compared to the hardware implementation format. Each algorithm can be provided as a decoding processing code, and since it is flexible to change, it is considered advantageous in terms of both cost and usability. Further, the present invention is characterized in that the calculation speed is improved by providing special hardware such as a high-speed multiplier and a plurality of data buses so as to facilitate the flow of data.
[0004]
[Problems to be solved by the invention]
In general, an audio decoder based on a DSP stores a decoding processing procedure as a program code in a built-in ROM. This is because the program code is read-only and needs to be directly connected to the DSP in order to avoid loss in the access cycle (a normal DSP is one instruction / one cycle).
[0005]
On the other hand, when an audio decoder is considered as a part of a digital broadcast receiver, there are various conditions for compression rate and sound quality depending on the contents of the service and the communication channel conditions on the service supply side such as broadcasting satellites, communication satellites, terrestrial waves and wired cables. Since the optimum encoding format is selected for each, it is necessary to correspond to a plurality of formats on the receiving side.
[0006]
Here, in order to support a plurality of types of compression encoding formats with one DSP chip, it is necessary to secure a program code as an internal ROM for each format. Further, not only the program code but also a dedicated constant table for each format is required as a built-in ROM. Therefore, there is a problem that it is difficult to integrate an audio decoder including a DSP in terms of circuit scale. Further, when the number of formats to be processed is increased or when the specification is changed, the internal ROM of the audio decoder cannot be easily changed, so that there is a problem that flexibility is lowered.
[0007]
An object of the present invention is to provide a receiving apparatus capable of supporting audio data compressed in a plurality of formats in digital broadcasting.
[0008]
[Means for Solving the Problems]
In order to solve the above problems, for example, it is better to use the technical idea disclosed in the scope of claims.
[0009]
With this configuration, multiple types of decode processing codes are stored in the read-only memory, so even when the number of formats to be processed increases or when the specifications are changed, it can be easily handled by changing the read-only memory. , Which can improve flexibility.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the configuration and operation of a multiplexed audio data decoding apparatus according to an embodiment of the present invention will be described with reference to the drawings .
[0015]
First, with reference to FIG. 10, a description will be given of the overall structure of the multiplexed audio data decoding apparatus according to the present embodiment.
[0016]
The multiplexed audio data decoding apparatus according to the present embodiment includes a demultiplexer 10, an audio decoder 20, a digital / analog converter (DAC) 30, a user interface (I / F) 40, an external CPU 50, and an external ROM 60. It is composed of The demultiplexer 10, the audio decoder 20, the user interface (I / F) 40, the external CPU 50, and the external ROM 60 are connected by a data bus DB, and commands and data can be input and output. .
[0017]
The demultiplexer 10 extracts data corresponding to the program designated by the user from the MPEG transport stream (TS) in which a plurality of programs (programs) are multiplexed, and outputs the data to the audio decoder 20.
[0018]
Here, the hierarchical structure of the MPEG transport stream (TS) will be described with reference to FIG. Here, audio data will be described as an example.
[0019]
FIG. 2A shows an MPEG TS serving as an input to the demultiplexer 10 and is composed of TS packets having a fixed length of 188 bytes.
[0020]
As shown in FIG. 2B, the TS packet is composed of a packet ID (PID) and TS_h which are headers, and a payload which is a data portion. The PID is uniquely determined by selecting the program number and the contents of the data. Therefore, for example, by designating the audio data of program #j from the external CPU 50 to the demultiplexer 10, the demultiplexer 10 can extract only the TS packet corresponding to it and make it a processing target.
[0021]
The data portion (payload) of the TS packet is a part of a PES (Packetized Elementary Stream) packet shown in FIG. In other words, the payloads of a plurality of TS packets are collected to form a PES packet.
[0022]
As shown in FIG. 2D, the PES packet includes a PES header and a payload that is a data portion. The PES header (PES_h) includes a stream ID, a display time stamp (PTS: Presentation Time Stamp), and PES_h. The stream ID is a description related to the contents of the PES, and in the case of audio, the encoding format corresponds to the stream ID. The PES can have a plurality of audio access units in the payload, and the PTS indicates the time at which the first audio access unit after the header is to be displayed. The payload includes an audio access unit that is a data portion.
[0023]
As shown in FIG. 2E, the audio access unit is composed of an audio header (Audio_h) including various parameters and encoded audio data for one audio frame as a data portion. The header parameters include sampling frequency, bit rate, frame length, and the like. A series of audio access units is an audio elementary stream (ES). The output of the demultiplexer 10 is an audio elementary stream (ES) that is a continuation of the audio access unit shown in FIG.
[0024]
Next, returning to FIG. 10 , the configuration of the audio decoder 20 will be described.
[0025]
The audio decoder 20 includes a frame synchronization circuit 21, a digital signal processor (DSP) 22, a PCM output interface (I / F) circuit 23, an interface (I / F) circuit 24, and a built-in RAM 25. .
[0026]
The frame synchronization circuit 21 delimits an audio access unit as a unit of processing from the audio elementary stream (ES) input from the demultiplexer 10, that is, delimits an audio frame data composed of a predetermined number of encoded samples. Is discriminated from the periodically appearing bit pattern.
[0027]
The DSP 22 appropriately extracts necessary data from the header information of the audio access unit, and decodes the encoded data. The decoding process is performed in accordance with the decoding program code written in advance in the internal RAM 25 while the internal RAM 25 is used as intermediate data storage or input / output data buffer.
[0028]
A plurality of types of decoding process program codes are written in the built-in RAM 25 in advance, but the decoding process program codes are written by the external CPU 50 via the interface (I / F) 24.
[0029]
The result decoded by the DSP 22 is PCM (Pulse Code Modulation) audio data, which is sent from the PCM output interface circuit 23 to the digital / analog converter (DAC) 30 as time-series sample data and output as an analog audio signal. .
[0030]
The external CPU 50 controls the multiplexed audio data decoding apparatus including the audio decoder 20 and the demultiplexer 10, and the control procedure is stored in the CPU instruction code area 60 </ b> A in the external ROM 60.
[0031]
The external ROM 60 has, in addition to the CPU instruction code area 60A, decoding process code areas 60B1, 60B2,..., 60BN for storing a plurality of decoding process codes # 1, # 2,.
[0032]
The user interface (I / F) circuit 40 receives a command such as program change or media change based on a user channel change, and sends the command to the external CPU 50. When the external CPU 10 detects a change in the encoding format, the audio decoder 20 converts appropriate decoding processing codes # 1, # 2,..., #N stored in the code areas 60B1, 60B2,. Is transferred to the internal RAM 52.
[0033]
The transfer process is performed via an interface (I / F) 24, and buffering and address conversion are also performed.
[0034]
Here, the memory arrangement of the internal RAM circuit 25 used in the multiplexed audio data decoding apparatus according to the present embodiment will be described with reference to FIG. FIG. 3 schematically shows area division in the internal RAM 25.
[0035]
The internal RAM circuit 25 includes a decode processing code area 25a, a work area 25b, a register area 25c and the like. Decoding processing codes # 1, # 2,..., #N stored in decoding processing code areas 60B1, 60B2,..., 60BN of the external ROM 60 shown in FIG. Is stored in the decode processing code area 25a. The work area 25b and the register area 25c are areas used when the DSP 22 performs a decoding process. The boundaries of the areas 25a, 25b, and 25c are variable depending on the encoding format. For example, when the processing code is a short format, the work area 25b can be set wide.
[0036]
The DSP 22 performs an error check on the transferred data, and performs a decoding process on the incoming audio ES using the decoding process code stored in the decoding process code area 25a of the internal RAM 25.
[0037]
Next, the program switching process in the multiplexed audio data decoding apparatus according to the present embodiment will be described with reference to FIGS.
[0038]
FIG. 4 shows the program switching process according to the present embodiment as the subject of an algorithm, and FIG. 5 shows the program switching process according to the present embodiment as the subject of signal exchange between constituent blocks. 4 and 5, the same reference numerals indicate the same processing steps.
[0039]
In step S1, program switching processing is started. For example, when the user switches programs using a remote controller or the like, the program switching command is transferred to the external CPU 50 via the user I / F 40 shown in FIG. 10, and the program switching process by the external CPU 50 starts. Is done. In the following description, it is assumed that the user has selected program #k.
[0040]
Next, in step S <b> 2, the external CPU 50 sends the packet ID (PID) of the program map table (PMT) corresponding to the program number #k to the demultiplexer 10. The PMT is stored in the demultiplexer 10.
[0041]
Next, in step S3, the demultiplexer 10 filters the PID of a desired (audio in this example) packet. Here, in the obtained PMT, the PID of the transport stream (TS) packet including video, audio, and incidental data belonging to the program number #k is written together with the attribute, and the demultiplexer 10 stores this PID. Filter.
[0042]
Next, in step S4, the demultiplexer 10 extracts a reference time from a packet carrying a PCR (Program Clock Reference) indicating a time axis reference included in the accompanying data, and sets the reference time.
[0043]
Next, in step S <b> 5, the demultiplexer 10 acquires a stream ID from the header portion of an audio PES (Packetized Elementary Stream) packet, and sends the stream ID to the external CPU 50 and the audio decoder 20.
[0044]
Next, in step S6, the external CPU 50 knows the audio encoding format after program switching, determines whether or not there is a change from the current format, and jumps to step S9 if there is no change, but if there is a change. Advances to step S7.
[0045]
If there is a change, in step S7, the external CPU 50 reads out the decoding process code corresponding to the audio encoding format after the program switching from the decoding process code areas 60B1,. Forward to 20. The transferred decoding process code is stored in the decoding process code area 25 a of the internal RAM 25.
[0046]
Next, in step S8, the DSP 22 of the audio decoder 20 performs an error check in order to confirm a transfer error of the transferred decoding processing code. As an error check method, for example, a CRC (Cyclic Redundancy Check) code or a test data is actually decoded and compared with an expected value. If there is an error, the audio decoder 20 makes a retransmission request to the external CPU 50 and checks the retransmitted decoding processing code again.
[0047]
When the error check is completed, in step S9, the DSP 22 returns a check completion signal to the external CPU 50, and the external CPU 50 transmits this to the demultiplexer 10.
[0048]
On the other hand, the demultiplexer 10 acquires a display time stamp (PTS) from the PES header in step S5 following steps S3 and S4.
[0049]
Next, in step S11, the demultiplexer 10 sets a decoding time based on the head time of the audio access unit indicated by the PTS.
[0050]
Next, in step S12, the demultiplexer 10 uses the internal system time code (STC) to monitor the set decode time (PTS time), and until the PTS time has arrived, the demultiplexer 10 Stores the stream to be input to the internal buffer and stops the stream.
[0051]
Further, at the time when the PTS time is reached, in step S13, the demultiplexer 10 confirms completion of checking the transfer error sent in the process of step S9 of the audio decoder 20.
[0052]
If the check is not completed, the process returns to step S11 for the next PTS and audio access unit pair, and waits for the PTS time.
[0053]
On the other hand, if the check is completed, the demultiplexer 10 supplies the audio elementary stream (ES) to the audio decoder 20 in step S14.
[0054]
Next, in step S15, the frame synchronization circuit 21 of the audio decoder 20 performs frame (access unit) synchronization processing on the input audio ES.
[0055]
Next, in step S <b> 16, the DSP 22 starts decoding processing using the decoding processing code stored in the internal RAM circuit 25.
[0056]
As described above, in this embodiment, the decoding processing codes for a plurality of types of encoding formats are stored in the external ROM connected to the outside of the audio decoder. Then, in accordance with the encoding format of the input audio stream, one type of decoding processing code corresponding to the encoding format stored in the external ROM is read out and stored in the code area of the internal RAM of the audio decoder. ing. The DSP performs the decoding process using the decoding process code stored in the internal RAM. Here, since the capacity of the external ROM can be sufficiently large, even if the corresponding format is increased, the cost is not increased.
[0057]
Further, addition of a processing target format and specification change can be easily handled by changing the external ROM without changing the audio decoder including the DSP.
[0058]
The external ROM can be changed by replacing the external ROM chip in which a new decoding processing code is written. As another method, when a rewritable flash ROM is used as the external ROM, a new decoding processing code can be written in the flash ROM. At this time, the new decoding processing code may be read from a storage medium such as a disk, or may be downloaded from a network.
[0059]
Here, an example in which the multiplexed audio data decoding apparatus according to the present embodiment described above is applied is shown in FIG.
[0060]
FIG. 10 is a receiving apparatus for receiving a broadcast incorporating a multiplexed audio data decoding apparatus, in which 100 is an external antenna that receives a broadcast signal, 110 is a tuner that selects a received broadcast signal, and 120 is a selector. An error correction (FEC) circuit that performs processing such as error correction on the broadcast signal that has been stationed and outputs it to the demultiplexer 10, and 130 is a speaker that outputs an analog audio signal of the DAC 30.
[0061]
As described above, the present invention can be applied as a broadcast receiving apparatus in which the encoding format is changed . Next , the configuration and operation of a multiplexed audio data decoding apparatus according to another embodiment of the present invention will be described.
[0062]
First, the overall configuration of the multiplexed audio data decoding apparatus according to the present embodiment will be described with reference to FIG. In addition, the same code | symbol as FIG. 10 has shown the same part.
[0063]
The multiplexed audio data decoding apparatus according to the present embodiment includes a video decoder 70, an A / V decoding memory 80, and a digital / analog converter 35 in addition to the configuration of the multiplexed audio data decoding apparatus shown in FIG. Yes.
[0064]
The output of the demultiplexer 10 is input to the video decoder 70 together with the audio decoder 20. The audio decoder 20 and the video decoder 70 are configured to be able to access the common A / V decode memory 80 by time division. Since the A / V decoding memory 80 is realized as an external memory chip having a large capacity (in megabytes), the A / V decoding memory 80 has a sufficient capacity allocated to audio decoding even if the capacity necessary for video decoding is excluded.
[0065]
Here, the internal allocation of the A / V decoding memory 80 used in the multiplexed audio data decoding apparatus according to the present embodiment will be described with reference to FIG.
[0066]
The A / V decoding memory 80 is provided with a stream buffer area 80a necessary for video decoding and a work area 80b such as a frame buffer, and further provided with a graphic display buffer 80c for realizing an interface as a broadcast receiver. Yes.
[0067]
The A / V decoding memory 80 includes an audio decoding work area 80d that can be accessed by the audio decoder 20. Decoding process code areas 80d1,..., 80dN for storing decoding process program codes for all corresponding encoding formats are allocated to the audio decoding work area 80d.
[0068]
Decoding process codes # 1,..., #N stored in the decoding process code areas 60B1,..., 60BN of the external ROM 60 shown in FIG. Stored.
[0069]
Here, the decoding processing code storage processing according to the present embodiment will be described with reference to the flowchart shown in FIG.
[0070]
In step S21, the external CPU 50 sends the decoding process codes # 1,..., #N stored in the decoding process code areas 60B1,..., 60BN of the external ROM 60 via the interface (I / F) circuit of the audio decoder 20. The data is transferred to the A / V decode memory 80.
[0071]
Next, in step S <b> 22, the DSP 22 of the audio decoder 20 checks a transfer error of the decoding process code stored in the A / V decoding memory 80. The transfer error is checked by a CRC check that summarizes the N formats.
[0072]
Next, the program switching process in the multiplexed audio data decoding apparatus according to the present embodiment will be described with reference to FIG.
[0073]
FIG. 9 shows the program switching process according to the present embodiment as the subject of the algorithm. The same reference numerals as those in FIGS. 4 and 5 indicate the same processing steps.
[0074]
Since the program switching process in this embodiment is step S7 ′ instead of step S7 in the program switching process shown in the flowchart of FIG. 4, steps S8, S9, and S13 in FIG. 4 are deleted. The difference will be described.
[0075]
If it is determined in step S6 that the external CPU 50 has changed the audio encoding format after the program switching from the current format, the DSP 22 determines the decoding process code area of the A / V decoding memory 80 in step S7 ′. The decoded code after switching is transferred from 80d1,..., 80dN to the internal memory 25.
[0076]
In general, since the A / V decoding memory 80 has a transmission bandwidth that can withstand video decoding processing, the time required to transfer one type of decoding processing code should be sufficiently shorter than that when transferring from the external ROM 11. Can do.
[0077]
Further, since the transfer reliability is confirmed in the access at the time of decoding, the transfer error check is not required again.
[0078]
As described above, in the present embodiment, decoding processing codes for a plurality of types of encoding formats are stored from an external ROM in an A / V decoding memory connected to the outside of the audio decoder. Then, according to the encoding format of the input audio stream, one type of decoding processing code corresponding to the encoding format stored in the A / V decoding memory is read and stored in the code area of the internal RAM of the audio decoder. Like to do.
[0079]
The DSP performs the decoding process using the decoding process code stored in the internal RAM. Here, since the capacity of the A / V decoding memory can be sufficiently large, even if the corresponding format is increased, the cost is not increased.
[0080]
Further, addition of a processing target format and specification change can be easily handled by changing the external ROM without changing the audio decoder including the DSP.
[0081]
Furthermore, it is possible to reduce the time required to transfer one type of decoding processing code.
[0082]
Further, since the transfer reliability is confirmed in the access at the time of decoding, the transfer error check is not required again.
[0083]
Here, an example in which the multiplexed audio data decoding apparatus according to the present embodiment described above is applied is shown in FIGS.
[0084]
FIG. 11 shows a receiving apparatus for receiving a broadcast incorporating a multiplexed audio data decoding apparatus, wherein 100 is an external antenna for receiving a broadcast signal, 110 is a tuner for selecting the received broadcast signal, and 120 is a selection. An error correction (FEC) circuit that performs processing such as error correction on the broadcast signal that has been transmitted and outputs it to the demultiplexer 10, 130 a speaker that outputs an analog audio signal of the DAC 30, and 140 outputs an analog video signal of the DAC 35 It is a monitor.
[0085]
As described above, the present invention can be applied as a broadcast receiving apparatus in which the encoding format is changed.
[0086]
FIG. 12 shows a recording / reproducing device built-in receiving device for receiving and recording / reproducing a broadcast incorporating a multiplexed audio data decoding device, and 150 is a recording device for recording / reproducing a broadcast signal. The signal is output to the demultiplexer 10. Note that the external antenna 100, the tuner 110, and the error correction circuit 120 in FIG. 11 are omitted.
[0087]
As described above, the present invention can also be applied as a recording / reproducing apparatus built-in receiving device for receiving and recording / reproducing a broadcast whose encoding format is changed.
[0088]
FIG. 13 shows a communication device incorporating a multiplexed audio data decoding device, 170 is an external line such as the Internet, and 160 is a modem that receives the external line, and outputs external information from the modem to the demultiplexer 10. .
[0089]
As described above, the present invention can also be applied as a communication device for receiving communication in which the encoding format is changed.
[0090]
According to the present invention, it is possible to provide a receiving apparatus capable of supporting audio data compressed in a plurality of formats in digital broadcasting.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an overall configuration of a multiplexed audio data decoding apparatus according to an embodiment of the present invention.
FIG. 2 is an explanatory diagram of a hierarchical structure of an MPEG transport stream (TS) input to a multiplexed audio data decoding device according to an embodiment of the present invention.
FIG. 3 is an explanatory diagram of a memory arrangement of an internal RAM circuit used in a multiplexed audio data decoding device according to an embodiment of the present invention.
FIG. 4 is a flowchart illustrating a program switching process in the multiplexed audio data decoding apparatus according to an embodiment of the present invention.
FIG. 5 is an explanatory diagram of signal exchange for program switching processing in the multiplexed audio data decoding apparatus according to the embodiment of the present invention;
FIG. 6 is a block diagram showing an overall configuration of a multiplexed audio data decoding apparatus according to an embodiment of the present invention.
FIG. 7 is an explanatory diagram of allocation in the A / V decoding memory 80 used in the multiplexed audio data decoding device according to the embodiment of the present invention.
FIG. 8 is a flowchart of decoding processing code storage processing in the multiplexed audio data decoding device according to the embodiment of the present invention;
FIG. 9 is a flowchart illustrating a program switching process in a multiplexed audio data decoding apparatus according to another embodiment of the present invention.
FIG. 10 is a block diagram showing a receiving apparatus for receiving a broadcast incorporating the multiplexed audio data decoding apparatus of the present invention.
FIG. 11 is a block diagram showing a receiving apparatus for receiving a broadcast incorporating the multiplexed audio data decoding apparatus of the present invention.
FIG. 12 is a block diagram showing a recording / reproducing device built-in receiving device for receiving and recording / reproducing a broadcast incorporating the multiplexed audio data decoding device of the present invention.
FIG. 13 is a block diagram showing a communication device incorporating the multiplexed audio data decoding device of the present invention.
[Explanation of symbols]
10 ... Demultiplexer 20 ... Audio decoder 22 ... DSP
25 ... Internal RAM
50 ... External CPU
60 ... External ROM
70 ... Video decoder 80 ... A / V decode memory

Claims (4)

A first program including first audio data compressed in a first encoding format and first ID information indicating that the first audio data is compressed in the first encoding format Data, second audio data compressed in the second encoding format, and second ID information indicating that the second audio data is compressed in the second encoding format. A receiver for receiving the program data of 2;
A selection instruction unit for instructing selection of the first or second program data;
A demodulator that demodulates the first or second program data selected by the channel selection instruction unit;
A separation unit that separates the program data demodulated by the demodulation unit;
A decoding unit for decoding the program data separated by the separation unit;
A decoding program storage unit that stores a first decoding program corresponding to the first encoding format and a second decoding program corresponding to the second encoding format, which are arranged outside the decoding unit When,
A control unit that controls at least the decoding unit and the decoding program storage unit;
When the first program data is selected by the channel selection instruction unit, the control unit reads out the first decoding program stored in the decoding program storage unit using the first ID information, When the first audio data is decoded using the read first decoding program and the second program data is selected by the channel selection instruction unit, the second ID information is used. A receiving apparatus, wherein the second decoding program stored in the decoding program storage unit is read, and the second audio data is decoded using the read second decoding program. The receiving device according to claim 1,
The receiving apparatus characterized in that the first or second ID information is included in a PES packet of the first or second program data . The receiving device according to claim 2,
The receiving apparatus, wherein the first or second ID information is a stream ID included in the PES packet. A first program data including first audio data compressed in a first format; a second program data including second audio data compressed in a second format; and the first format. A tuner that receives first format information and second format information related to the second format, and selects the first or second program data;
A control unit that performs decoding processing of the first or second program data;
A memory for storing the first and second programs respectively corresponding to the first and second formats, arranged so as not to be included in the control unit;
When the first program data is selected by the tuner , the control unit reads the first program stored in the memory using the first format information , and reads the read first program data . decoding the first audio data by using the program and the second program data is selected by the tuner, the second program stored in said memory using said second format information And the second audio data is decoded using the read second program .

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