JP4300190B2 - Receiving apparatus and receiving method - Google Patents

Description

  The present invention relates to a television signal receiving and recording / reproducing apparatus, and more particularly to a digital broadcast signal receiving and recording / reproducing apparatus that records and reproduces a digital signal as it is.

  As a conventional technique for recording and reproducing a digital signal, a receiving system and a recording / reproducing apparatus for receiving and recording a digital signal transmitted by multiplexing a plurality of pieces of information are described in JP-A-8-98164. ing. The prior art comprises a receiving means for receiving a digital information signal transmitted by multiplexing a plurality of pieces of information and selecting desired information, and a recording means for recording the information received by the receiving means. A receiving system is described. Japanese Patent Application Laid-Open No. 8-56350 discloses a technique for selecting a desired program when a digital signal transmitted by multiplexing and transmitting a plurality of information is presented. In the prior art, a plurality of programs are each packetized with a packet identifier added thereto, and transmission control data indicating a correspondence relationship between the program and the packet identifier is also packetized, and each of these packets is multiplexed. An apparatus for searching for each program from the multiplexed signals transmitted in this manner is described.

JP-A-8-98164 JP-A-8-56350

In the prior art described in the above-mentioned Japanese Patent Laid-Open No. 8-98164, there is no description about a method of reproducing only information related to a desired program from information multiplexed when the recorded program is reproduced. On the other hand, the prior art described in JP-A-8-56350 describes search means for extracting a desired signal from a multiplexed digital signal and presenting it. However, for example, when a program recorded on a conventional analog VTR is to be reproduced, it is generally possible to reproduce the program without any other operation by simply pressing a reproduction switch. Even when the digital information signal technique described in Japanese Patent Laid-Open No. 8-98164 is combined with the technique described in Japanese Patent Laid-Open No. 8-56350, a troublesome operation such as searching for a program must be performed for reproduction. Rather, the aforementioned analog VTR
Thus, a method of reproducing a desired program immediately recorded by simply pressing one switch could not be realized.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a digital broadcast signal receiving and recording / reproducing apparatus capable of immediately reproducing a program recorded as a digital signal without having to perform a troublesome operation as in the case of the analog system VTR described above. To do.

In order to solve the above problems, for example, the technical idea described in the claims may be used.

By using the present invention, it is possible to detect recording or program breaks during playback. For example, it is possible to easily perform resetting, automatic channel selection, or the like at recording edit points or program breaks.

Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram of a digital broadcast signal receiving and recording / reproducing apparatus according to the present invention. In the following description, an example in which the antenna 1 receives a satellite broadcast radio wave digitally modulated by a quadrature phase shift keying (hereinafter abbreviated as QPSK) method is shown, but this limits the transmission method used in the present invention to satellite broadcast. The modulation method is not limited to the QPSK method. In addition, an example using the international standard Moving Picture Experts Group 2 (hereinafter abbreviated as MPEG2) is shown as a signal compression and decompression method, but this does not limit the signal compression and decompression method used in the present invention to MPEG2. Absent.

  In FIG. 1, 1 is an antenna, 2 is a tuner, 3 is a QPSK demodulator, 4 is a forward error correction (hereinafter abbreviated as FEC) for correcting a signal error accompanying transmission, 5 is a switch, and 6 is a first packet separation. Circuit, 7 MPEG2 decoder, 8 video and audio output terminal, 9 second packet separation circuit, 10 packet replacement circuit, 11 interface circuit, 12 recording / reproducing apparatus, 13 system controller, 14 output circuit It is.

  In FIG. 1, a radio wave transmitted from a satellite (not shown) is received by an antenna 1 and input to a tuner 2. In the example shown in FIG. 1, the tuner 2 selects and outputs a desired signal from the input signal according to the setting of the system control 13. The output of the tuner 2 is demodulated by the QPSK demodulation circuit 3 and input to the FEC 4. The FEC 4 performs error correction of an input digital signal accompanying transmission.

The operation when the digital signal obtained by performing error correction of the input signal as described above is input to the first packet separation circuit 6 via the switch 5 will be described. The satellite digital broadcasting described in the present invention has a feature that a plurality of programs can be multiplexed on one radio wave relayed by a radio wave transponder (not shown) generally mounted on the satellite. The first packet separation circuit 6 selects a desired program from among the multiplexed programs. The signal separated by the first packet separation circuit 6 is input to the MPEG2 decoder 7. The MPEG2 decoder 7 decompresses the compressed digital signal and reproduces the digital video signal and digital audio signal before compression. The reproduced digital video signal and digital audio signal are converted into analog signals by the output circuit 14 and output from the video and audio output terminal 8. The above operation is controlled by the system control 13.

  In the above description, an example of a general procedure for separating desired program information in the first packet separation circuit 6 will be described with reference to FIGS. The signal input to the first packet separation circuit 6 has a configuration in which the packets shown in FIG. An example of multiplexing is shown in FIG. The multiplexed signal as shown in FIG. 2B is processed by the first packet separation circuit 6 to perform the operation described below.

  FIG. 2C shows a configuration example of the header 20 shown in FIG. 2A, in which 23 is a synchronization byte which is a fixed pattern indicating the head of the header, 24 is a transport error indicator, 25 Is a payload unit start indicator, 26 is a transport priority, 27 is a PID indicating an attribute of the packet, 28 is a transport scramble control, 29 is an adaptation field control, 30 is a continuity damage, It indicates the status and consists of 4 bytes. Each number represents the number of bits.

An example of the operation in the first packet separation circuit 6 is shown in FIG. First, in step 201, the program channel of the program that the viewer wants to watch is input. An organized channel is a collective term for video, audio, and the like constituting one program, and corresponds to a television channel in conventional analog broadcasting. In digital broadcasting, generally, one frequency in which a plurality of programs are multiplexed is called a physical channel. Next, in step 202, a PAT (Program Association Table) included in the currently received multiplexed signal (= Transport Stream, hereinafter referred to as TS) is received. The PAT is one of tables in PSI (Program Specific Information) defined by the MPEG2 standard which is an international standard. In step 203, a desired knitting channel is searched from the PAT received in step 202. If there is a desired knitting channel, the process proceeds to step 207. If there is no desired formation channel, the process proceeds to step 204, where one of the PSIs is received, a NIT (Network Information Table) describing the relationship between the formation channel and the physical channel, and the desired formation channel is included. A physical channel is acquired, and the next step 205 moves to the physical channel acquired in step 204. In the actual circuit, the transition of the physical channel is performed by setting a frequency to be selected from the system controller 13 to the tuner 1 as shown in FIG. Thereafter, in step 206, the PAT of the TS in the physical channel after the transition is received. When the PAT is received, the PMT (Packet ID) of the PMT (Program Map Table) in which the PIDs such as video and audio constituting the organization channel input in Step 207 are described is acquired from the PAT, and the PMT having the PID is obtained. Receive. However, the PMT is one of the PSI tables, and as shown in FIG. 2C, the PID is a packet identifier included in the header of the packet. Since the PMT describes PIDs such as PCR (Program Clock Reference) indicating the video, audio, and time information that make up each organized channel included in the TS being received, the video and audio of the desired program in step 208 PID such as PCR is acquired. Thereafter, the acquired PID is set in the first packet separation circuit 6 in step 209, the desired video and audio streams are extracted, the program stream 101 is obtained, and input to the MPEG2 decoder 7 for decoding and the like. The decoded video signal and audio signal are processed by the output circuit 14 to be converted into analog signals, output from the video and audio output terminal, and received by an external television (not shown). A program can be presented.

  Next, a procedure for recording a signal received by the recording / reproducing apparatus 12 through the second packet separation circuit 9 and reproducing a signal from the recording / reproducing apparatus 12 through the switch 6 will be described.

  The second packet separation circuit 9 is means for extracting data necessary for the viewer to reproduce only a desired program during reproduction after recording. At the time of reproduction, in addition to the signal extracted by the first packet separation circuit 6, a packet is required, so a stream different from the program stream 101 is required. In the embodiment of FIG. 1, in addition to the above-described TSs such as PAT, PMT, video, and audio, the PCR (Program Clock Reference) that is data indicating time information required by the MPEG2 decoder 7 and the program related information Among them, information relating to a desired program (program currently being viewed) is extracted and recorded in the recording / reproducing apparatus 12 via the packet replacement circuit 10 and the interface circuit 11.

  An object of the present invention is to automatically select a program of a recorded signal when it is played back by the recording / playback apparatus 12, and for this purpose, the packet replacement circuit 10 performs the above-described PAT replacement before recording.

  Hereinafter, the operation of the packet replacement circuit 10 will be described.

  FIG. 4 shows a configuration example of the packet replacement circuit, in which 44 is a buffer for temporarily storing data of about several bytes, 40 is a PID detection circuit for detecting PID27 from the data stored in the buffer, and 41 is a PID. A PID matching circuit that compares a PID detected by the detection circuit 40 with a predetermined value, 42 is a storage circuit that stores data after replacement, 46 is an output of the input buffer 44 or the output of the storage circuit 42 A selection circuit 54, a timing generation circuit 54, and a PID register 56 for storing a predetermined PID input from the system control 13.

  FIG. 5 shows the operation timing. This packet replacement circuit operates on a byte basis, and all input packets 45 and the like are 8-bit parallel signals. Although not shown in FIG. 4, it operates in synchronization with the byte clock 60 shown in FIG.

  The separated stream 45 output from the second packet separation circuit 9 is sequentially stored in the buffer 44 for several bytes. In FIG. 5, the data for each stage stored in the buffer 44 is referred to as a buffer 1 (52), a buffer 2 (53), a buffer 3 (61), and a buffer 4 (46). In addition, although an enable 70 indicating a section of the input packet is shown, this may be output from the second packet separation circuit 9 or may be generated from the synchronization byte 23 by the timing generation circuit 54.

  The PID (replacement PID) of the packet to be replaced in advance is input by the system control 13 and stored in the PID register 56, and the replaced data (replacement data) is input from the system control 13 and stored in the storage circuit 42. deep. The storage circuit 42 may store a plurality of packet data.

The detection clock 63 is generated from the enable 70 by the timing generation circuit 54. At timing 64, the total of 13 bits including the output 8 bits of buffer 1 and the lower 5 bits of buffer 2 becomes PID27. The PID matching circuit 41 compares the detection PID 55 detected by the PID detection circuit 40 with the replacement PID 57 stored in the PID register 56. If they match, the detection result 51 is set to H as indicated by 65. If they do not match, L is left as indicated by the broken line 66. The selection circuit 46 selects a when the detection result 51 is L, and selects b when the detection result 51 is H. When the detection PID 55 matches the replacement PID 57, the selection circuit 46 outputs the replacement data 47 that is the output of the storage circuit 42. Thereby, the entire packet having a predetermined PID can be replaced with arbitrary data. The output timing of the storage circuit 42 is controlled by the timing generation circuit 54. If they do not match, the output 46 of the buffer 44 is output as it is.

  As a result, a PAT in which PIDs of a plurality of PMT packets for a plurality of programs multiplexed in one input stream 80 is written, and only a PID of a PMT packet of only the currently recorded program is written. Substitution with PAT becomes possible. That is, the system control 13 may store the PID of the PAT in the PID register and store the PAT of only the PID of the PMT packet of the program to be recorded in the storage circuit 42.

  FIG. 6 is a timing chart showing an operation example of packet separation and packet replacement, in which 80 is an input stream inputted to the second packet separation circuit 9, and 45 is one relating to one program in the second packet separation circuit 9. 48 is an output stream that is an output of the packet replacement circuit 10, and _A, _B, and _C are packets related to the A program, the B program, and the C program, respectively, and SI is a video, Packets other than voice are shown.

  The packet separation circuit 9 extracts the packet related to the A program and the PAT from the input stream 80 to obtain the separated stream 45. Since the PATs of the PMTs of all ABC programs are written in the PAT (81, 83) at this time, the PAT (82, 84) of only the PIDs of the PMTs of the A program is performed by the above operation by the packet replacement circuit 10. The replacement is performed and the output stream 48 is output. The output stream 48 is subjected to, for example, parallel-serial conversion by the interface circuit 11 and output to the recording / reproducing apparatus 12 for recording.

  At the time of reproduction, the signal reproduced by the recording / reproducing apparatus 12 is serial-parallel converted by the interface circuit 11 and input to the first separated packet means circuit 6 via the switch 5. The first packet separation circuit 6 is operated by the procedure shown in FIG. 7 under the control of the system control 13 when reproducing the signal recorded in the recording / reproducing apparatus 12. Hereinafter, the operation will be described. In general, the PID indicating program-related information is indicated by a specific value regardless of the program, and this embodiment will be described based on this assumption.

  When a signal is input from the recording / reproducing apparatus 12 via the interface circuit 11 and the switch 5, the first packet separation circuit 6 receives the PAT at step 442. In this PAT, only the PID of the PMT in which the PID of the recorded video, audio, etc. for one program is written is written, so that the desired PID can be acquired immediately. The following procedure is the same as that described in FIG.

  As described above, in the present embodiment, the program reproduced from the recording / reproducing apparatus 12 which recorded the program in the state of the multiplexed digital signal is automatically demultiplexed without the viewer performing a complicated operation. Can be decoded and presented. Furthermore, since the desired program related information is recorded, it is possible to enhance the service using information related to the program, which is one of the features of digital broadcasting.

  In the above description, the packet replacement circuit 10 replaces the entire packet. However, when replacing the PAT, the header 20 is stored as it is, and only the data 21 portion is replaced. It is good. FIG. 8 shows the configuration of the replacement circuit 10 in this case, and FIG. 9 shows the operation timing. In FIG. 8, the a input of the selection circuit 43 is the separated stream 45 before the buffer 44. The timing of the detection clock 63 shown in FIG. 9 and the timing at which the detection result 51 becomes H are the same as in FIG. 5, but the a input of the selection circuit 43 is just when the header 20 ends, and only the data 21 is replaced. Is done. With this configuration, the storage capacity of the buffer 44 can be reduced, and the circuit scale can be reduced.

  5 and 9, the timing 67 at which the detection result 51 returns to L is after the end of the output of the last data of the packet, but it may be switched in the middle of the packet. As a result, only a part of the data 21 can be replaced.

Further, by providing the packet replacement circuit 10 with a mode in which all packets are replaced with replacement data, any packet can be recorded in the recording / reproducing apparatus 12 at any timing. An example of the operation in this case is shown in FIG. In the figure, reference numeral 50 denotes an operation mode of the packet replacement circuit 10 controlled by the system controller 13. The PAT replacement is a mode for performing the normal packet replacement described above, and the total replacement mode_1 is for all input separated streams. Regardless of the PID, the first replacement data stored in the memory circuit 42 (which may be different from the replacement data replaced in the PAT replacement mode), the all replacement mode_2, In this mode, the data is replaced with 2 replacement data. In the full replacement mode, the PID matching circuit 41 may set the detection result 51 to H regardless of the values of the detection PID 55 and the replacement PID 57. As shown in the output stream 48 of FIG. 10, a plurality of packets, PA1 (93 and 94) and PA2 (95) can be recorded under the control of the replacement mode 50 from the system controller 13. PA1 and PA2 may be selected by determining the replacement mode 50 by the timing generation circuit 54 and controlling the storage circuit 42. Specifically, when a RAM is used for the memory circuit 42, the read address of the RAM may be switched.

  Thereby, for example, a packet indicating a recording break can be recorded at the start of recording and at the end of recording, and an edit point of recording, a change point of program, etc. can be detected during reproduction. Thus, it is possible to automatically reset or switch programs.

  By the way, in the above case, there is no guarantee that a packet exists on the separated stream 45 when the time of the full replacement mode is short. Therefore, the separation operation by the second packet separation circuit 9 may be controlled to allow all packets to pass during the full replacement mode.

  FIG. 11 shows the operation timing in this case. The second packet separation circuit 9 is provided with the all packet through mode under the control of the system control 13. Reference numeral 100 denotes a separation mode. When L, the normal separation operation is performed, and when H, the whole packet through mode is performed.

  Since all packets 101 to 105 are input to the packet replacement circuit 10 on the separated stream by setting the second packet separation circuit 9 to the all packet output mode during the full replacement mode_1 and the full replacement mode_2. PA1 (106, 107, 108) and PA2 (109, 110) can be reliably recorded by the recording / reproducing apparatus 12.

  In FIG. 1, the interface circuit 11 and the recording / reproducing apparatus 12 are connected in common to the input and output, but the input and output may be separated. In the above description, serial transmission is used, but parallel transmission may be used. In this case, parallel-serial conversion or the like in the interface circuit 11 becomes unnecessary. Although the first packet separation circuit 6 and the second packet separation circuit 9 have been described as separate circuits, the two means may be the same circuit block.

  Further, in the description of the operations in FIGS. 4 and 8, the signal is described as an 8-bit parallel signal. However, for example, the signal may be processed as a 16-bit parallel signal or a 1-bit serial signal.

  6, 10, and 11, the input stream 80, the separated stream 45, and the output stream 48 are written at the same timing. However, in actuality, because of various processes, there are several bytes to several packets between the streams. This will cause some delay, but is ignored here.

  In the description of the packet replacement circuit 10, the replacement of the PAT has been described. However, the header 20 and data 21 of other packets may be replaced.

  Also, the 4 bits of continuity damage 30 in the header 20 may need to be changed for each packet. At that time, every time the packet is replaced by the system controller 13, the continuity damage 30 on the storage circuit 42 or data of 8 bits (1 byte) including the continuity damage 30 may be rewritten. For this purpose, although not shown in FIG. 4 or the like, the detection result 51 may be input to the system control 13 so that it can be recognized that the packet has been rewritten.

  Furthermore, a CRC code for error check is added to the actual packet data 21, but the CRC of the replacement data may be calculated by the system control 13, or a CRC generation circuit is installed in the packet replacement circuit 10. It may be provided (not shown), thereby generating and adding.

  In the description of this embodiment, a dedicated packet replacement circuit 10 is provided for packet replacement. However, replacement may be performed within the block of the first packet separation circuit 9. Further, packet replacement may be performed simultaneously with packet separation or before packet separation. Alternatively, each packet may be fetched once by the system controller 13 and replaced by the system controller. When the system controller 13 is used, the burden is increased, and thus a high-speed CPU is required. However, there is an advantage that the replacement operation is flexible.

  In this description, whether or not to replace a packet is determined by the PID 27 in the header 20, but other data in the header 20 or specific data in the data 21 may be used.

  4 and 8, the buffer 44, the storage circuit 42, and the PID register 56 are separate circuits, but these may be shared by one or two storage circuits.

The figure which shows the structure of the Example of this invention. Diagram showing packet structure and packet multiplexing method The figure which shows the procedure of program presentation The figure which shows the 1st structure of a packet substitution circuit Timing diagram showing the operation of the packet replacement circuit of FIG. Timing diagram showing packet separation and replacement status The figure which shows the procedure of program presentation at the time of reproduction The figure which shows the 2nd structure of a packet substitution circuit Timing diagram showing the operation of the packet replacement circuit of FIG. Timing diagram showing first operation in full replacement mode Timing diagram showing second operation in full replacement mode

Explanation of symbols

DESCRIPTION OF SYMBOLS 5 ... Switch, 6 ... 1st packet separation circuit, 9 ... 2nd packet separation circuit, 10 ... Packet replacement circuit, 12 ... Recording / reproducing apparatus, 13 ... System control, 20 ... Header, 27 ... PID, 40 ... PID Detection circuit, 41 ... PID matching circuit, 42 ... Storage circuit, 43 ... Selection circuit, 44 ... Buffer, 45 ... Separated stream, 48 ... Output stream, 54 ... Timing generation circuit, 56 ... Timing generation circuit, 80 ... Input stream,

Claims (2)

In a receiving apparatus for receiving a stream in which a plurality of programs and program identification information for identifying the programs are multiplexed in a packet format,
Receiving means for receiving the stream;
Output means for outputting the stream received by the receiving means as an output stream;
Creating means for creating a packet indicating a break in recording that can detect program changes ;
Control means for controlling the output stream output by the output means and the packet created by the creation means to be switched and output;
The receiving device characterized in that the control means continuously outputs a plurality of packets created by the creating means. In a receiving method for receiving a stream in which a plurality of programs and program identification information for identifying the programs are multiplexed in a packet format,
Receiving the stream,
A reception method for outputting the received stream as an output stream,
Create a packet that indicates a break in the record that can detect program changes ,
A receiving method comprising: continuously outputting a plurality of packets indicating a recording break at which a program change point can be detected as an output stream.

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