JPH1168763A - System decoder - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce processing by an MPEG 2 decoder system in which an MPEG 2 transport stream is received from an ATM channel and decoded. SOLUTION: A packet storage processing section 9 has a means to inform a transport stream TS packet storage destination address of a TS packet stored in a RAM 10 to a packet selection processing section 11 and the packet selection processing section 11 accesses only required information of the TS packet in the RAM 10 based on the informed packet storage position information. Then the packet selection processing section 11 reads a packet identifier PID of the TS packet in the RAM 10 and discriminates the packet to be a packet including video data/audio data to be separately outputted, then the packet selection processing section 11 outputs the TS packet to a video decoder 6 and an audio decoder 7 to conduct demultiplexing processing of the TS packet and in the case that it is discriminated that the TS packet is not a packet including the video data/audio data to be separately outputted, the processing with respect to the TS packet is finished immediately.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPEG2 system decoder which receives an MPEG2 image and sound multiplex signal received from an ATM line and performs a multiplex signal separation process.
In particular, the present invention relates to a system decoder that can efficiently separate an image compression signal and an audio compression signal from a multiplex signal by utilizing transmission of a multiplex signal in an ATM network in synchronization with a multiplex packet.

[0002]

2. Description of the Related Art MPEG2 which is an international standard for moving picture compression
(ISO / IEC 13818) is a transport stream (hereinafter, referred to as T) as an audio-visual multiplex signal suitable for broadcasting and communication applications.
S). The TS can multiplex a plurality of programs (a set of video, audio, and other data synchronized with the same time information) into one stream.

An MPEG2 system decoder for decoding a TS separates video data and audio data belonging to one program selected from the input TS (TS separation). Each of the video and audio data separated by the system decoder is decoded into an image signal and an audio signal by the video decoder and the audio decoder, respectively.

The prior art of this type of MPEG2 system decoder will be described in detail with reference to the drawings.

FIG. 12 is a view for explaining the MPEG2 TS data structure, and FIG. 13 is a diagram showing the AAL of an MPEG2 TS packet.
FIG. 14 is a block diagram showing a configuration example of a system decoder according to a conventional technique for performing image / audio multiplex signal separation. In FIG. 14, 1 is an ATM cell assembling unit, 2 is a packet synchronization / byte checking unit, 3 is a FIFO, 4 is a packet selection processing unit, 5 is a system decoder unit, 6 is a video decoder, and 7 is an audio decoder.

[0006] As shown in FIG. 12, a TS has a 188-byte fixed-length transport stream packet (Transport Stream) including a header portion and a payload (PES).
amPacket, hereinafter referred to as a TS packet), and the T
In order to decode S, it is necessary to correctly identify the delimiters of the TS packets in the input TS packet sequence (TS packet synchronization). The first 8 bits of the TS packet are a sync byte for this purpose, and are always H "4".
7 ”(the leading“ H ”means hexadecimal notation,
Similarly, when "B" is added at the beginning, the expression is a binary expression, and when "D" is added at the beginning, the expression is a decimal expression. ). TS
The packet synchronization is generally realized by detecting the shift of the synchronization byte.

[0007] As shown in the figure, the header section is composed of a number of fields, and has a known configuration. In FIG. 12, the information portion in the header portion used for TS separation in the present invention, which will be described later, is surrounded by a thick line.

[0008] Since MPEG2 can be encoded at an arbitrary fixed or variable rate, a flexible application can be realized by using an ATM (Asynchronous Transfer Mode) communication network in which the transmission rate can be freely set. Can be built.

Next, referring to FIG. 13, ATM Adapta
Type-5 (hereinafter AAL5)
A method of mapping a TS packet to an ATM cell when transmitting a TS by using the method will be described.

A plurality of continuous TS packets as shown in the upper part of FIG. 13 are transferred to a CPCS-SDU (Common Part Conv.
ergence sublayer-service data unit), and adding 8 bytes of a padding field and a trailer to the CPCS-PDU (Common Part Convergence S).
ublayer-Protocol Data Unit). The padding field is added for the purpose of making the length of the CPCS-PDU an integral multiple of 48 bytes, and is 0 to 47 bytes. When storing a TS packet in a CPCS-PDU, the first byte of a certain TS packet must be a CPCS-SDU.
To be the first byte of The CPCS-PDU is divided into 48 bytes, each having a 5-byte ATM cell header added, and mapped to a 53-byte ATM cell. Then, the last ATM cell obtained by dividing one CPCS-PDU is distinguished by a parameter in the cell header. Although the number of TS packets stored in the CPCS-PDU is basically two, this value may be set to a value larger than two by negotiation between the transmitting and receiving terminals.

ATM as a receiving terminal of an ATM communication network
The interface is used for receiving ATM
The TS packet is restored from the cell. That is, the ATM interface identifies the last cell constituting the original CPCS-PDU based on the parameters in the cell header of the received ATM cell, and assembles the CPCS-PDU. And
CPCS-S displayed in the CPCS-PDU trailer
By reading the length of the DU and dividing the CPCS-SDU into 188 bytes, the original TS packet sequence at the transmitting terminal is restored.

An MPEG2 system decoder according to the prior art for receiving a TS via an ATM line, demultiplexing and decoding the TS, as shown in FIG. 14, has an ATM cell assembling unit 1, a system decoder unit 5, a video A decoder 6;
It comprises an audio decoder 7. Then, the ATM cell assembling unit 1 receives the A from the ATM line.
The TS packet sequence is restored from the TM cell sequence based on the AAL5 protocol. The system decoder unit 5 is an ATM
Video data and audio data are separated from the TS packet sequence restored by the cell assembling unit 1. Each data separated by the system decoder 5 is decoded by the video decoder 6 and the audio decoder 7. The system decoder unit 5 performs packet synchronization and realization of TS synchronization.
Byte checker 2 and FIF for temporarily storing TS packets
O3 and a packet selection processing unit 4 that identifies the type of the TS packet read from the FIFO 3 and performs a separation process.

In the above description, the packet synchronization / byte inspection unit 2 detects the synchronization byte of each packet in the TS packet sequence received from the ATM cell
Perform synchronization. And a packet synchronization / byte inspection unit 2
Transmits the TS packet sequence to FIFO3 while synchronization is in progress.
When synchronization is lost, synchronization is reestablished by detecting the shift of the synchronization byte, and data during that time is discarded.

The ATM cell assembling unit 1 converts the ATM cell into a CP.
After completing the CS-PDU assembly, the CP
When outputting a plurality of TS packets stored in a CS-PDU, the time interval at which each TS packet is output is not constant. The FIFO 3 is necessary for the purpose of absorbing the fluctuation of the time interval of such TS packets.

The packet selection processing unit 4 reads a TS packet from the FIFO 3, and stores a PID (Packet) which is data indicating a packet type described in a packet header.
An IDentifier, a packet identifier) performs processing corresponding to each packet. The PID is described in the second and third bytes of the TS packet, and the packet selection processing unit 4 can determine the processing for the packet relatively early in the packet reading processing.

When the packet selection processing unit 4 determines from the PID that the TS packet being processed contains video data / audio data belonging to one preselected program, the packet selection processing unit 4 continues to process the TS packet. And performs a process of reading and sending it to a video decoder / audio decoder. Also, the packet selection processing unit 4
A packet containing data that does not require processing of the TS packet,
For example, in the case of a packet storing data belonging to a non-selected program or a packet containing no significant data (null packet) inserted for adjusting the speed of a stream, packet data after the PID is stored in a FIFO. And discard it. Thereafter, the packet selection processing unit 4 processes the next TS packet stored in the FIFO 3.

The system decoder 5 separates video data and audio data from the input TS and outputs the separated data by performing the above operations.

[0018]

In the system decoder according to the prior art shown in FIG.
In the process of analyzing the structure of the S packet, even if it turns out that subsequent processing is unnecessary for the TS packet, it is necessary to read the TS packet from the FIFO 3 and discard it.

The TS is a multiplex signal format capable of multiplexing a plurality of programs as described above. Therefore, in the system decoder according to the prior art, when the program multiplicity is n, that is, when n programs are multiplexed in the TS, the packet selection processing unit 4 must process data at n times speed. However, there is a problem that a high processing capability is required for realizing the packet selection processing unit 4.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a demultiplexer in a system decoder capable of realizing a packet selection processor with lower processing capability.

[0021]

According to the present invention, an object of the present invention is to provide a system decoder which receives a multiplexed signal composed of fixed-length packets and separates and outputs a signal multiplexed on the multiplexed signal. A temporary storage unit for storing the multiplexed signal; a packet storage processing unit for storing the input multiplexed signal in the temporary storage unit; and a boundary position of a fixed-length packet constituting the multiplexed signal stored in the temporary storage device. This is achieved by providing packet selection processing means for reading data at an arbitrary position stored in the temporary storage means and processing each fixed-length packet according to the type of fixed-length packet.

Further, the object is that the packet storage processing means stores fixed-length packets in the temporary storage device while identifying boundaries of fixed-length packets constituting the input multiplexed signal, and the packet selection processing means , The position information indicating the boundary of the fixed-length packet, and the multiplexed signal consisting of the fixed-length packet is transmitted to the ATM AAL Type.
Receiving the ATM cell divided by -5 from the ATM line,
This is achieved by further comprising ATM cell assembling means for assembling the original multiplex signal and inputting the multiplex signal to the packet storage means.

Further, the object is achieved by the ATM cell assembling means notifying the packet storage means of a packet boundary position of a fixed length packet, and the multiplexed signal being an MPEG2 transport stream. Is done.

[0024] Also, the object is to provide a control unit for controlling the address of the temporary storage means by using the storage location of the transport packet acquired from the ATM cell assembling means, An interface unit for reading and writing the device, a transport packet synchronization byte checking unit for checking a synchronization byte of the transport packet stored in the temporary storage unit,
Image and sound P belonging to the program to be separated
A PID table storing a PID of a transport packet including an ES, and a PI of the transport packet;
A PID comparing unit that reads D and compares it with the PID indicated in the PID table; a transport packet analyzing unit that reads necessary information of the transport packet and analyzes the structure; and an analysis of the transport packet analyzing unit This is achieved by including a PES transfer unit that separates and outputs an image and an audio PES from the transport packet using the result.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a system decoder for performing demultiplexing according to the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a basic configuration of a system decoder according to the present invention. In FIG. 1, 8 is A
TM cell assembling unit, 9 is a packet storage processing unit, 10 is a random access memory (Random Access Memory),
RAM 11), 11 is a packet selection processing unit, 12 is a system decoder unit, and the other symbols are the same as those in FIG.

The system decoder shown in FIG. 1 comprises an ATM cell assembling section 8, a system decoder section 12, a video decoder 6, and an audio decoder 7. This configuration is basically shown in FIG. This is the same as in the case of the related art. The system decoder according to the present invention is different from the system decoder of FIG. That is, the system decoder unit 12
A RAM 10 for temporarily storing a TS packet sequence;
A packet storage processing unit 9 for storing the input TS in the RAM 10 while identifying the packet boundary of the packet, and a packet selection processing unit 11 for reading out the TS packets stored in the RAM 10 and performing a process corresponding to each packet. Is done.

The packet storage processing unit 9 has a means for notifying the packet selection processing unit 11 of a TS packet storage destination address as storage position information of a TS packet stored in the RAM 10. The packet selection processing unit 11 can access only necessary information of the TS packet on the RAM 10 based on the packet storage position information notified from the packet storage processing unit 9. Then, the packet selection processing unit 11 determines whether the P
When the ID is read and it is determined that the packet includes video data and audio data to be separated and output, the TS packet is output to the video decoder 6 and the audio decoder 7 to perform the TS packet separation processing. be able to.

Further, the packet selection processing unit 11 has a RAM
When it is determined that the TS packet on P.10 is not a packet containing video data and audio data to be separated and output by determining the PID of a certain TS packet on PI,
There is no need to access the data after D, and the process for the TS packet can be immediately terminated, and the process for the next TS packet can be started.

As described above, the system decoder according to the present invention, even when the input TS has a high degree of program multiplexing, has a packet selection processing unit 11 for TS packets that do not include video data and audio data belonging to the program to be separated. Processing can be kept low.

In addition, the packet storage processing unit 9 in the above configuration generally needs to detect a synchronization byte in order to identify the packet boundary of the input TS. However, when the MPEG2 decoder system including the system decoder having the above-described configuration is connected to the ATM line and the TS is received as an ATM cell, the ATM cell assembling unit 8 for restoring the TS from the received ATM cell outputs the TS packet boundary. It is possible to get

FIG. 2 is a block diagram showing the configuration of a system decoder according to the first embodiment of the present invention, FIG. 3 is a functional block diagram showing the configuration of a packet selection processing unit, and FIG.
FIG. 5 is a diagram for explaining the use status of M and FIFO, FIG. 5 is a flowchart for explaining the processing operation of the packet selection processing unit, and FIG.
Is a diagram illustrating an example of a TS packet, and FIG. 7 is a PID of the TS.
It is a figure explaining the example of. 2 and 3, 17,
18 is a FIFO, 22 is an interface unit, 23 is a TS
Packet synchronization checker, 24 is a PID comparator, 25 is a PI
D table, 26 is TS packet analyzer, 27 is PES
A transfer unit 28 is a control unit, and other reference numerals are the same as those in FIG.

In the first embodiment of the system decoder according to the present invention, the system decoder section 12 includes a TS output from an ATM cell assembling section 8 connected to an ATM line.
And a video and audio PES (Packetized Elementary Stream) belonging to one program among a plurality of programs multiplexed on the input TS are separated and output to the video decoder 6 and the audio decoder 7, respectively. . When the ATM cell assembling unit 8 assembles the TS from the received ATM cells, the CPCS-
Since the first byte of the PDU is always the first byte of the TS packet, the ATM cell assembling unit 8 can identify the boundary of the TS packet. Therefore, in the illustrated example, the AT
The M cell assembling unit 8 has a configuration that outputs a TS packet sequence to the system decoder unit 12 and has a unit that notifies a packet boundary.

The system decoder section 12 has a RAM 10
And a packet storage processing unit 9 for storing an input TS packet sequence in the RAM 10 for each packet, and a packet selection processing unit for reading out necessary data from the RAM 10 to identify the type of the TS packet and performing a process according to each packet 11, the packet storage processing unit 9 and the packet selection processing unit 1
FI for managing the status of use of RAM 10
FOs 17 and 18 are provided.

The RAM 10 has a TS packet length of 18
A plurality of RAM blocks B0, B1,
, B19, and the TS packet is stored in one of the blocks of the RAM 10 by the packet storage processing unit 9. In the following description, the RAM blocks B0, B
,..., The start address of B19 is AD0, AD1,.
, AD19. The FIFO 17 stores the RAM 10 in which the TS packet is stored by the packet storage processing unit 9.
Temporarily stores the start address of the block. Also, FI
The FO 18 temporarily stores the head address of the RAM block in which no TS packet is stored by the packet storage processing unit 9 among the RAM blocks in the RAM 10.

The packet storage processing unit 9 is provided with a usable RA
It has means for obtaining the address of the M block from the FIFO 18 and means for storing the head address of the RAM block storing the TS packet in the FIFO 17. The packet selection processing unit 11 determines the start address of the RAM block in which the packet storage
After completing the processing obtained from O17 and the processing for the TS packet stored in one RAM block,
Means for storing the start address of the RAM block in the FIFO 18. Further, the FIFO 17 sets the start address of the RAM block storing the TS packet to 1
If none is stored, an empty flag signal line is provided as means for notifying the packet selection processing unit 11 of this fact.

As shown in FIG. 3, the packet selection processing unit 11 controls the address of the RAM 10 by the control unit 2.
8 and RAM 10 from each unit in the packet selection processing unit 11.
Interface unit 22 for realizing access to
Read the synchronization byte of the TS packet on M10 and read TS
TS packet synchronization checker 23 for checking packet synchronization
A PID table 25 storing PID data for identifying a TS packet to be processed, a PID comparison unit 24 for reading out the PID of the TS packet on the RAM 10 and referring to the PID table 25 to determine a process for the TS packet. , Read necessary information from the RAM 10 and
TS packet analyzer 26 for analyzing the structure of S packet
And the TS based on the analysis result of the TS packet analysis unit 26.
A video PES and an audio PES are extracted from the packet, and the PES transfer unit 27 is configured to transfer these to the video decoder 6 and the audio decoder.

Next, referring to FIG. 4, when a TS packet is input from the ATM cell assembling section 8 to the system decoder section 12, a packet storage processing section 9, a RAM 10, a FIFO
Operations around O17 and O18 will be described. FIG. 4 (a)
4C, the data written in the FIFOs 17 and 18 by the packet storage processing unit 9 and the packet selection processing unit 11 are described by being stacked on the data already written. I will do it. Therefore, FIFOs 17, 18
Is the data written in the past, and is the data read by the packet selection processing unit 11 and the packet storage processing unit 9.

FIG. 4A shows the state of the RAM 10 and the FIFOs 17 and 18 before the operation of the system decoder 12 starts. Before starting the operation, the RAM 10
No significant data is stored in the upper blocks B0, B1,..., B19. The FIFO 18 holds the head address of the block in which no TS packet is stored among the RAM blocks B0, B1,..., B19. Before the operation of the system decoder 12, all the RAM blocks are in an unused state. So the FIFO
, B19 is a state in which the head addresses AD0, AD1,..., AD19 of the RAM blocks B0, B1,. FIFO 17 is a RAM block B
0, B1,..., B19, a TS packet is stored.
It holds the start address of the block waiting for processing by the packet selection processing unit 11. Therefore, before the operation of the system decoder 12 starts, the FI
In the FO 17, no head address of any block is written, and the empty flag signal is active.

When the system decoder 12 starts operating and the packet storage processing unit 9 receives a TS packet from the ATM cell assembling unit 8, the packet storage processing unit 9
From 18, the address of a usable RAM block is obtained. In this case, since the address AD0 is obtained, the packet storage processing unit 9 stores the TS packet in the RAM block B0 having the address AD0 as the start address, and when this storage is completed, the start address A of the storage destination block B0.
Write D0 into FIFO17. RA at this point
The state of M10, FIFOs 17, 18 is shown in FIG.

Thereafter, each time the packet storage processing unit 9 receives one TS packet from the ATM cell
An operation is performed in which the start address ADk of the usable RAM block Bk is obtained from the FO 18, the TS packet is stored in the RAM block Bk, and the address ADk is written in the FIFO 18.

After the illustrated system decoder unit 12 starts operating, the packet selection processing unit 11 monitors the empty flag signal of the FIFO 17 and waits until the signal becomes inactive. One of the TS packets is input from the ATM cell assembling section 8 to the system decoder section 12, the TS packets are stored in the RAM block, and the state shown in FIG. 4B is reached, and the empty flag signal of the FIFO 17 becomes inactive. Then, the packet selection processing unit 11
Reading is performed from the IFO 17. As a result, the start address AD of the RAM block B0 in which the TS packet is stored
0 is obtained. The packet selection processing unit 11 performs a process to be described later on the TS packet stored in the RAM block B0, and then performs a start address A of the RAM block B0.
Write D0 into FIFO18. RA at this point
The state of M10, FIFOs 17, 18 is shown in FIG.

Thereafter, the packet storage processing unit 11
The empty flag signal of O17 is monitored. If the signal is inactive, the start address ADk of the RAM block Bk storing the TS packet is obtained from the FIFO 17, and the TS packet stored in the RAM block Bk is obtained. After performing the processing described later, the operation of writing the head address ADk of the RAM block Bk in the FIFO 18 is repeated.

Next, the packet selection processing unit 11
Among the processing performed on the TS packets stored in the RAM block Bk on the TS block 0,
This will be described with reference to the flow shown in FIG.

(1) When a TS packet is received and stored in the RAM 10, the packet selection processing unit 11
O17 to R in which the TS packet on the RAM 10 is stored.
Acquire the address ADk of the AM block (Step 5)
01).

(2) The TS packet synchronization checking unit 23 of the packet selection processing unit 11 reads out the synchronization byte of the TS packet in the RAM block Bk starting from the address ADk, and the value is H “47”. Check whether or not. If the TS packet is stored in a properly synchronized manner, the 1st to 8th bits of the RAM block Bk are the synchronization byte, which is read. If the value of the synchronization byte is not H “47”, the TS packet synchronization checking unit 23
It is determined that the TS packet is not synchronized, and the process for the TS packet is terminated (steps 502 and 503).

(3) If it is determined in step 503 that synchronization has been achieved, the PID comparison unit 24 determines whether the PID is stored in the RAM block Bk 12 to 24 which is the position where the PID is stored.
The bit is read out and compared with the PID of the TS packet including the video or audio PES described in the PID table 25 to determine whether the packet is the TS packet to be processed. If it is determined that the packet is a TS packet not to be processed, the PID comparison unit 24
End the processing for the S packet (step 50)
4, 505).

(4) If it is determined in step 505 that the packet is a TS packet to be processed, the TS packet analysis unit 2
6 are RAM blocks Bk 27 to 27 which are locations where adaptation field controls are stored.
The 28th bit is read, and the presence / absence of the adaptation field and the payload is determined. If it is determined that the adaptation field exists and the payload does not exist, the processing for the TS packet is terminated (steps 506 and 507).

(5) If it is determined in step 507 that the adaptation field does not exist and the payload exists, it is determined that the header length of the TS packet is 4 bytes, and the process is passed to step 510 to be described later ( Step 508).

(6) If it is determined in steps 507 and 508 that both the adaptation field and the payload are present, the TS packet analyzer 26
Reads the adaptation field length. Since the adaptation field length indicates the number of bytes of the subsequent adaptation field, the number obtained by adding 5 to this value is the number of bytes of the header of the TS packet (step 509).

(7) Since the header length has been obtained by the processing of the TS packet analysis unit 26, the PES transfer unit 2
7 reads out the data up to the 188th byte from the TS header based on the result and sends it to the video decoder 6 or the audio decoder 7 (step 51).
0).

Next, the processing operation described above will be described with reference to FIG.
FIG. 7 illustrates an example of an S packet and the PI of the TS illustrated in FIG. 7.
A specific description will be given with reference to a diagram illustrating an example of D.

Now, how the TS packets are processed in the case where the TS packets (a) to (e) having the values shown in FIG. 6 are stored in the block Bk will be described below. Here, it is assumed that the PID indicating the type of the TS packet is defined as shown in FIG. 7, and the MPEG2 decoding apparatus having the system decoder according to the present invention as a component decodes the program of program number 1. -It shall be reproduced. Therefore, according to the definition of FIG. 7, the PID table 25 of FIG. 3 contains H as the PID of the TS packet including the video PES to be separated.
“0110” is described, and H “0120” is described as the PID of the TS packet including the audio PES to be separated.

When the TS packet (a) is stored in the block Bk In steps 502 and 503, the TS packet synchronization checker 2
Numeral 3 reads data on the address where the synchronization byte is to be stored, that is, 8-bit data starting with ADk. As a result, H “D9” is obtained. H "4
Since it is not 7 ", it is determined that a synchronization error has occurred, and the processing is terminated for the TS packet.

When the TS packet (b) is stored in the block Bk In steps 502 and 503, the TS packet synchronization checker 2
As a result of reading of the synchronization byte by H.3, H "47" is obtained, and it is determined that it is in a synchronized state. Then, step 5
At steps 04 and 505, the PID comparison unit 24 reads the PID, and H “0210” is obtained. The PID comparison unit 24
The PID of the video PES to be separated (H “0110”) and the PID of the audio PES to be separated (H “0120”) described on the PID table 25 are compared. As a result, since these are different from each other, the TS packet (b)
Is determined not to be a TS packet to be separated,
The process ends for the TS packet.

When the TS packet (c) is stored in the block Bk In steps 502 and 503, the TS packet synchronization checker 2
As a result of reading of the synchronization byte by H.3, H "47" is obtained, and it is determined that it is in a synchronized state. Then, step 5
At steps 04 and 505, the PID comparing section 24 reads the PID, and H “0110” is obtained. The PID comparison unit 24
Compared with the PID described on the PID table 25,
TS containing the video PES to be separated by the TS packet
Judge as a packet. Then, step 506
Then, the TS packet analysis unit 26 reads the adaptation field control. As a result, B “0
1 "is obtained. In step 507, it is determined that no payload exists in the TS packet, and therefore, actual data of the video PES does not exist, and the process for the TS packet ends.

When the TS packet (d) is stored in the block Bk In steps 502 and 503, the TS packet synchronization check unit 2
As a result of reading of the synchronization byte by H.3, H "47" is obtained, and it is determined that it is in a synchronized state. Then, step 5
At steps 04 and 505, the PID comparing section 24 reads the PID, and H “0110” is obtained. The PID comparison unit 24
Compared with the PID described on the PID table 25,
TS containing the video PES to be separated by the TS packet
Judge as a packet. Then, step 506
Then, the TS packet analysis unit 26 reads the adaptation field control. As a result, B “1”
0 "is obtained, and in steps 507 and 508, there is no adaptation field in the TS packet,
It is determined that a payload exists, and it is determined that the header length of the TS packet is 4 bytes. Subsequently, in step 510, the payload (5th to 188th bytes of Bk) following the 4-byte packet header is transferred to the PES transfer unit 27.
Is read out and transferred to the video decoder 6, and upon completion, the processing for the TS packet is terminated.

When the TS packet (e) is stored in the block Bk In steps 502 and 503, the TS packet synchronization checker 2
As a result of reading of the synchronization byte by H.3, H "47" is obtained, and it is determined that it is in a synchronized state. Then, step 5
At steps 04 and 505, the PID comparing section 24 reads the PID, and H “0110” is obtained. The PID comparison unit 24
Compared with the PID described on the PID table 25,
TS containing the video PES to be separated by the TS packet
Judge as a packet. Then, step 506
Then, the TS packet analysis unit 26 reads the adaptation field control. As a result, B “1”
1 "is obtained, and in steps 507 and 508, it is determined that both the adaptation field and the payload are present in the TS packet. In step 509, the TS packet analysis unit 26 determines that the adaptation field length is Is read, and D “9” is obtained, so that the header length of the TS packet is determined to be 14 bytes by adding 5 to 9. Then, in step 510, the header length of the TS packet follows the 14-byte packet header. Payload (15th to 188th bytes of Bk) is transferred to PES transfer unit 2
7 reads it out and transfers it to the video decoder 6, and after completion,
The process for the TS packet ends.

The above-described TS packets (c), (d),
In the example of the process (e), the PID is H “0110” and the TS packet including the video PES is used.
In the case of the TS packet including the audio PES in “0120”, the same processing as described above is performed except that the transfer destination of the PES in the processing of step 510 is the audio decoder 7.

By the processing operation described above, one T
TS separation processing for S packets is possible. Moreover, even when the multiplicity of the input TS is high, the video PES / audio PES belonging to the selected program
Processing for TS packets including data other than the above can be completed by the processing up to step 505, and the processing amount required for TS separation can be reduced.

Note that the above-described embodiment of the present invention
Although M10 is divided into 20 RAM blocks B0, B1,..., B19, it may be necessary to secure more RAM blocks on the RAM 10 as described below.

That is, in the above-described embodiment of the present invention, in order for the system decoder 12 to continue the demultiplexing process without failure, the packet must be transmitted when the ATM cell assembling unit 8 inputs the TS packet to the system decoder 12. RAM that the storage processing unit 9 can use from the FIFO 18
It must be possible to obtain the start address of the block. As processing of a TS packet in which the packet selection processing unit 11 has,
When the PES is transferred to the video decoder 6 and the audio decoder 7, the time required for processing the TS packet is longer than the time required for processing other TS packets.

For this reason, when the TS multiplicity of the input TS is large, the packet selection processing unit 11
While processing the packet, the address of the block storing the TS packet is accumulated in the FIFO 17, and the packet storage processing unit 9 may not be able to obtain the address of the usable block from the FIFO 18. obtain. Therefore, it is necessary to secure a sufficient number of RAM blocks on the RAM 10 to prevent such a state.

FIG. 8 is a block diagram showing the configuration of a system decoder according to a second embodiment of the present invention, and FIG.
0 illustrates the configuration of the address space of FIG. 10, FIG. 10 illustrates the address space of the processor 31, and FIG.
It is a figure explaining the use situation of. 8, 31 is a processor, 32 is a program memory, 33 is a PES output unit, and other symbols are the same as those in FIG.

In the system decoder according to the second embodiment of the present invention, the packet selection processing section 11 in the system decoder section 12 includes a processor 31 and a program memory 32
And the PES output unit 33, and the FIFOs 17 and 18 in the system decoder unit 12 described with reference to FIG.
Is performed by the processor 31. Other configurations are the same as those of the first embodiment of the present invention described with reference to FIG.
This is the same as the embodiment.

In FIG. 8, the system decoder section 12
As in the case described with reference to FIG. 2, a TS output from the ATM cell assembling unit 8 connected to the ATM line is input and one of a plurality of programs multiplexed on the input TS is The video and audio PESs to which they belong are separated and output to the video decoder 6 and the audio decoder 7, respectively. When the ATM cell assembling unit 8 assembles the TS from the received ATM cells,
Since the first byte of the CPCS-PDU is always the first byte of the TS packet, the ATM cell assembling unit 8 can identify the boundary of the TS packet. Therefore, the ATM cell assembling unit 8 in the illustrated example is configured to output the TS packet sequence to the system decoder unit 12 and have a unit for notifying the boundary of the packet.

The system decoder section 12 has a RAM 10
And a packet storage processing unit 9 for storing an input TS packet sequence in the RAM 10 for each packet, and a packet selection processing unit for reading out necessary data from the RAM 10 to identify the type of the TS packet and performing a process according to each packet 11. As shown in FIG. 9, buffer areas B0, B0 for storing TS packets are stored in the RAM 10.
, B19, and flags F0, F1, F2,..., F19 indicating whether or not each buffer area stores a TS packet at a certain point in time.
When the start address of the buffer area Bk is B_ADk and the start address of the flag Fk is F_ADk, the packet storage processing unit 9 and the packet selection processing unit 11 can access the corresponding data by specifying each address.

The packet selection processing unit 11
1 and a program memory 32 storing a program operating on the processor 31, and a PES output unit 33 for outputting a video PES and an audio PES to the video decoder 6 and the audio decoder 7. The processor 31 is connected to the program memory 32, the PES output unit 33, and the RAM 10 via a data bus and an address bus. As described above, in the RAM 10, the buffer areas B0, B1,..., B19 (start addresses B_AD0, B_AD1,..., B_AD19) and the flags F0, F1,. F_AD0, F_AD1,..., F_AD19) are secured, so that the processor 31 can access the corresponding data by designating each address.

As shown in FIG. 10, the address space accessed by the processor 31 includes the buffer area, the flag address, and the output information to the PES output unit 33, that is, the output information to the video decoder and the audio decoder. The storage area (start address V_AD,
A_AD) and a program memory area (head address P_AD) in which an instruction group for implementing the same processing as that of FIG. 5 of the first embodiment is described. In the example shown in FIG. 8, the program memory 32 is shown independently, but the program memory 32 may be secured as a program memory area in the RAM 10 as described above.

In the above, when the processor 31 outputs the video PES and the audio PES to the addresses V_AD and A_AD, the PES output unit 33 decodes these addresses and outputs the data on the data bus to the video decoder 6 and the audio decoder. The data is transferred to the decoder 7. The instruction group as described above is described on the program memory 32, and the processor 31 sequentially stores the instruction group,
Read, decrypt, execute.

Next, in the system decoder according to the second embodiment of the present invention, when the TS packet is input from the ATM cell
The operation around the AM 10 is described by referring to buffer areas B0, B1,...
A description will be given by taking the data stored in F1,..., F19 as an example. In the following description, when the TS packet is stored in the buffer area Bk, the value of the specific bit B in the corresponding flag Fk is set to “1”, and when the TS packet is not stored in Bk. It is assumed that the value of bit B is “0”.

Now, before the operation of the system decoder section 12 starts, as shown in FIG. 11A, the state of the buffer area and the flag in the RAM 10 is such that no significant data is stored in all the buffer areas. It is assumed that “0” is described as the value of bit B of all the flags.

The system decoder section 12 starts operating from the state described above, and the ATM cell assembling section 8 stores the TS packet in the 1
When the packet is sent to the packet storage processing unit 9 of the system decoder unit 12, the packet storage processing unit 9
After confirming that the value of bit B is “0”, the TS packet is stored in the buffer B0 and the flag F0
Is set to "1" as shown in FIG. Thereafter, every time a TS packet is received, the packet storage processor 9 confirms that the value of the bit B of the flag Fk is “0”, and performs an operation of storing the TS packet in the buffer Bk.

After the operation of the system decoder unit 12 starts, the packet selection processing unit 11 monitors the flag F0,
Wait for bit B of flag F to be changed to "1". A
When one TS packet is input from the TM cell assembling unit 8 and the state shown in FIG. 11B is reached, and the value of the bit B of the flag F0 is changed from “0” to B “1”, packet selection is performed. The processing unit 11 performs a process described later on the TS packet stored in the buffer B0,
Is changed from "1" to "0". During this time, the packet storage processing unit 9 sends the T
If one S packet has been received, buffer B
The TS packet is stored in 1 and the value of the bit B of the flag F1 is changed from “0” to “1”. The state of the RAM 10 at this time is shown in FIG.

As described above, the buffer area is sequentially used by the operation of the packet storage processing unit 9, but at the same time, the TS packet in the buffer area is separated by the operation of the packet selection processing unit 11 described later. Is performed, the buffer area becomes usable again (the value of the bit B of the corresponding flag Fk is “0”). After storing the TS packet in the buffer B19, the buffer storage processing unit 9 again receives the next TS packet,
After confirming that the value of the bit B of the flag F0 is "0", the TS packet is stored in the buffer B0.

Next, the operation of the packet selection processing section 11 will be described. The processor 3 in the following description
All of the TS separation processing 1 is realized by the processor 31 reading, decoding, and executing an instruction group on the program memory 32.

The processor 31 includes the system decoder 1
After the operation 2 starts, the flag F0 on the RAM 10 is monitored. When the processor 31 confirms that the packet storage processing unit 9 stores the TS packet in the buffer B0 and changes the value of the bit B of the flag F0 to “1”, the buffer B0
After the process described later is performed on the TS packet stored in the flag F0, the value of the bit B of the flag F0 is changed to “0”. Subsequently, the processor 31 monitors the flag F1,
When it is confirmed that the value of the bit B of the flag has been changed to "1", the TS packet stored in the buffer B1 is processed, and the value of the bit B of the flag F1 is changed to "0". Thereafter, the processor 31 monitors the flag Fk, confirms that the value of the bit B has been changed to “1”, processes the TS packet stored in the buffer Bk, and
The operation of changing the value of bit B of k to “0” is repeated.

Next, the processing performed by the processor 31 on the TS packets stored in the buffer Bk will be described. The processor 31 monitors the flag Fk and, when detecting that the value of the bit B has been changed from “0” to “1”,
A series of processes described below are performed on the TS packets in the buffer Bk (start address B_ADk). Note that this processing operation is the same as the processing operation of the packet selection processing unit described according to the first embodiment of the present invention.
Hereinafter, the processing operation of the processor 31 will be described with reference to FIG. 5 again.

(1) The processor 31 monitors the flag Fk and, when detecting that the value of the bit B has been changed from “0” to “1”, receives the TS packet and
10 is determined, the synchronization byte of the TS packet in the corresponding buffer Bk is read, and the value is set to H.
It is checked whether it is "47". If the TS packet is stored in a properly synchronized manner, 1-8 of the buffer Bk
The bit is a synchronization byte, which is read. If the value of the synchronization byte is not H “47”, the processor 31 determines that the TS packet is not synchronized, and ends the processing on the TS packet (steps 501 to 503).

(2) If it is determined in step 503 that synchronization has been established, the processor 31 reads the 12th to 24th bits of the buffer Bk, which is the position where the PID is stored, and reads the video or video designated in advance. Audio P
By comparing with the PID of the TS packet including the ES, it is determined whether or not the TS packet is a processing target TS packet. If it is determined that the processing target TS packet is not a processing target TS packet, the processing for the TS packet is terminated (step 5
04, 505).

(3) If it is determined in step 505 that the packet is a TS packet to be processed, the processor 31 reads the 27th to 28th bits of the RAM block Bk, which is the position where the adaptation field control is stored. Then, the presence / absence of an adaptation field and a payload is determined. If it is determined that the adaptation field is present and the payload is not present, the processing for the TS packet is terminated (steps 506 and 507).

(4) If it is determined in step 507 that the adaptation field does not exist and that the payload exists, it is determined that the header length of the TS packet is 4 bytes, and the process is passed to step 510 to be described later ( Step 508).

(5) If it is determined in steps 507 and 508 that both the adaptation field and the payload are present, the TS packet analyzer 26
Reads the adaptation field length. Since the adaptation field length indicates the number of bytes of the subsequent adaptation field, the number obtained by adding 5 to this value is the number of bytes of the header of the TS packet (step 509).

(6) Since the header length is obtained by the above-described processing, the processor 31
The data up to the 188th byte from the TS header is read out and written to the address V_AD for video PES and to address A_AD for audio PES. Then, the PES output unit 33 decodes the address on the address bus, and outputs the video PES to the video decoder and the audio PES to the audio decoder (Step 510).

By the processing operation described above, one T
TS separation processing for S packets is possible. Moreover, even when the multiplicity of the input TS is high, the video PES / audio PES belonging to the selected program
Processing for TS packets including data other than the above can be completed by the processing up to step 505, and the processing amount required for TS separation can be reduced.

In the above-described second embodiment of the present invention, B0, B1,
, B19 have been reserved, but when the input TS has a high degree of multiplexing, sufficient buffering is required for the same reason as in the first embodiment of the present invention described above. It is necessary to reserve the number of buffer areas.

As described above, since the mapping of TS packets to AAL5 type is performed by using two or more TS packets as CPCS-SDUs, the packet storage processing in each of the above-described embodiments is performed. The unit 9 receives the CP received from the ATM cell assembling unit 8.
Two or more TS packets constituting a CS-SDU are
It can be easily stored in one block of AM10. As described above, according to each embodiment of the present invention, even when a plurality of TS packets are stored in one block of the RAM 10, since the TS packets have a fixed length, Can be obtained, and the packet separation processing unit 11 can perform the above-described TS separation processing on each TS packet.

The processing for extracting the video PES and the audio PES from the TS packet by the packet selection processing unit constituting the system decoder according to each of the embodiments of the present invention is performed by checking the synchronization of the TS packet, comparing the PID,
This is realized by sequentially executing the procedure of analyzing the data structure of the S packet and transferring the PES. If the synchronization check of the TS packet determines that a synchronization error has occurred, or if the PID comparison determines that the TS packet is not to be processed. , And PES to be extracted by data structure analysis of TS packets
If it is determined that the TS is not included, the TS
The processing for the packet can be ended. According to each of the above-described embodiments of the present invention, the amount of processing as a system decoder can be reduced.

[0089]

As described above, according to the present invention, it is possible to reduce the processing amount of the packet selection processing unit of the system decoder, and it is possible to separate a TS packet having a high degree of multiplicity despite its low processing capability. It is possible to do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a system decoder according to the present invention.

FIG. 2 is a block diagram showing a configuration of a system decoder according to the first embodiment of the present invention.

FIG. 3 is a functional block diagram illustrating a configuration of a packet selection processing unit in FIG. 2;

FIG. 4 is a diagram for explaining the use status of a RAM and a FIFO in FIG. 2;

FIG. 5 is a flowchart illustrating a processing operation of a packet selection processing unit in FIG. 2;

FIG. 6 is a diagram illustrating an example of a TS packet.

FIG. 7 is a diagram illustrating an example of a PID of a TS.

FIG. 8 is a block diagram illustrating a configuration of a system decoder according to a second embodiment of the present invention.

FIG. 9 is a diagram illustrating a configuration of an address space of a RAM in FIG. 8;

FIG. 10 is a diagram illustrating an address space of a processor in FIG. 8;

FIG. 11 is a diagram illustrating the usage status of a RAM in FIG. 8;

FIG. 12 is a diagram illustrating an MPEG2 TS data structure.

FIG. 13 is a diagram illustrating a method of mapping an MPEG2 TS packet to AAL5 type.

FIG. 14 is a block diagram illustrating a configuration example of a system decoder according to the related art.

[Explanation of symbols]

 Reference Signs List 1 ATM cell assembling unit 2 Packet synchronization / byte checking unit 3, 17, 18 FIFO 4 Packet selection processing unit 5 System decoder unit 6 Video decoder 7 Audio decoder 8 ATM cell assembling unit 9 Packet storage processing unit 10 RAM 11 Packet selection processing unit Reference Signs List 12 system decoder unit 22 interface unit 23 TS packet synchronization check unit 24 PID comparison unit 25 PID table 26 TS packet analysis unit 27 PES transfer unit 28 control unit 31 processor 32 program memory 33 PES output unit

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H04N 7/24 H04N 7/13 Z H04Q 3/00

Claims (7)

[Claims] 1. A system decoder for receiving a multiplexed signal consisting of fixed-length packets as input and separating and outputting a signal multiplexed into the multiplexed signal, a temporary storage means for storing the input multiplexed signal, A packet storage processing unit for storing a signal in the temporary storage unit, and a boundary position of a fixed-length packet constituting a multiplexed signal stored in the temporary storage device, and identifying an arbitrary position stored in the temporary storage unit. A system decoder comprising: a packet selection processing unit that reads data and processes each fixed-length packet according to the type of the fixed-length packet. 2. The packet storage processing means stores fixed-length packets in the temporary storage device while identifying boundaries of fixed-length packets constituting the input multiplexed signal, and stores the fixed-length packets in the packet selection processing means. 2. The system decoder according to claim 1, wherein position information indicating a boundary of the information is notified. 3. A multiplexed signal composed of fixed-length packets is transmitted to an AT.
ATM cell divided by M's AAL Type-5
3. The system decoder according to claim 1, further comprising an ATM cell assembling means for receiving an original multiplexed signal from the line, assembling the multiplexed signal, and inputting the multiplexed signal to said packet storage means. 4. The system decoder according to claim 3, wherein said ATM cell assembling means notifies a packet boundary position of a fixed length packet to said packet storing means. 5. The system decoder according to claim 3, wherein the multiplex signal is an MPEG2 transport stream. 6. The packet selection processing means comprises:
A control unit that performs address control on the temporary storage unit using a storage location of the transport packet acquired from the M cell assembling unit; an interface unit for reading and writing the temporary storage device; A transport packet synchronization byte inspection unit for inspecting a synchronization byte of the transport packet, a PID table storing PIDs of transport packets including an image and an audio PES belonging to a program to be separated, and a PID table of the transport packet. PID for reading the PID and comparing it with the PID shown in the PID table
A comparing unit, a transport packet analyzing unit that reads necessary information of the transport packet and analyzes the structure, and separates an image and an audio PES from the transport packet using an analysis result of the transport packet analyzing unit. 6. The system decoder according to claim 5, further comprising a PES transfer unit that outputs the data. 7. The system decoder according to claim 5, wherein
MPEG image decoding means for decoding a PEG image signal;
An MPEG2 decoding device comprising: MPEG audio decoding means for decoding a PEG audio signal.