JPH11355125A - Logical circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a logical circuit by a pass-transistor, by which a circuit area is reduced, low power consumption conversion owing to a low voltage operation is enabled and high integration and high speed conversion are attained. SOLUTION: The logical circuit is provided with a logic part 1 constituted of pass-transistor logic and a buffer part 2 for compensating the output level of the pass-transistor logic. In the circuit, the logic part is constituted by using partial depletion-type SOI MOSFET 13. Here, it is favorable that partial depletion-type SOI MOSFET 13 is NMOSFET. Besides, the substrate potential of MOSFET 13 is also favorable to be in a floating state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a logic circuit using pass transistors.

[0002]

2. Description of the Related Art As LSIs become finer, higher in performance, and larger in capacity, power consumption of transistors constituting next-generation LSIs has become a major problem. This is because an increase in the number of elements causes an increase in power consumption. In order to reduce the power consumption of the LSI, it is effective to lower the power supply voltage. As a method of lowering the power supply voltage of the logic part of the LSI, adoption of a pass transistor logic is being studied.

A logic circuit using pass transistors has been disclosed in Japanese Patent Application Laid-Open No. 2-288917 for the purpose of miniaturizing the circuit, reducing power consumption, and increasing the speed.
However, in a logic circuit having a pass gate structure, as shown in FIG. 2, in an insulated gate transistor (MOSFET) 3 constituting a pass transistor logic, 1
When a signal propagates between the drain and the source in the stage, a voltage higher than the threshold value of the transistor to be used is reduced by the threshold value. Therefore, the signal level does not exceed (power supply voltage-threshold).

In addition to the voltage drop, when a bulk MOSFET is used as a pass transistor, the threshold voltage increases due to the body effect. The effect is greater in later stages. When an SOI MOSFET is used, the threshold voltage increases due to the body effect. In order to compensate for the signal delay time caused by such a voltage drop, the output of the logic circuit is output via a compensation circuit, that is, a buffer circuit. Therefore, the driving capability of this buffer circuit must be increased, and
An increase in the area occupied by the buffer circuit in the chip poses a new problem.

[0005] In order to minimize the increase in the circuit area due to such a compensation circuit, to reduce the substrate bias effect of the bulk MOSFET and the body effect of the SOI MOSFET, the circuit has a structure in which the threshold value of each FET is controlled. Has been devised. FIG. 3 shows a circuit example of a structure for suppressing the substrate bias effect. In this example, the bulk MOSFET 4
Has a structure for connecting the gate 5 and the substrate 6. However, in order to assemble a logic circuit with such a structure, it is necessary to electrically isolate each MOSFET.

Another conventional example is shown in FIG.
GBC (Ga) described in the document “Design Method of 0.5 V Operation CMOS Logic Using SOI”
te-Body Connection) The F-type used in the SOI / MOSFET circuit to reduce the body effect called the system
An example of an ET circuit is shown. By providing a back gate 9 in the SOI MOSFET 7 and connecting the gate 8 and the back gate 9, a threshold voltage drop related to an output signal from the pass gate network is reduced. In this case, in order to provide the back gate 9,
Special structures and manufacturing processes need to be added.

FIGS. 5 and 6 show examples of a compensation circuit according to the prior art. FIG. 5 shows an example in which two inverter circuits 11 are used to compensate for a decrease in the output of the pass transistor 10, and FIG. Requires a compensation circuit with a large number of elements.

[0008]

In the above prior art, the threshold value is controlled for each MOSFET.
It is necessary to electrically separate a substrate or a body for each transistor, and to add a circuit for controlling a substrate potential or a body potential. For this reason, there are problems that the structure for electrical isolation between the FETs becomes complicated, further manufacturing steps are added, the circuit area of the added circuit increases, and the power consumption increases. Furthermore, bulk MOSF
In addition to the delay time of the substrate of the ET or the body of the SOI MOSFET, there is a problem that a delay time is generated due to a circuit for controlling the potential of the substrate or the body. In addition, there is a problem that a compensating circuit having a complicated number of elements must be used.

Accordingly, an object of the present invention is to solve the above-mentioned problems of the prior art and to provide a logic circuit using a highly integrated and high-speed pass transistor which realizes low power consumption applicable to the gigabit generation. Is to do.

[0010]

The present invention provides a partially depleted SO.
A logic circuit comprising: a logic unit configured by a pass transistor logic using an I-MOSFET; and a buffer unit provided for compensating an output of the logic unit.

Partially depleted SO as a pass transistor
By using an I-MOSFET, an increase in threshold voltage due to a body effect when a signal propagates through a pass transistor is suppressed without performing element isolation, addition of a body potential control circuit, or the like. As a result, it is possible to reduce the propagation delay of the pass transistor and to increase the speed and the voltage. In addition, since the area of the buffer circuit required for operating the circuit at high speed can be minimized, power consumption can be reduced and the degree of integration can be prevented in this aspect as well. In addition, it is possible to suppress an increase in power consumption due to a through current or the like.

Then, a partially depleted SOI MOSFET
Is made to be an NMOSFET, higher speed operation becomes possible. The substrate potential of the partially depleted SOI.MOSFET can be set to a floating state.

The output power of the logic circuit can be further increased by forming the buffer portion on the same substrate as the logic portion and using the buffer portion with a bulk MOSFET. Further, the manufacturing process can be shortened by forming the buffer portion from a fully depleted SOI.MOSFET formed on the same substrate as the logic portion.

Further, in the present invention, the logic portion is formed by a partially depleted SOI.MO having a substrate potential in a floating state.
The buffer section is composed of a plurality of partially depleted SOI MOSFETs formed on the same substrate as the logic section and having independent back gates. , It is possible to suppress an increase in power consumption during off-state even when a partially depleted SOI.MOSFET having a small threshold value is used also in the buffer section.

[0015]

FIG. 7 shows a partially depleted SOI · M constituting the present invention.
5 shows voltage-current characteristics of an OSFET and a normal bulk MOSFET. The horizontal axis is the gate voltage, and the vertical axis is the source / drain current. These are the results obtained by changing the body potential or the bulk potential in six steps between -2V and 2V, respectively. In the case of a partially depleted SOI.MOSFET, the voltage-current characteristics at each stage overlap, and no shift in the voltage-current characteristics due to a change in the body potential is observed. on the other hand,
In the case of a bulk MOSFET, a characteristic is shown in which the voltage-current characteristics shift due to a change in the bulk potential. The curve on the right side indicates a case where the bulk potential is higher, and indicates that the threshold value increases as the bulk potential increases.
As described above, the partially depleted SOI.MOSFET has such characteristics that the threshold voltage hardly changes due to the body potential and the effect of the body effect is extremely small.
The present invention mainly utilizes such characteristics of the partially depleted SOI MOSFET.

As described above, the partial depletion type SOI / MOSF in which the change in the threshold voltage due to the body effect is extremely small.
By using ET as a component of pass transistor logic, MOSF
It is possible to prevent a voltage drop due to the ET body effect. Since the voltage drop is small, driving at a low voltage becomes possible, and furthermore, it is possible to prevent a reduction in the speed at which a signal propagates in the pass transistor network.
Further, as shown in FIG. 7, since the rise of the voltage-current characteristic is steep, when a buffer circuit such as a CMOS is used as the compensation circuit, an increase in power consumption due to a through current at the time of switching can be suppressed. .
In addition, by using a partially depleted FET, the threshold voltage itself can be reduced, and since the variation in threshold voltage between the transistors is small, the power supply voltage can be reduced accordingly.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to specific embodiments, but the present invention is not limited to the embodiments described below. Various modifications are possible without departing from the technical scope of the present invention.

FIG. 1 shows a basic configuration of a logic circuit according to the present invention. The logic circuit of the present invention includes a logic unit 1 composed of logic using pass transistors, and a buffer unit 2 connected to the logic unit 1 and having a compensation circuit for compensating an output voltage drop of the logic unit.

FIG. 8 shows an embodiment of the present invention, in which an AND circuit section 14 and a compensating circuit 1 each including four pass transistors 13 are provided.
5 shows a three-input AND circuit 16 using 5. In FIG. 8, a partially depleted SOI · M
OSFET is used. The channel of this FET may be either n-type or p-type.
It is more desirable to use types. A, B, ~ B in the figure,
C and -C are signal input terminals of the AND circuit unit 14,
O is an output terminal of the AND circuit unit 14.

When a signal is input to each input terminal of FIG.
Each FET 13 in FIG. 8 has a gate input A, B,
When .about.B, C, or .about.C is at "H" level, the input or output potential of the preceding stage is propagated, and as a result, A.B.C
Is output to the output terminal YO of the AND circuit unit 14. The compensation circuit 15 is a pass transistor 1
3 to compensate for the voltage drop, and further increase the power supplied to the subsequent stage. As the compensation circuit 15, a buffer circuit generally used in a normal digital IC circuit can be used, and the present invention is not limited by a specific circuit configuration of the buffer circuit.

As the pass transistor 13 in FIG. 8, a partially depleted SOI MOSFET 13 that can suppress the body effect without adding another circuit or changing the structure is used. By using a partially depleted SOI / NMOSFET, a circuit can be designed without lowering the degree of integration and without considering an increase in threshold voltage due to the body effect, and a high-speed circuit operation is possible.

FIG. 9 shows a partial sectional structure according to an embodiment of the present invention. On the same substrate 17, a partially depleted SOI MOSFET 13 forming the logic unit 1 and bulk MOSFETs 25 and 26 forming the buffer unit 2 are formed. If the bulk MOSFET has a higher device driving capability due to process characteristics, the bulk MO
Buffer part 2 is made of SFET and partially depleted SOI / MOS
By configuring the logic unit 1 with the FET, the effect of the body effect can be suppressed in the logic unit 1 and the high driving capability of the bulk MOSFET can be utilized in the buffer unit 2.

In the example shown in FIG. 9, an N-type well 24 is formed in a P-type silicon substrate 17 and bonded to each other with an oxide film 18 therebetween.
The source 19, the drain 20, and the channel layer 21 of the FET 13 are formed. P of substrate if necessary
It is also possible to reverse the type and the N type. Further, a compound semiconductor such as GaAs can be used instead of the silicon layer. 22, a gate oxide film; and 23, a gate electrode. In order to make the MOSFET 13 partially depleted,
The thickness and impurity concentration of the channel portion 21 are appropriately controlled. The threshold voltage of the partially depleted MOSFET can be manufactured with less variation by appropriately controlling the gate oxide film thickness and the impurity amount of the channel portion 21 which are easily controllable.

25 is a P-type bulk MOSFET, 26 is N
Type bulk MOSFET.
It can be formed by an S inverter circuit. FIG.
In another embodiment of the present invention, the FETs 13 and 28 are formed on the N-type layer on the surface of the substrate which is insulated and separated by a pn junction to bring the substrate potential into a floating state. In this embodiment, both partially depleted SOI
The logic unit 1 and the buffer unit 2 are configured using the MOSFETs 13 and 28.

The N-type layer 2 is formed on the surface of the P-type silicon substrate 17.
7 is formed, and partially depleted SOI MOSFETs 13 and 28 are formed thereon via an oxide film layer 29. According to this structure, the influence of the body effect of the pass transistor can be suppressed, and at the same time, the MOSFET of the buffer section can be manufactured by the same process as the MOSFET of the logic section.
The production process is not mixed, the yield is improved, and the chip area can be minimized.

FIG. 11 shows still another embodiment of the present invention.
34, and a partially depleted SOI / MOSF of the logic unit 1
The ET 13 is configured in a floating state. A buried back gate structure 31 is provided immediately below the SOI MOSFETs 33 and 34 in the buffer unit 2. With this structure, a potential can be applied to the back gates of the MOSFETs 33 and 34. This structure is
An N-type layer 30 having a buried back gate structure 31 formed by, for example, an N-type high impurity concentration region is formed on the surface of the type silicon substrate 17, and a partially depleted SOI MOSFET 13 and an oxide film layer 34 are formed thereon. SOI ・
The MOSFETs 33 and 34 are formed. In this example, the SOI MOSFETs 33 and 34 are of the same partially depleted type as the logic part, but may be of the fully depleted type if necessary. Further, the back gate structure is insulated and separated, and for example, the MOSFET 33 is an n-type MOSFET, M
The OSFET 34 may be a P-type MOSFET and have a circuit configuration in which PMOS and NMOS are mixed.

With this configuration, the logic unit 1 suppresses the influence of the body effect, and the buffer unit 2 applies a potential to the back gate electrode 32 when the operation is stopped, thereby depleting the channel layer from the back gate side of the partially depleted FET to the channel layer. By extending the layer and operating like a fully depleted SOI MOSFET, suppressing current leakage, high speed operation and low power consumption can be realized.

As described above, the buffer unit 2 for compensating the output level of the logic unit 1 constituted by the pass transistor logic
In the logic circuit having
By using an I.MOSFET, the effect of the body effect can be suppressed, and the logic unit 1 can be operated at higher speed, lower voltage, and lower power consumption. Further, the buffer unit 2 is provided with bulk MOSFETs 25, 2 depending on process characteristics, purpose of use, and the like.
6. SOI · M having partially depleted SOI · MOSFET 28 and body potential control structure 31 with back gate
By using the OSFET 33 or the like, a logic circuit excellent in high integration, low power consumption, high-speed operation, and the like can be formed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the present invention.

FIG. 2 is a diagram illustrating signal propagation in a pass transistor logic circuit.

FIG. 3 is a diagram for explaining a conventional technique.

FIG. 4 is a diagram for explaining a GBC system which is a conventional technique.

FIG. 5 is a diagram illustrating a compensation circuit according to the related art.

FIG. 6 is a diagram illustrating a compensation circuit according to the related art.

FIG. 7 is a partially depleted SOI MOSFET and bulk MO.
FIG. 3 is a diagram illustrating voltage-current characteristics of an SFET.

FIG. 8 is a diagram showing an embodiment of the present invention.

FIG. 9 is a diagram showing a partial cross-sectional structure in an example of the present invention.

FIG. 10 is a diagram showing a cross-sectional structure of another embodiment of the present invention.

FIG. 11 is a view showing a sectional structure of another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Logic part 2 ... Buffer part 3 ... MOSFET which comprises pass transistor logic 4 ... Bulk MOSFET 5 ... Gate 6 ... Substrate 7 ... SOI.MOSFET 8 ... Gate 9 ... Back gate 10 ... Pass transistor 11 ... Inverter circuit 12 ... Intersection Latch circuit 13 ... Pass transistor 14 ... AND circuit section 15 ... Compensation circuit 16 ... 3-input AND circuit 17 ... Substrate 18 ... Oxide film 19 ... Source 20 ... Drain 21 ... Channel layer 22 ... Gate oxide film 23 ... Gate electrode 24 ... N Type Well 25, 26 ... Bulk MOSFET 27 ... P-type silicon substrate 28 ... N-type layer 29 ... Oxide film layer 30 ... N-type layer 31 ... Embedded back gate structure 32 ... Back gate electrode 33, 34 ... SOI MOSFET

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroaki Tanaka 1-1-1, Showa-cho, Kariya-shi, Aichi Pref.

Claims (7)

[Claims] 1. A logic circuit comprising a logic section composed of pass transistor logic and a buffer section for compensating an output level of the pass transistor logic, wherein the logic section is a partially depleted SOI · M as a pass transistor.
A logic circuit comprising an OSFET. 2. The partially depleted SOI.MOSFET includes an N-type SOI MOSFET.
The logic circuit according to claim 1, wherein the logic circuit is a MOSFET. 3. The logic circuit according to claim 1, wherein the substrate potential of said partially depleted SOI.MOSFET is in a floating state. 4. The logic circuit according to claim 1, wherein the buffer unit is formed on the same substrate as the logic unit, and is configured using a bulk MOSFET. 5. The logic circuit according to claim 1, wherein the buffer section is formed on the same substrate as the logic section, and is configured using a fully depleted SOI MOSFET. 6. A logic circuit comprising a logic section composed of pass transistor logic and a buffer section for compensating an output level of the pass transistor logic, wherein the logic section has a partially depleted type having a floating substrate potential. The logic unit is configured by using a plurality of partially depleted SOI MOSFETs formed on the same substrate as the logic unit and provided with independent back gates. circuit. 7. The logic circuit according to claim 6, wherein the MOSFETs constituting the buffer section include an NMOSFET and a PMOSFET having a back gate, and supply a potential to each back gate such that these are completely depleted. A control method for a logic circuit, characterized in that: