JPH11354577A - Manufacture on opened spheric lattice array package technology - Google Patents
Manufacture on opened spheric lattice array package technologyInfo
- Publication number
- JPH11354577A JPH11354577A JP17205998A JP17205998A JPH11354577A JP H11354577 A JPH11354577 A JP H11354577A JP 17205998 A JP17205998 A JP 17205998A JP 17205998 A JP17205998 A JP 17205998A JP H11354577 A JPH11354577 A JP H11354577A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- substrate
- package
- packaging
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体ＩＣ回路チッ
プのパッケージ技術に関するもので、パッケージ後は製
品の体積が小さく、信頼性が良くなり、パッケージの過
程は一貫かつ完全であるメリットがあり、なおかつそれ
は低コスト、低汚染性の製造過程であり、高い産業利用
性のあるパッケージ法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor IC circuit chip packaging technology, which has the advantages that after packaging, the volume of the product is small, the reliability is improved, and the packaging process is consistent and complete. It is a low-cost, low-contamination manufacturing process and relates to a packaging method with high industrial applicability.
【０００２】[0002]
【従来の技術】エレクトロニックスＩＣ産業の盛んな発
展によってそれの競争はますます激しくなり、半導体Ｉ
Ｃ回路のパッケージは軽薄短小の傾向下に於いて、逐
次、チップスケールパッケージ（Ｃhip Ｓcale Ｐackag
e, ＣＳＰ）法へ歩むようになっている。すなわち、パ
ッケージされた製品の長さと幅はＩＣチップの１.２倍
または面積が１.４４倍になり、そのためにパッケージ
後の寸法をできるだけ元のチップ寸法に接近させ、容積
が大幅に縮小するようにし、それによって応用製品はよ
り小さく密集するようになって軽薄短小の要求に合致す
るようにしている。2. Description of the Related Art With the vigorous development of the electronics IC industry, its competition has become increasingly intense,
Under the trend of C-type packages, which are becoming lighter and thinner, chip-scale packages (Chip Scale Packag)
e, CSP) method. That is, the length and width of the packaged product is 1.2 times or 1.44 times the area of the IC chip, so that the dimensions after packaging are made as close as possible to the original chip dimensions and the volume is greatly reduced. In this way, the application products become smaller and more compact, so as to meet the requirements of light and small.
【０００３】従来のＩＣ回路パッケージ法はリードフレ
ームを主としたパッケージ法で、図１に示すものはパッ
ケージ終了後の製品の側面断面図である。その中、ＩＣ
回路チップ１０は中央に位置し、それの両側にはリード
フレーム２０が分布されてあり、接続線３０をもってチ
ップ１０の接続脚とリードフレーム２０を連接し、外部
と接続できる回路に形成する。外側周縁はパッケージ物
質４０をもって全体的構造を密封包覆し、一部のリード
フレーム２０だけが溶接用として露出するようになって
いる。The conventional IC circuit package method is a package method mainly using a lead frame, and FIG. 1 is a side sectional view of a product after the package is completed. Among them, IC
The circuit chip 10 is located at the center, and lead frames 20 are distributed on both sides of the circuit chip 10. The connection legs of the chip 10 and the lead frame 20 are connected to each other with connection lines 30 to form a circuit that can be connected to the outside. The outer periphery hermetically encloses the entire structure with the packaging material 40 so that only a portion of the leadframe 20 is exposed for welding.
【０００４】普通、このようなパッケージ法によってパ
ッケージされたＩＣ回路の容積はＩＣの寸法よりもかな
り大きく、ＣＳＰの要求に合致しにくくなる。その原因
はもしリードフレーム２０の外部溶接用の接続脚間の距
離を狭くすることによってそれに占される容積を小さく
しようとした場合、表面溶接技術（Ｓurface ＭountＴe
chnology, ＳＭＴ）の制限があることを考えてパッケー
ジされるＩＣ回路を印刷回路板に溶接する必要がある。[0004] Usually, the volume of an IC circuit packaged by such a packaging method is much larger than the size of the IC, making it difficult to meet the requirements of the CSP. The cause is that if an attempt is made to reduce the volume occupied by reducing the distance between the connecting legs for external welding of the lead frame 20, the surface mounting technology (Surface MountTe) is used.
It is necessary to weld the IC circuit to be packaged to the printed circuit board in view of the limitations of SMT (Chnology, SMT).
【０００５】しかし、このＳＭＴに使われる機械設備は
加工制度の制限があるので、普通、そのリードフレーム
２０の溶接接続脚の距離が０.５mmよりも小さい場合、
ＳＭＴ加工の難しさが大幅に増えてしまい、加工コスト
も相対的に増えてしまう。更にＩＣ回路の設計による接
続脚の増加及び脚間距離の短縮に伴い、それとの連接に
使われるリードフレーム２０は従来のスタンピング法に
代わってエッチング法が使われ、より精度の良いものを
作る必要があり、当然ながらコストの上昇は無視できな
くなる。またＴＳＯＰ（Ｔhinner Ｓmall Ｏut-Ｌead
Ｐackage）法をパッケージに応用することは、それの厚
さに決められた仕様があり、その最終的にパッケージさ
れたＩＣ回路を仕様に合致できるようにするためにはチ
ップを薄くする必要がある。そのために加工過程に於い
てチップが破れることが起こり、知らない中に加工コス
トとリスクが増えてしまうことがある。この外、近年来
は高速、高周波数のＩＣ回路が絶えず作られ、このパッ
ケージ法によって形成される高いインピーダンス特性は
このような製品の特性に合致しない。However, since the mechanical equipment used for this SMT has a limitation in the processing system, usually, when the distance of the welding connection leg of the lead frame 20 is smaller than 0.5 mm,
The difficulty of the SMT processing is greatly increased, and the processing cost is relatively increased. Further, as the number of connection legs increases and the distance between the legs decreases due to the design of the IC circuit, the lead frame 20 used for connection with the connection is replaced with the conventional stamping method, and the etching method is used. The rise in costs cannot be ignored, of course. In addition, TSOP (Thinner Small Out-Lead)
Applying the (Package) method to a package requires specification of its thickness, and the chip needs to be thinner in order to be able to finally meet the specification of the packaged IC circuit. . As a result, the chip may be broken during the processing process, and the processing cost and risk may increase without knowing it. In addition, in recent years, high-speed, high-frequency IC circuits are constantly being produced, and the high impedance characteristics formed by this packaging method do not match the characteristics of such products.
【０００６】図２に示すものは従来の球状格子配列の溶
接法を主としてパッケージした製品である。そのＩＣチ
ップ１０の裏面は予め熱硬化性接着剤をもって基板５０
の表面に接着し、基板５０の裏面には球状格子配列の接
点６０がある。接続線３０はチップ１０の接続脚と基板
５０の連接点を接続するが、このような基板５０は少な
くても２枚（上、下ともに銅箔がついている）使われて
いるので、基板５０上側の連接点に孔を開け、銅メッキ
等の方法をもって基板５０下側の球状格子配列の接点６
０と連接導通することができ、パッケージ物質４０は基
板５０上に於いてチップ１０及び接続線３０をパッケー
ジして製品にする。The product shown in FIG. 2 is a product mainly packaged by a conventional welding method of a spherical lattice arrangement. The back surface of the IC chip 10 is preliminarily coated with a thermosetting adhesive on the substrate 50.
And a contact point 60 in a spherical lattice arrangement on the back side of the substrate 50. The connection line 30 connects the connection leg of the chip 10 and the continuous contact of the substrate 50. Since at least two such substrates 50 (both upper and lower are provided with copper foil) are used, A hole is made in the upper connecting contact, and the contact 6 in a spherical lattice arrangement on the lower side of the substrate 50 is formed by a method such as copper plating.
The package material 40 packages the chip 10 and the connection lines 30 on the substrate 50 to form a product.
【０００７】このような方法は前述リードフレームのパ
ッケージ法よりも占す面積が小さいが、チップ１０上側
に延伸する接続線３０の回路がパッケージ後の高さを増
すことを避けられないので、ＣＳＰの外観寸法に対する
要求に合致しにくい。また、チップ１０の裏面は熱硬化
性接着剤をもって基板に接着され、かつ、チップ１０と
基板５０間の熱膨脹の差異によって発生する接着面の応
力を有効に低減することができず、くり返しに発生する
熱応力によって破壊してしまう。更に、パッケージの過
程に使用される基板５０は両面板であり、それの上、下
表面の導通には孔開け、メッキ、孔封じ、孔封じ後の研
磨処理等を経なければならなく、そのために基板の製造
コストは増大してしまい、かつ孔開け導通法はかなり大
きい面積を占してしまうので、配線及び球状格子配列の
接点に植球する面積が減少してしまう。Although such a method occupies a smaller area than the above-described lead frame packaging method, it is inevitable that the circuit of the connection line 30 extending to the upper side of the chip 10 increases the height after packaging. It is difficult to meet the requirements for external dimensions. In addition, the back surface of the chip 10 is bonded to the substrate with a thermosetting adhesive, and the stress on the bonding surface generated due to the difference in thermal expansion between the chip 10 and the substrate 50 cannot be reduced effectively. Destroyed by the applied thermal stress. Further, the substrate 50 used in the package process is a double-sided plate, and the conduction of the upper and lower surfaces thereof must be perforated, plated, sealed, and polished after sealing the holes. In addition, the manufacturing cost of the substrate is increased, and the hole conduction method occupies a considerably large area, so that the area of the wiring and the contact area of the spherical grid array is reduced.
【０００８】[0008]
【発明が解決しようとする課題】本発明は半導体ＩＣ回
路チップのパッケージ技術に関するもので、パッケージ
後は製品の体積が小さく、信頼性が良くなり、パッケー
ジの過程は一貫かつ完全であるメリットがあり、なおか
つそれは低コスト、低汚染性の製造過程であり、高い産
業利用性のあるパッケージ法を提供しようとするもので
ある。SUMMARY OF THE INVENTION The present invention relates to a semiconductor IC circuit chip packaging technology, which has the advantages that the volume of a product after packaging is small, the reliability is improved, and the packaging process is consistent and complete. Yet, it is a low cost, low pollution manufacturing process which seeks to provide a packaging process with high industrial applicability.
【０００９】[0009]
【課題を解決するための手段】本発明による開口型球状
格子配列パッケージ技術の製造法は、主としてパッケー
ジ時、チップをフェイスダウンにして基板と接着し、接
続線の回路をチップと基板の間に置いてパッケージの高
さを大幅に減らすことができる。基板は孔開け、メッ
キ、孔封じ、研磨処理等をしなくても良い片面通路板が
使用されるので基板の製造コストは低減することがで
き、かつ基板製造過程中のメッキによって発生する汚染
を減らすことができる。SUMMARY OF THE INVENTION A method of manufacturing an open-type spherical lattice array package technology according to the present invention mainly includes a step of bonding a chip face down and bonding to a substrate during packaging, and connecting a circuit of connection lines between the chip and the substrate. The height of the package can be greatly reduced. Since the substrate uses a single-sided passage plate that does not need to be perforated, plated, sealed, and polished, the production cost of the substrate can be reduced, and contamination caused by plating during the substrate production process can be reduced. Can be reduced.
【００１０】本発明の開口型球状格子配列パッケージ技
術の製造法は、半導体ＩＣ回路のチップのパッケージ技
術であり、それは主として片面通路の基板を使用し、チ
ップの接続脚のある面を基板の特定箇所に置いて位置を
正確にし、熱可塑性接着剤から作られた接着ドライフィ
ルムをもって基板に接着し、加熱加圧した後接続線を連
結し、接続線回路を基板の開口に通して基板と通路がで
きるようにする。更にパッケージ物資をもってチップの
周囲をパッケージし、かつ基板の下側に於いて球状格子
配列の接点の植球作業を行い、パッケージの過程を完成
する。The method of manufacturing the open-type spherical grid array package technology of the present invention is a semiconductor IC circuit chip packaging technology, which mainly uses a substrate having a single-sided passage, and specifies a surface of a chip connecting leg with a substrate. Place it on the place to make it accurate, glue it to the board with an adhesive dry film made of thermoplastic adhesive, connect it by heating and pressurizing, connect the connecting wire, pass the connecting wire circuit through the opening of the board and the passage with the board To be able to Further, the package material is packaged around the chip, and the contacting operation of the spherical lattice arrangement is performed on the lower side of the substrate to complete the packaging process.
【００１１】接続線回路はチップと基板の間に置いてい
るので、パッケージの高さを大幅に低下することがで
き、パッケージの製品は軽薄短小の特性をもつことがで
きる。また、チップと基板の接着には熱可塑性接着剤を
使用しているので熱膨脹から起る接着面の応力が減少
し、接着箇所の破壊が防止されて製品の信頼性が高めら
れ、かつ基板に使われている片面通路板は製造コストと
メッキによる汚染を減少することができ、それはまさに
パッケージ後は体積が減少し、製品は良い信頼性を持
ち、パッケージ過程は一貫かつ完全であり、低コスト、
低汚染のＩＣ回路パッケージの製造過程であると云え
る。[0011] Since the connection line circuit is placed between the chip and the substrate, the height of the package can be greatly reduced, and the package product can have light, thin and short characteristics. In addition, since the chip and substrate are bonded using a thermoplastic adhesive, the stress on the bonding surface caused by thermal expansion is reduced, preventing breakage of the bonded part, improving product reliability, and improving the reliability of the substrate. The single-sided passage plate used can reduce the manufacturing cost and the pollution due to plating, which is exactly the same after packaging, the volume is reduced, the product has good reliability, the packaging process is consistent and complete, low cost ,
It can be said that this is a manufacturing process of a low-contamination IC circuit package.
【００１２】[0012]
【発明の実施の形態】図３に示すのは本発明を応用して
パッケージした周縁接点式ＩＣ回路の製品の側面断面図
であり、図４は本発明のフローダイアグラムである。FIG. 3 is a side sectional view of a peripheral contact type IC circuit product packaged by applying the present invention, and FIG. 4 is a flow diagram of the present invention.
【００１３】先ず、図３からパッケージ製品の主な構造
が見られるが、その中、基板５０は片面板であり、それ
はＢ.Ｔ.(Ｂismaleimide Ｔriazine)・ポリイミド・テ
ープ、またはその他の同様な樹脂から製成される。この
基板の導通方法は孔開け、メッキ、孔封じ、孔封じ後の
研磨等作業を必要としないので、基板製作のコストを下
げることができる。チップ１０はフェイスダウンにして
基板５０に接着され、それの周囲はパッケージ物質４０
をもってパッケージしているのでチップ１０の接続脚は
基板５０に面する。接続脚はチップ１０の両側周縁に位
置するのでこの方法を「周縁接点式ＩＣ回路（Ｐeriphe
ral Ｐad ＩＣ)」と称し、チップ１０の接続脚に相対す
る基板５０には接続線３０を通すための開口が設けられ
てある。チップ１０と連接する接続脚は基板５０下側の
球状格子配列接点６０に位置して接続通路が構成されて
いるのですべての接続線３０回路はチップ１０と基板５
０の間に位置し、そのためにそれが占有する面積は小さ
く、ＣＳＰの外観寸法の要求に合致することができる。First, the main structure of the package product can be seen from FIG. 3, in which the substrate 50 is a single-sided board, which is made of BT (Bismaleimide Triazine), polyimide tape or other similar resin. It is produced from. This method of conducting the substrate does not require operations such as drilling, plating, sealing the hole, and polishing after sealing the hole, so that the cost of manufacturing the substrate can be reduced. The chip 10 is bonded face down to the substrate 50, and a package material 40 is provided around the chip 10.
Therefore, the connection leg of the chip 10 faces the substrate 50. Since the connection legs are located on both sides of the chip 10, this method is referred to as "peripheral contact type IC circuit (Periphe
ral Pad IC), and an opening for passing the connection line 30 is provided in the substrate 50 facing the connection leg of the chip 10. The connection legs connected to the chip 10 are located at the spherical grid array contacts 60 under the substrate 50 to form connection paths, so that all the connection lines 30 are connected to the chip 10 and the substrate 5.
0, so it occupies a small area and can meet the CSP's external dimensions requirements.
【００１４】この外、本発明のチップ１０と基板５０の
間に用いられる接着剤は熱可塑性接着剤であるため、チ
ップ１０と基板５０の間の熱膨脹の差異による接着面の
応力を大幅に低減して破壊を防ぐことができ、それによ
って製品の信頼性を高めることができる。図４は本発明
のフローダイアグラムを示しており、それは次のステッ
プを含む。In addition, since the adhesive used between the chip 10 and the substrate 50 of the present invention is a thermoplastic adhesive, the stress on the bonding surface due to the difference in thermal expansion between the chip 10 and the substrate 50 is greatly reduced. Damage can be prevented, thereby increasing the reliability of the product. FIG. 4 shows a flow diagram of the present invention, which includes the following steps.
【００１５】(1) １枚の基板を取り、その基板には予め
チップの接着箇所が計画され、かつチップ両側の接続脚
に対応する箇所には開口が設けられてある。 (2) 熱可塑性接着剤で作られた接着ドライフィルムを接
着剤とする。 (3) ステップ(2)の接着ドライフィルムを基板のチップ
接着箇所に貼り付け、熱を加えて接着性があるようにす
る。 (4) ユニットに分割されたチップを取り出す。 (5) 接続脚のあるチップの面を基板上の特定箇所に置
き、位置を正確にする。 (6) 加熱加圧する。 (7) 接続線を連結する。 (8) 接続線回路を基板の開口に通し、かつ基板と通路が
できるように接続する。 (9) モルディングする。 (10) 基板の下側に於いて球状格子配列の接点の植球作
業を行う。(1) A single substrate is taken, a chip bonding portion is planned on the substrate in advance, and openings are provided at positions corresponding to the connection legs on both sides of the chip. (2) An adhesive dry film made of a thermoplastic adhesive is used as the adhesive. (3) Attach the adhesive dry film of step (2) to the chip bonding portion of the substrate and apply heat to make it adhesive. (4) Take out the chips divided into units. (5) Place the surface of the chip with connection legs at a specific location on the board to make the position accurate. (6) Heat and pressurize. (7) Connect the connection lines. (8) Pass the connection line circuit through the opening in the board and connect it to the board so that a passage is formed. (9) Mold. (10) Perform a ball-planting operation of the contacts in a spherical lattice array on the lower side of the substrate.
【００１６】以上のステップを得ると図３に示すパッケ
ージ製品が完成される。When the above steps are obtained, the package product shown in FIG. 3 is completed.
【００１７】図５は本発明の製造過程を応用して完成し
た別の形式のＩＣ回路パッケージを示す図で、図３のも
のと違うところは、チップの接続脚がチップの中央位置
にあり、かつ直線配列になるので「中央直配列接点式Ｉ
Ｃ回路（ＬＯＣ Ｐad ＩＣ）」と称し、その中ＬＯＣ
（Ｌead on Ｃhip）パッケージ法はＤＲＡＭのパッケー
ジに良く見られる。図６に示す製造過程は図４と同じ
で、唯一つ違うところは基板上のチップの接続脚に合せ
て設けられた開口がチップの中央にあるだけで、その他
ステップはすべて同じく、それは本発明の別の形式の応
用である。FIG. 5 is a view showing another type of IC circuit package completed by applying the manufacturing process of the present invention. The difference from FIG. 3 is that the connection legs of the chip are located at the center of the chip. In addition, since it is a linear array,
C circuit (LOC Pad IC) "
The (Lead on Chip) package method is often found in DRAM packages. The manufacturing process shown in FIG. 6 is the same as that of FIG. 4 except that the opening provided for the connection leg of the chip on the substrate is only at the center of the chip, and all other steps are the same as those of the present invention. Is an application of another form of.
【図１】従来のパッケージ法によってパッケージされた
製品の側面断面図である。FIG. 1 is a side sectional view of a product packaged by a conventional packaging method.
【図２】別のパッケージ法によってパッケージされた製
品の側面断面図である。FIG. 2 is a side sectional view of a product packaged by another packaging method.
【図３】本発明を応用してパッケージした周縁接点式Ｉ
Ｃ回路の製品の側面断面図である。FIG. 3 shows a peripheral contact type I packaged by applying the present invention.
It is side surface sectional drawing of the product of C circuits.
【図４】開口型球状格子配列周縁接点式ＩＣ回路（Ｗin
dow-ＢＧＡ for ＰeripheralＰad ＩＣ）パッケージ法
のフローダイアグラムである。FIG. 4 is an open type spherical lattice array peripheral contact type IC circuit (Win
It is a flow diagram of a dow-BGA for Peripheral Pad IC) package method.
【図５】本発明を応用してパッケージした中央直配列接
点式ＩＣ回路の製品の側面断面図である。FIG. 5 is a side cross-sectional view of a product of a central direct-sequence contact type IC circuit packaged by applying the present invention.
【図６】開口型球状格子配列中央直配列接点式ＩＣ回路
（Ｗindow-ＢＧＡ for ＬＯＣＰad ＩＣ）パッケージ法
のフローダイアグラムである。FIG. 6 is a flow diagram of a package method of a contact type IC circuit (Windows-BGA for LOCPad IC) having an aperture type spherical lattice array and a central direct array.
１０ チップ ２０ リードフレーム ３０ 接続線 ４０ パッケージ物質 ５０ 基板 ６０ 球状格子配列接点 ７０ 熱硬化性接着剤 ７１ 熱可塑性接着剤 DESCRIPTION OF SYMBOLS 10 Chip 20 Lead frame 30 Connection line 40 Package material 50 Substrate 60 Spherical lattice arrangement contact 70 Thermosetting adhesive 71 Thermoplastic adhesive
───────────────────────────────────────────────────── フロントページの続き (71)出願人 598081182 10Ｆ−３， Ｎｏ．458， Ｋｗａｎｇ Ｆｕ Ｓｏｕｔｈ Ｒｏａｄ， Ｔａｉｐ ｅｉ， Ｔａｉｗａｎ， Ｒ．Ｏ．Ｃ. (71)出願人 598081193 ４Ｆ， Ｎｏ．５， Ａｌｌｅｙ ６， Ｌａｎｅ 394， Ｃｈｕｎｇ Ｃｈｅｎ Ｎ． Ｒｄ．， Ｔａｉｐｅｉ Ｈｓｉ ｅｎ， Ｔａｉｗａｎ， Ｒ．Ｏ．Ｃ. (71)出願人 598081207 ホー、 クオ − テー Ｈｏ， Ｋｕｏ−Ｔｅｈ 台湾、タイワン、タイペイ、セクション １、キールン ロード、レーン 35、アレ ー ７ 、ナンバー １−３、５エフ ５Ｆ， Ｎｏ． １−３， Ａｌｌｅｙ ７， Ｌａｎｅ 35， Ｋｅｅｌｕｎｇ Ｒｏａｄ， Ｓｅｃ． １， Ｔａｉｐｅ ｉ， Ｔａｉｗａｎ， Ｒ．Ｏ．Ｃ. (71)出願人 598081218 リー、 ジャッキー Ｌｅｅ， Ｊａｃｋｙ 台湾、タイワン、タイペイ セン、ロク チョウ、チュウ チン ロード、 レーン 59、アレー 12、ナンバー ３、１エフ １Ｆ， Ｎｏ．３， Ａｌｌｅｙ 12， Ｌａｎｅ 59， Ｃｈｕｎｇ Ｃｈｅｎ Ｒｄ．， Ｌｕ Ｃｈｏｗ， Ｔａｉｐｅ ｉ Ｈｓｉｅｎ， Ｔａｉｗａｎ， Ｒ. Ｏ．Ｃ. (72)発明者 マ、 チュウ − ニン 台湾、タイワン、タイペイ、クワン フ サウス ロード、ナンバー 458、10エフ −３ (72)発明者 ビア、 ジン − チュアン 台湾、タイワン、タイペイ セン、チュウ チン エヌ ロード、レーン 394、ア レー ６、ナンバー ５、４エフ (72)発明者 ホー、 クオ − テー 台湾、タイワン、タイペイ、セクション １、キールン ロード、レーン 35、アレ ー ７ 、ナンバー １−３、５エフ (72)発明者 リー、 ジャッキー 台湾、タイワン、タイペイ セン、ロク チョウ、チュウ チン ロード、 レーン 59、アレー 12、ナンバー ３、１エフ ──────────────────────────────────────────────────続 き Continuation of front page (71) Applicant 598081182 10F-3, No. 458, Kwang Fu South Road, Taiei, Taiwan, R.A. O. C. (71) Applicant 598081193 4F, No. 5, Alley 6, Lane 394, Chung Chen N. et al. Rd. , Taipei Hsien, Taiwan, R .; O. C. (71) Applicant 598081207 Ho, Kuo-Theh Taiwan, Taiwan, Taipei, Section 1, Keelung Road, Lane 35, Array 7, Numbers 1-3, 5F 5F, No. 1-3, Alley 7, Lane 35, Keelung Road, Sec. 1, Taipe i, Taiwan, R.A. O. C. (71) Applicant 598081218 Lee, Jackie Lee, Jacky Taiwan, Taiwan, Taipei Sen, Lok Chow, Chu Chin Road, Lane 59, Array 12, Number 3, 1F 1F, No. 3, Alley 12, Lane 59, Chung Chen Rd. , Lu Chow, Taipei Hsien, Taiwan, R.O. C. (72) Inventors Ma, Chu-Nin Taiwan, Taipei, Taipei, Kwanfu South Road, Number 458, 10F-3 Road, Lane 394, Array 6, Number 5, 4F (72) Inventor Ho, Quote Taiwan, Taiwan, Taipei, Section 1, Keelung Road, Lane 35, Array 7, Number 1-3, 5F (72) Inventor Lee, Jackie Taiwan, Taiwan, Taipei, Taipei, Lok Chow, Chu Chin Road, Lane 59, Array 12, Number 3, 1F
Claims (1)
性が良くなり、パッケージの過程は一貫かつ完全である
メリットがあり、かつそれは低コスト、低汚染性ＩＣ回
路のパッケージ製造過程である半導体ＩＣ回路のチップ
のパッケージ法であって、 片面通路の基板に予めチップ貼り付け箇所を計画し、か
つチップの接続脚に対応する箇所に開口を設け、その開
口はチップの両側周縁または中央にあっても良いこと
と、 熱可塑性接着剤で作られた接着ドライフィルムを接着剤
とし、かつこの接着ドライフィルムを基板のチップ接着
箇所に貼り付け、更に熱を加えて接着性があるようにす
ることと、 ユニットに分割されたチップの接続脚のある面を基板上
の特定箇所に置き、かつ位置を正確にして基板と接着す
ることと、 加熱加圧した後、接続線を連結し、接続線回路を基板の
開口に通して基板と通路ができるようにすることと、 パッケージ物質をもってチップの周囲をパッケージし、
かつ基板の下側に於いて球状格子配列の接点の植球作業
を行い、パッケージの過程を完成することとから構成さ
れ、 全体的構造は接続線回路をチップと基板の間に置いてい
るのでパッケージの高さを大幅に低下することができ、
パッケージの製品は軽薄短小の特性をもつことができ、
またチップと基板の接着には熱可塑性接着剤が使われて
いるので熱膨脹から起る接着面の応力が減少されて製品
の信頼性が高められ、かつ基板は片面通路板を使用して
いるので、製造コストとメッキによる汚染を減少するこ
とができることを特徴とする開口型球状格子配列パッケ
ージ技術の製造方法。1. A semiconductor IC which has a merit that the volume of a product after packaging is small, the reliability is improved, and the packaging process is consistent and complete, and is a low cost, low pollution IC circuit package manufacturing process. A method of packaging a chip of a circuit, in which a chip attachment position is planned in advance on a substrate having a single-sided passage, and an opening is provided at a position corresponding to a connection leg of the chip. The good thing is that the adhesive dry film made of thermoplastic adhesive is used as the adhesive, and this adhesive dry film is attached to the chip bonding part of the board, and further heat is applied to make it adhesive. The surface of the chip divided into units with the connection legs is placed at a specific location on the board, and the position is adjusted accurately and adhered to the board. Connecting the line, the periphery of the chip package with a possible to allow the substrate and the passageway, the package material connection line circuit through the opening of the substrate,
And, on the lower side of the board, the work of planting the contacts of the spherical lattice array is completed, and the process of packaging is completed.The overall structure is because the connection line circuit is placed between the chip and the board The height of the package can be greatly reduced,
Package products can have light, thin and small characteristics,
In addition, since a thermoplastic adhesive is used to bond the chip and the substrate, the stress on the bonding surface caused by thermal expansion is reduced and the reliability of the product is improved, and the substrate uses a single-sided passage plate. A method of manufacturing an open-type spherical lattice array package technology, which can reduce manufacturing cost and contamination due to plating.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17205998A JPH11354577A (en) | 1998-06-05 | 1998-06-05 | Manufacture on opened spheric lattice array package technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17205998A JPH11354577A (en) | 1998-06-05 | 1998-06-05 | Manufacture on opened spheric lattice array package technology |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11354577A true JPH11354577A (en) | 1999-12-24 |
Family
ID=15934783
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17205998A Pending JPH11354577A (en) | 1998-06-05 | 1998-06-05 | Manufacture on opened spheric lattice array package technology |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11354577A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6339260B1 (en) * | 1999-03-09 | 2002-01-15 | Hyundai Electronics Industries Co., Ltd. | Wire arrayed chip size package |
| CN100364087C (en) * | 2002-08-30 | 2008-01-23 | 日本电气株式会社 | Semiconductor device and its mfg. method, circuidboard, electronic device and apparatus for mfg. semiconductor device |
-
1998
- 1998-06-05 JP JP17205998A patent/JPH11354577A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6339260B1 (en) * | 1999-03-09 | 2002-01-15 | Hyundai Electronics Industries Co., Ltd. | Wire arrayed chip size package |
| US6489182B2 (en) | 1999-03-09 | 2002-12-03 | Hynix Semiconductur, Inc. | Method of fabricating a wire arrayed chip size package |
| CN100364087C (en) * | 2002-08-30 | 2008-01-23 | 日本电气株式会社 | Semiconductor device and its mfg. method, circuidboard, electronic device and apparatus for mfg. semiconductor device |
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