JPH11354447A - Production method of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means for efficiently eliminating a catalyst element required for crystallization from a polysilicon film having high crystallinity and uniformity. SOLUTION: After completing the process of crystallization, vicinities of the surface of a mask 104 and a nickel-doped area 106 are cleaned by hydrofluoric treatment. After that, a thin oxidized silicon film 108 is formed on the nickel- doped area 106. In addition, an amorphous silicon film 109 which has N-type conductivity is formed on the oxidized silicon film 108. When a gettering process has been completed, only the amorphous silicon film 109 having N-type conductivity is optionally eliminated. At that time, the thin oxidized silicon film 108 functions as an etching stopper.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a method for manufacturing a thin film transistor (hereinafter, referred to as a TFT) using a semiconductor thin film, and can be applied to a semiconductor device including a semiconductor circuit formed using a TFT. Technology.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, such as an electro-optical device represented by a liquid crystal display device, a semiconductor circuit in which a TFT is integrated, Such electronic engineering devices and electronic devices including semiconductor circuits as components are also included in the category.

[0003]

2. Description of the Related Art In recent years, a TFT is formed on a glass substrate, and a circuit is formed using the TFT to form a liquid crystal display device or an E.
Attempts have been made to perform j driving of an L display device or the like. In particular, as a TFT active layer, a polysilicon film having high carrier mobility has been attracting attention.

As a technique for forming a polysilicon film on a glass substrate, a technique for crystallizing an amorphous silicon film by annealing with an excimer laser is generally known. However, laser annealing has difficulty in uniformity, and it has been difficult to obtain a polysilicon film having uniform crystallinity.

The present applicant has disclosed Japanese Patent Application Laid-Open No. Hei 7-130652 as a means for obtaining a polysilicon film having high crystallinity and uniformity.
Discloses a technique described in Japanese Patent Application Laid-Open Publication No. HEI 10-209 (1995). In that publication,
A catalytic element (typically, nickel) for promoting crystallization is added to the amorphous silicon film, and 550 to 600
It discloses a technique for performing crystallization at a relatively low temperature of ° C.

[0006] The polysilicon film formed by using the above publication is characterized by having extremely high crystallinity and excellent uniformity. However, there is a concern that the influence of the catalyst element remaining in the polysilicon film may occur. That is, when driving the TFT, a phenomenon in which the catalyst element moves to cause a local increase in off-state current (or leak current) was sometimes observed.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and is intended to effectively remove a catalyst element required for crystallization from a polysilicon film having high crystallinity and uniformity. Means are provided.

[0008]

SUMMARY OF THE INVENTION The invention disclosed in the present specification comprises a step of forming a mask having an opening on an amorphous silicon film formed on a substrate having an insulating surface; A step of applying a solution containing a catalytic element that promotes the above by a spin coating method, a step of performing a first heat treatment and crystallizing a part of the amorphous silicon film to form a polysilicon film, and an etching treatment. Exposing the polysilicon film to the bottom of the opening; forming a silicon oxide film on the surface of the polysilicon film exposed to the bottom of the opening; Forming an amorphous silicon film having N-type conductivity and performing a second heat treatment on the amorphous silicon film having N-type conductivity. A step of serial getter the catalytic element, and having a step of removing the amorphous silicon film having the N-type conductivity.

Another aspect of the present invention is a process for forming a mask having an opening on an amorphous silicon film formed on a substrate having an insulating surface, and a thin film made of a catalytic element for promoting crystallization of silicon. Forming a polysilicon film by performing a first heat treatment, crystallizing a part of the amorphous silicon film to form a polysilicon film, and performing an etching process to form the silicon crystallization. Removing a thin film made of a promoting catalytic element and exposing the polysilicon film to the bottom of the opening; and forming a silicon oxide film on the surface of the polysilicon film exposed to the bottom of the opening. Forming an amorphous silicon film having N-type conductivity on the mask and the silicon oxide film; and performing a second heat treatment,
A step of gettering the catalyst element in the amorphous silicon film having the n-type conductivity and a step of removing the amorphous silicon film having the n-type conductivity.

The gist of the present invention is to utilize an amorphous silicon film having N-type conductivity as a gettering site when removing the catalyst element from a polysilicon film crystallized using the catalyst element. is there.
At this time, it is important to provide a thin silicon oxide film as an etching stopper so that the underlying polysilicon film is not etched when the amorphous film having N-type conductivity is removed by etching.

In the above structure, the catalyst element that promotes crystallization of silicon is typically nickel, palladium, tin, lead, or cobalt. In addition, germanium, iron, platinum, gold, and cadmium may be used.

In the above structure, the second heat treatment is performed at 550 to 750 ° C. (preferably 600 to 650 ° C.).
(° C.). At 550 ° C. or lower, the gettering effect is weak. At 750 ° C. or higher, diffusion of impurities (typically, phosphorus) imparting N-type conductivity to the amorphous silicon film cannot be ignored, and impurities in the polysilicon film are more than necessary. This is undesirable because it will diffuse.

In the above structure, it is preferable that the amorphous silicon film having the N-type conductivity has 1 × 10 ¹⁸ atoms. Below this concentration, catalytic elements are not

In the above structure, the step of removing the amorphous silicon film having N-type conductivity may be performed by a dry etching method using a halogen-based gas (specifically, ClF ₃ gas). The etching selectivity with the dry siliconized film can be increased.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described.
A detailed description will be given with reference to the following embodiments.

[0016]

(Embodiment 1) An embodiment of the present invention will be described with reference to FIG. First, a substrate 10 having an insulating surface
As 1, a glass substrate provided with a base film made of a silicon oxide film is prepared. Of course, not limited to a glass substrate, a quartz substrate, a silicon substrate, or the like may be used.

Next, an amorphous silicon film 102 is formed on the substrate 101. As a film formation method, a reduced pressure thermal CVD method, a plasma CVD method, or a sputtering method may be used. The film thickness is 10
What is necessary is just to select suitably from the range of 100 nm. Note that other amorphous semiconductor films such as a silicon germanium film other than amorphous silicon may be used.

Next, the amorphous silicon film 102
Is crystallized, and here, JP-A-7-13065 is used.
The technique described in Japanese Patent Publication No. 2 is used.

First, a silicon oxide film (not shown) is formed on the amorphous silicon film 102 and is patterned to form a mask 104 having an opening 103. The opening 103 functions as a starting point for crystal growth later.

Next, a solution containing a catalytic element for promoting crystallization of silicon (a nickel acetate solution containing 10 ppm of nickel in this embodiment) is applied by a spin coating method to form a nickel-containing layer 105. . When the solution to be applied is an aqueous solution, it is preferable to form a thin silicon oxide film on the amorphous silicon film 102 and hold the nickel element in a state of being adsorbed on the oxide film.

Thus, the state shown in FIG. 1A is obtained. Next, furnace annealing at 570 ° C. for 14 hours (first
Is performed, and a part of the amorphous silicon film is crystallized. The crystal growth starts from the nickel-added region 106 (crystallized into a polysilicon film).
It proceeds in a direction substantially parallel to the substrate.

The present applicant refers to such a crystal growth mode as lateral growth, and the crystal region 107 made of the polysilicon film formed in this manner is referred to as a lateral growth region. Since the lateral growth region 107 thus formed is an aggregate of rod-like crystals macroscopically grown in a specific direction, the lateral growth region 107 should be a polysilicon film excellent in crystallinity with few factors that hinder carrier movement. I know. Further, since the concentration of nickel contained is lower than that in the nickel-added region, gettering efficiency is good later.

When the state shown in FIG. 1B is thus obtained, etching cleaning is performed with 1% diluted hydrofluoric acid to expose the polysilicon film (nickel-added region) at the bottom of the opening 103. In this step, the surface layer of the mask 104 containing nickel at a high concentration is removed, and further, the surface layer of the polysilicon film exposed in the nickel added region 106 is removed. At this time, the thin silicon oxide film on the surface of the polysilicon film used for adsorbing nickel is simultaneously etched and removed.

This step is performed to enhance the gettering efficiency later. In the state shown in FIG. 1 (B), nickel was in contact with the entire exposed surface, so that a very high concentration of nickel was present near the exposed surface. However, by performing etching cleaning with hydrofluoric acid, nickel in the surface layer can be removed to some extent.

After the etching cleaning with hydrofluoric acid is completed, a thin silicon oxide film 108 is formed on the surface of the polysilicon film exposed in the nickel-added region 106. As a formation method, a thermal oxidation method, an ultraviolet irradiation method, or a chemical oxidation method (eg, oxidation with ozone or hydrogen peroxide solution) can be used. The silicon oxide film formed here is a silicon oxide film that later functions as an etching stopper, and has a completely different meaning from the silicon oxide film for adsorbing nickel formed on the surface of the amorphous silicon film.

The thickness of the thin silicon oxide film 108 may be 1 to 10 nm (typically 3 to 5 nm).
In short, it only has to function as an etching stopper later, and if the etching selectivity is high, it is 1 to 10
Even a film thickness of about nm has a sufficient effect. When the above-described ultraviolet irradiation method or the like is used, a thin silicon oxide film having a thickness of about 3 to 5 nm is formed, but under the conditions of the present embodiment, it sufficiently functions as an etching stopper.

Next, the mask 104 and the thin oxide film 108
Amorphous silicon film 10 having N-type conductivity on
9 is formed. In this embodiment, the film thickness is set to 200 nm.
It is not necessary to limit to this. In this embodiment, phosphorus is used as an impurity element imparting N-type conductivity. Another one
It is possible to use an element belonging to Group 5 (arsenic, antimony, etc.), but phosphorus has the highest effect of gettering nickel.

The concentration of phosphorus contained in the amorphous silicon film 109 having N-type conductivity is 1 × 10 ¹⁹ atom × 10
¹⁹ to 1 × 10 ²¹ atoms / cm ³ ) is desirable. This is because of the following.

In the case of this embodiment, the lateral growth region 107
Contains nickel at a concentration of about 5 × 10 ¹⁸ atoms / cm ³
6 contains nickel at a concentration of about 1 × 10 ¹⁹ atoms / cm ³ . It is preferable that the amorphous silicon film 109 having N-type conductivity has a concentration of about 10 to 100 times the nickel concentration contained in the sub polysilicon film.

Thus, the state shown in FIG. 1C is obtained. Next, furnace annealing at 550 to 750 ° C. (second
Heat treatment) for 0.5 to 12 hours.
The nickel remaining in 7 is gettered in amorphous silicon film 109 having N-type conductivity. The moving direction of the nickel is as indicated by the arrow.

In this way, the lateral growth region 110 having a significantly reduced nickel concentration is formed. This lateral growth region 110
The nickel content is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less

At this time, the gettering ability of the amorphous silicon film 109 having N-type conductivity is affected by the nickel concentration to be gettered. That is, when compared at the same phosphorus concentration, the higher the nickel concentration to be gettered, the lower the gettering ability tends to be. In that sense, it can be said that the above-described surface cleaning with hydrofluoric acid is effective in reducing the concentration of nickel to be gettered.

Further, by keeping the mask 104 consistently from the crystallization step to the gettering step, the lateral growth region 107 is formed.
Each step can be performed without deteriorating the surface state of (or the lateral growth region 110) as much as possible. In the present invention, since the lateral growth region is a region to be an active layer of the TFT,
Careful attention must be paid to the surface condition.

After the gettering step shown in FIG. 3D is completed, the amorphous silicon film 109 having N-type conductivity is removed. In this embodiment, ClF ₃ gas is used as an etching gas.
The thin silicon oxide film 108 functions as an etching stopper.

After only the amorphous silicon film 109 having N-type conductivity is selectively removed by etching, a mask 104 and a thin silicon oxide film are formed using an etchant such as buffered hydrofluoric acid which is suitable for etching the silicon oxide film. The film 108 is removed.

Then, the exposed polysilicon film is patterned to form an active layer 1 comprising only the lateral growth region 110.
11 is formed. In practice, a plurality of active layers are formed on a substrate. At this time, it is preferable that the nickel-added region 106 is not used as the active layer because the crystallinity of the nickel-added region 106 is not as high as the lateral growth region.

Thus, an active layer made of a polysilicon film whose crystallization is promoted by utilizing the catalytic action of nickel is obtained. This active layer has extremely high crystallinity and is extremely effective in realizing excellent TFT characteristics (low off-current, high mobility). Moreover, by performing the gettering of the catalytic element, a highly reliable TFT with little variation in TFT characteristics can be obtained. By assembling a circuit using such a TFT, a semiconductor device having high functionality and high reliability can be realized.

The provision of the thin silicon oxide film 108 as an etching stopper in this embodiment has a very important meaning. This will be described with reference to FIG.

FIG. 2A shows an example in which an etching step of an amorphous silicon film having N-type conductivity is performed without forming an etching stopper. As shown in FIG. 2A, when an amorphous silicon film (not shown) having N-type conductivity is etched, the polysilicon film (not shown) which was the nickel-added region is also etched as it is, and the underlying surface ( An opening 202 reaching the surface of the substrate 201 having an insulating surface) is formed. Since the opening 202 is formed in a self-aligned manner by the mask 104, its diameter matches the diameter of the opening provided in the mask 104.

After removing the amorphous silicon film having N-type conductivity, the mask 104 is removed next. The material of the mask 104 is a silicon oxide film, and the outermost surface of the substrate 201 having an insulating surface is oxidized. In the case of a silicon film, the outermost surface of the substrate 201 having an insulating surface is also etched simultaneously with the etching of the mask 104.

As a result, the concave portion 20 as shown in FIG.
3 is formed. Since the location where the concave portion 203 is formed is a portion not used as an active layer, it does not directly affect the TFT characteristics. However, when a wiring or the like crosses this portion, a disconnection failure due to a step may occur. Therefore, it is desirable that such a step is not formed as much as possible.

In this sense, forming a thin silicon oxide film as an etching stopper in advance before forming an amorphous silicon film having N-type conductivity as in this embodiment increases the reliability of the semiconductor circuit. This is a very effective tool.

In this embodiment, the TF of any known structure is used.
Applicable to T. That is, the present invention can be easily applied to a top gate structure represented by a coplanar TFT and a bottom gate structure represented by an inverted staggered TFT.

(Embodiment 2) In Embodiment 1, the present invention can be implemented even if the amorphous silicon film having dry conductivity using ClF ₃ gas is removed from the amorphous silicon film having N-type conductivity by wet etching. It is possible.

To etch a silicon film by a wet etching method, hydrazine may be used as an etchant. Hydrazine also has a high etching selectivity between the silicon oxide film and the silicon film, so that only the amorphous silicon film having N-type conductivity can be selectively removed.

In this embodiment, the TF of any known structure is used.
Applicable to T. That is, the present invention can be easily applied to a top gate structure represented by a coplanar TFT and a bottom gate structure represented by an inverted staggered TFT.

(Embodiment 3) In this embodiment, a case of manufacturing a TFT using the active layer formed by the manufacturing steps of Embodiment 1 or Embodiment 2 will be described with reference to FIGS.

First, after the active layer 301 is formed in the manufacturing steps shown in the embodiment or the embodiment 2, a gate insulating film 302 made of a silicon oxide film is formed. In this embodiment, the plasma
It is formed to a thickness of 120 nm by a CVD method. Subsequently,
Gate electrode 30 made of aluminum-based material
Form 3

[0049] Here, Japanese Patent Application Laid-Open No.
The technology described in Japanese Patent Publication No. 18 is used. In this publication, an LDD + offset structure is realized by anodizing a gate electrode mainly composed of aluminum. The LDD region is formed by etching a part of the gate insulating film using an anodic oxide film and adding an impurity element (impurities forming the source region and the drain region) using the remaining gate insulating film as a mask. You.

FIG. 3B shows a structure obtained by utilizing the technique described in the publication. 304 is a gate electrode, and 305 is a barrier type anodic oxide film for protecting the gate electrode. 306 is a gate insulating film, 307 is a source region, 30
8 is a drain region, 309 is an LDD region, and 310 is a channel formation region.

Although not shown, an offset region is formed between the LDD region 309 and the channel forming region 310. However, since the thickness of the barrier type anodic oxide film 305 determines the width of the offset region, the anodic oxide film 305
If the film thickness is less than 150 nm, it hardly functions as an offset region.

In this embodiment, an N-channel TFT is manufactured using phosphorus as an impurity element for forming the source region 307, the drain region 308, and the LDD region 309. Of course, other Group 15 elements such as arsenic may be used, and if a Group 13 element represented by boron is added, a P-channel TFT can be easily manufactured.

When the state shown in FIG. 3B is obtained by using the technique described in JP-A-7-135318, a silicon oxide film having a thickness of 1 μm is formed as the interlayer insulating film 311. Needless to say, a silicon nitride film or a silicon oxynitride film may be used, or these insulating films may be stacked.

Next, a contact hole is formed in the interlayer insulating film 311 to form a source wiring 312 and a drain wiring 313 made of a material containing aluminum as a main component. Finally, the entire device is subjected to furnace annealing at 350 ° C. for 2 hours in a hydrogen atmosphere to complete hydrogenation.

Thus, a TFT as shown in FIG. 3C is obtained. The structure described in the present embodiment is an example, and the TFT structure to which the present invention can be applied is not limited to this. Therefore, the present invention can be applied to all known TFTs.

Of course, the present invention can be easily applied not only to the top gate structure but also to a bottom gate structure represented by an inverted staggered TFT.

Also, if a known means is used, a CMOS in which an N-channel TFT and a P-channel TFT are complementarily combined is used.
A circuit can be easily formed. Further, FIG.
If a pixel electrode (not shown) electrically connected to the drain wiring 313 is formed by known means in the structure of FIG. 3C, it is easy to form a pixel switching element of an active matrix display device.

That is, the present invention is a very effective technique as a method for manufacturing an electro-optical device such as a liquid crystal display device or an EL (electroluminescence) display device.

As described above, the present invention can be applied to a TFT having any structure.
And various semiconductor circuits can be constructed using the present invention. That is, the invention of the present application is TF
It can be said that the present invention can be applied to any semiconductor device including a semiconductor circuit formed with T.

[0060]

According to the present invention, it is possible to obtain a polysilicon film in which a catalytic element used for crystallization is effectively removed or reduced. And it has high electrical characteristics and reliability by using the polysilicon film as an active layer.
TFT can be realized.

Further, by forming a semiconductor circuit on a substrate using such a TFT, a high-performance and highly reliable electro-optical device and an electronic apparatus equipped with such an electro-optical device can be realized. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a view showing a process of manufacturing a polysilicon film according to the present invention.

FIG. 2 is a view showing a process of manufacturing a polysilicon film.

FIG. 3 illustrates a manufacturing process of a TFT.

Claims (7)

[Claims] 1. A step of forming a mask having an opening on an amorphous silicon film formed on a substrate having an insulating surface, and applying a solution containing a catalytic element for promoting crystallization of silicon by spin coating. Performing a first heat treatment to crystallize a part of the amorphous silicon film to form a polysilicon film; and performing an etching process to expose the polysilicon film at the bottom of the opening. Forming a silicon oxide film on the surface of the polysilicon film exposed at the bottom of the opening; and forming an amorphous silicon film having N-type conductivity on the mask and the silicon oxide film. Performing a second heat treatment to getter the catalytic element into the amorphous silicon film having the N-type conductivity; The method for manufacturing a semiconductor device characterized by having the steps of removing the amorphous silicon film having conductivity. 2. A step of forming a mask having an opening on an amorphous silicon film formed on a substrate having an insulating surface, and forming a thin film comprising a catalytic element for promoting crystallization of silicon by a gas phase method. Performing a first heat treatment, crystallizing a part of the amorphous silicon film to form a polysilicon film, and performing a etching process to form a thin film made of a catalytic element for promoting crystallization of silicon. Removing the polysilicon film at the bottom of the opening, forming a silicon oxide film on the surface of the polysilicon film exposed at the bottom of the opening, the mask and the silicon oxide A step of forming an amorphous silicon film having N-type conductivity on the film, and a second heat treatment to form a film in the amorphous silicon film having N-type conductivity. The method for manufacturing a semiconductor device, characterized in that it comprises a step of the catalytic element gettering, removing the amorphous silicon film having a N type conductivity, a. 3. The method for manufacturing a semiconductor device according to claim 1, wherein the catalyst element for promoting crystallization of silicon is nickel, palladium, tin, lead, or cobalt. 4. The method according to claim 1, wherein the second
Wherein the heat treatment is performed in a temperature range of 550 to 750 ° C. 5. An amorphous silicon film having N-type conductivity according to claim 1 or 2, wherein 1 × 10 ¹⁸
A method for manufacturing a semiconductor device, comprising a semiconductor device. 6. The semiconductor device according to claim 1, wherein the step of removing the amorphous silicon film having N-type conductivity is performed by a dry etching method using a halogen-based gas. Production method. 7. The semiconductor device according to claim 6, wherein the halogen-based gas is ClF ₃ gas.