JPH11352198A - Timing pulse generating circuit and semiconductor testing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a state in that a plurality of timing generating portions (TG) corresponding to one pin independently generate a timing within one period and a state avoiding a timing dead zone by interleaving a portion of the TG to other TG in a semiconductor testing device carrying out various test of an object, i.e., LSI. SOLUTION: A plurality of TG generating a timing pulse at the time responsive to a user's setting is provided. A waveform forming circuit 4 varying a pin output is provided every when the timing pulse is generated from a plurality of TG. A function portion 6 is provided so as to realize an interleave-off state in that all TG generate the timing pulse within the same period and an interleave-on state in that the odd number of TG generate the timing pulse within the same period and the even number of TG generate the timing pulse within a period subsequent to the period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing pulse generation circuit and a semiconductor test apparatus, and more particularly, to a timing pulse generation circuit suitable for executing various tests for LSIs, and a timing pulse generation circuit therefor. The present invention relates to a semiconductor test apparatus using a circuit.

[0002]

2. Description of the Related Art Conventionally, there has been known a semiconductor test apparatus which executes various tests using an LSI as a device to be measured.
FIG. 5 is a circuit diagram of a timing pulse generation circuit provided in a conventional semiconductor test apparatus. The conventional timing pulse generation circuit includes a reference signal generation unit 3. The reference signal generator 3 is a part that generates an internal reference signal of the semiconductor test device. In a semiconductor test apparatus, an execution cycle of a processing cycle is determined based on a reference signal.

The reference signal generator 3 includes a plurality of timing generators (TGs), more specifically, first to n-th T generators.
G, that is, n TGs are connected. The first to n-th TGs include first to n-th counters 1 and first to n-th verniers 2, respectively. The reference signals generated by the reference signal generator 3 are supplied to the first to n-th counters 1. On the other hand, the first to n-th verniers 2 are supplied with a reference signal (hereinafter, referred to as a delay reference signal) that has been subjected to a predetermined delay process and the output signals of the first to n-th counters 1.

The first to n-th counters 1 increment the count value based on the reference signal and reset the count value every cycle. Each of the first to n-th counters 1 can read the user's setting every period, and generate a timing pulse when the count value becomes a value corresponding to the setting. According to the first to n-th counters 1, by executing the above processing, it is possible to generate a coarse timing pulse corresponding to the setting of the user.

Each of the first to n-th verniers 2 performs an OR logic operation on the output pulses of the first to n-th counters 1 and the delay reference signal, and generates a desired timing pulse based on the signal obtained as a result. Occur. 1st to n-th vernier 2
Can read the user's settings every period and generate a timing pulse so that an edge that exactly matches the settings is obtained. According to the first to n-th verniers 2, by executing the above processing,
Each can generate a timing pulse that exactly corresponds to the user's settings.

The outputs of the first to n-th verniers, ie,
The outputs of the first to n-th TGs are supplied to the waveform forming circuit 4. The waveform forming circuit 4 is provided corresponding to one output pin. The waveform forming circuit 4 is a circuit that inverts a pin output every time a timing pulse is supplied from any of the first to nth TGs. In the timing pulse generation circuit shown in FIG. 15, the waveform supply circuit 4 can supply n timing pulses from the first to n-th TGs in one cycle. Therefore, according to the timing pulse generation circuit shown in FIG. 15, n timing pulses can be generated in one cycle.

The timing pulse output from the waveform forming circuit 4 is applied to one pin of the device under test or
It is supplied to a decision circuit built in the semiconductor test device. When the above timing pulse is supplied to one pin of the device under test, it is used, for example, as an address signal or a clock signal. On the other hand, when the timing pulse is supplied to the determination circuit, it is used as a signal for determining the timing for determining the output of the device under test.

In some cases, the semiconductor test apparatus is required to change the timing pulse generation timing in real time according to the content of the test to be executed. According to the semiconductor test apparatus shown in FIG.
By changing a command to the first to n-th verniers 2, that is, a setting by the user, the timing of generation of the timing pulse can be changed in real time.

In the conventional semiconductor test apparatus, the first to n-th counters 1 and the first to n-th verniers 2 read the user's settings every period, and read the timing pulse at a time corresponding to the settings. Occurs. For this reason, the first to n-th TGs start after one cycle,
While the setting of the timing data is completed, the timing pulse cannot be generated.

FIG. 16 shows a relationship between a period in which the above-mentioned state occurs (hereinafter, referred to as a timing dead zone) and a cycle of a processing cycle in a semiconductor test apparatus. In the conventional semiconductor test apparatus, a period indicated by hatching in FIG. 16 is a timing dead zone in all of the first to n-th TGs.

When it is required that the semiconductor test apparatus generate a timing pulse at high speed, the same TG
In contrast, a situation may occur in which the generation of a timing pulse is required immediately before the end of the cycle N and immediately after the start of the cycle N + 1. That is, a situation may occur in which the generation of the timing pulse indicated by the dashed line is required after the timing pulse indicated by the solid line in FIG.

However, when it is required to change the generation timing of the pulse in real time together with the generation of the pulse at the above-described timing, the latter pulse, that is, the timing at which the pulse indicated by the dashed line is to be generated is determined. Within the timing dead zone. Therefore, FIG.
In such a conventional semiconductor test apparatus, a desired timing pulse cannot be generated in such a situation.

FIG. 17 is a circuit diagram of a timing pulse generating circuit conventionally used to solve the problem of the timing dead zone. The timing pulse generation circuit illustrated in FIG. 17 includes first to (m + 1) th TGs (m
Is an odd number). The first to (m + 1) th TGs include first to (m + 1) th counters 1 and first to (m + 1) th verniers 2, respectively.

An enable circuit 5 is provided for each of the first to (m + 1) th TGs. Enable circuit 5
Is a circuit for selectively enabling or disabling an input to the TG. In the timing pulse generation circuit shown in FIG. 17, the reference signal generation section 3 outputs a change signal that is inverted every cycle of the processing cycle.

The change signal is directly supplied to the enable circuit 5 provided in the even-numbered TG among the first to (m + 1) -th TGs. On the other hand, among the first to (m + 1) th TGs, the enable circuit 5 included in the odd-numbered TG includes:
The change signal is supplied via an inverter circuit. According to the above structure, the even-numbered TG group and the odd-numbered TG group are alternately enabled every processing cycle of the semiconductor test apparatus.

In the first to (m + 1) th TGs, one interleave circuit 6 is provided for every two adjacent TGs. The interleave circuit 6 is a circuit that makes the output of one of the two TGs valid every cycle. According to the above-described structure, the timing pulse generated by the even-numbered TG and the timing pulse generated by the odd-numbered TG can be alternately output from the interleave circuit 6 for each processing cycle. .

That is, in the timing pulse generation circuit shown in FIG. 17, during the period in which the even-numbered TG generates the timing pulse, the odd-numbered T
G can terminate the process for generating the timing pulse. Similarly, during the period in which the odd-numbered TG generates the timing pulse, the process for generating the timing pulse in the next period can be completed by the even-numbered TG. Therefore, according to the timing pulse generation circuit shown in FIG. 17, the occurrence of a timing dead zone immediately after the start of each cycle can be reliably prevented.

[0018]

However, according to the configuration of the timing pulse generation circuit shown in FIG. 17, twice the TG is required for the maximum number of timing pulses that can be generated in one cycle. That is, according to the configuration shown in FIG. 15, the function of generating n timing pulses in one cycle can be realized by n TGs, whereas according to the configuration shown in FIG. , M + 1 TGs, only m + 1/2 timing pulses can be generated in one cycle. For this reason, the conventional timing pulse generation circuit shown in FIG. 17 is liable to cause inconveniences such as an increase in power consumption and an increase in substrate size, an increase in size of the apparatus, and an increase in cost due to an increase in mounted components. Was.

The present invention has been made in order to solve the above-mentioned problem, and has one waveform forming circuit and a plurality of TGs for each pin, and all TGs generate timing pulses within one cycle. It is a first object of the present invention to provide a timing pulse generation circuit that realizes both a state that can occur and a state that prevents the occurrence of a timing dead zone by interleaving some TGs with other TGs.

It is a second object of the present invention to provide a semiconductor test apparatus for testing a semiconductor device using the above-described timing pulse generating circuit.

[0021]

According to a first aspect of the present invention, there is provided a timing pulse generating circuit comprising: a plurality of timing generating means for generating a timing pulse at a time according to a setting of a user; A waveform forming means for changing a pin output every time a timing pulse is issued, an interleave-off state in which all timing generating means can generate a timing pulse in the same cycle, and a part of timing generating means in the same cycle. Interleave means for realizing an interleave-on state in which a timing pulse can be generated and the remaining timing generation means can generate a timing pulse in a cycle following the same cycle.

A timing pulse generating circuit according to a second aspect of the present invention is characterized in that the interleaving means generates a timing pulse while the interleaving on state is realized.
A state in which the remaining timing generating means generates a timing pulse is generated alternately for each cycle.

According to a third aspect of the present invention, there is provided the timing pulse generating circuit, wherein the timing generating means reads a set value of the user and generates a coarse pulse when the set value matches the count value. And a vernier for reading a set value of a user and generating an accurate timing pulse based on the coarse pulse.

According to a fourth aspect of the present invention, there is provided a timing pulse generating circuit, wherein the interleave means generates an interleave off signal and an interleave on signal, and the interleave signal is generated when the interleave off signal is generated. When all the timing generating means are in the active state and the interleave-on signal is issued, only a part of the timing generating means is provided under the condition that the change signal inverted every cycle is at the first level. And a logic circuit that activates only the remaining timing generating means when the change signal is at the second level.

According to a fifth aspect of the present invention, in the timing pulse generating circuit, when the interleave-off signal is issued, the logic circuit always activates the enable terminals of all the timing pulse generating means. When the interleave-on signal is issued, one of the change signal and its inverted signal is supplied to an enable terminal of the part of the timing pulse generating means, and the remaining timing pulse generating means is supplied. The other of the change signal and its inverted signal is supplied to an enable terminal.

In a timing pulse generating circuit according to a sixth aspect of the present invention, one of the counter and the vernier included in the partial timing generating means executes a process for alternately generating a timing pulse for each cycle. A first bank and a second bank, wherein the interleave means causes the some timing generation means to generate the timing pulse by a built-in counter and vernier while the interleave-on state is realized; The remaining timing generating means uses one of the first and second banks built in the partial timing generating means and one of a counter and a vernier built in the remaining timing generating means, It is characterized in that a pulse is generated.

According to a seventh aspect of the present invention, in the timing pulse generating circuit, the first bank and the second bank may include:
A first counter bank and a second counter bank for generating a coarse pulse for each cycle.

In the timing pulse generating circuit according to claim 8 of the present invention, the interleave means may include an interleave signal generation means for generating an interleave off signal and an interleave on signal, and Supplying the outputs of the first and second counter banks included in the partial timing generating means to the verniers included in the timing generating means, and outputting the outputs of the counters included in the remaining timing generating means to the timing generating means. Realizes an interleave off state to be supplied to the vernier provided by, furthermore, when the interleave on signal is issued,
An output of the first counter bank included in the partial timing generator is supplied to a vernier included in the timing generator, and an output of the second counter bank is
Selecting means for realizing an interleave-on state to be supplied to the vernier provided in the remaining timing generating means.

According to a ninth aspect of the present invention, there is provided a semiconductor test apparatus, comprising: a timing pulse generating circuit according to any one of the first to eighth aspects; and a test process for executing a process necessary for testing a plurality of types of semiconductor devices. Executing means.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. Elements common to the drawings are denoted by the same reference numerals, and redundant description will be omitted.

Embodiment 1 FIG. 1 is a circuit diagram of a timing pulse generation circuit according to the first embodiment of the present invention. The timing pulse generation circuit according to the present embodiment is a part of a semiconductor test apparatus that performs a predetermined test using an LSI such as a microcomputer, a synchronous or asynchronous memory as a device to be measured.

As shown in FIG. 1, the timing pulse generating circuit includes a reference signal generating section 3. The reference signal generator 3 outputs a reference signal that is inverted at a predetermined cycle, and a change signal that is inverted every period that is one cycle of a processing cycle in a test performed by the semiconductor test apparatus.

The reference signal generated by the reference signal generator 3 is supplied to first to n-th timing generation circuits, that is, first to n-th TGs (n is an even number). The first to n-th TGs are respectively the first to n-th
A counter 1 and first to n-th verniers 2 are provided. Further, an enable circuit 5 is provided for each of the first to n-th TGs. The enable circuit 5
An active state is realized by the “L” input, that is, a state in which an input signal to the TG is made valid, and “L”
This circuit realizes an inactive state by input, that is, a state in which an input signal to the TG is invalidated.

The first to n-th counters 1 operate when the corresponding enable circuit 5 realizes the active state.
While receiving the reference signal, the count value is incremented,
The count value is reset every cycle. Each of the first to n-th counters 1 reads the user's setting in each cycle of the process executed by the semiconductor test apparatus, and generates a timing pulse when the count value becomes a value corresponding to the setting. I do. According to the first to n-th counters 1, by executing the above processing, it is possible to generate a coarse timing pulse corresponding to the setting of the user.

Each of the first to n-th verniers 2 includes
Output pulses of the first to n-th counters 1 are supplied, and a reference signal, that is, a delay reference signal is supplied from the quasi-signal generator 3 via a delay circuit. The first to n-th verniers 2 perform OR logic of the output pulses of the first to n-th counters 1 and the delay reference signal, and generate a desired timing pulse based on a signal obtained as a result. First
The n-th vernier 2 reads the user's setting every period, and generates a timing pulse so that an edge that exactly matches the setting is obtained. According to the first to n-th verniers 2, by executing the above-described processing, it is possible to generate timing pulses that exactly correspond to user settings.

The timing pulse generating circuit of the present embodiment has a plurality of functional units 6. The functional unit 6 is provided for each of two adjacent TGs. The function unit 6 includes a two-input NOR circuit 604 connected to the enable circuit 5 corresponding to the even-numbered TG, and an odd-numbered T
Two-input NOR connected to enable circuit 5 corresponding to G
A circuit 605 is provided.

A change signal is supplied from the reference signal generator 3 to one input terminal of the NOR circuit 604. Further, a change signal is supplied from the reference signal generator 3 to one input terminal of the NOR circuit 605 via an inverter circuit 606. Further, the output signals of the D flip-flop 603 are supplied to the other input terminals of these two NOR circuits.

The D flip-flop 603 operates according to a bus signal supplied from the CPU of the semiconductor test apparatus, or
It is controlled by a high-speed signal supplied via a dedicated line.
Specifically, D flip-flop 603 generates an “H” output or an “L” output according to these bus signals or high-speed signals.

The function section 6 has a two-input AND circuit 601. The output signal of the vernier 2 included in the even-numbered TG is supplied to one input terminal of the AND circuit 601. The output signal of the two-input OR circuit 607 is supplied to the other input terminal of the AND circuit 601. OR circuit 6
The input terminal of 07 is supplied with the output signal of the vernier included in the odd-numbered TG and the output signal of the D flip-flop 603.

The function unit 6 further includes a two-input NAND circuit 602
It has. One input terminal of the NAND circuit 602 includes:
The output signal of the vernier 2 included in the odd-numbered TG is supplied via the inverter circuit 608. The other input terminal of the NAND circuit 602 has a D flip-flop 6
03 is supplied. The output signal of the AND circuit 601 and the output signal of the NAND circuit 602 are both supplied to the waveform forming circuit 4.

The waveform forming circuit 4 is provided corresponding to one output pin. The waveform forming circuit 4 includes an AND circuit 60
1 and a circuit that inverts the pin output each time a timing pulse is supplied from any of the NAND circuit 602.

The timing pulse output from the waveform forming circuit 4 is applied to one pin of the device under test or
It is supplied to a decision circuit built in the semiconductor test device. When the above timing pulse is supplied to one pin of the device under test, it is used, for example, as an address signal or a clock signal. On the other hand, when the timing pulse is supplied to the determination circuit, it is used as a signal for determining the timing for determining the output of the device under test.

Next, the operation of the timing pulse generation circuit according to the present embodiment will be described with reference to FIGS. FIG. 2 shows a state where the D flip-flop 603 generates an “H” output. D flip-flop 603
Generates an "H" output, the input of the enable circuit 5 is fixed at the "L" input. Therefore, in this case, the first to n-th TGs are always in the active state.

The D flip-flop 603 is set to "H".
When an output is generated, the input to one input terminal of the AND circuit 601 is fixed to the “H” input, and the NAND circuit 6
02 is fixed to an “L” input. In this case, the timing pulse generated from the odd-numbered TG is supplied to the waveform forming circuit 4 via the AND circuit 601, and the timing pulse generated from the even-numbered TG is supplied to the waveform forming circuit 4 via the NAND circuit 602. Supplied.

That is, the D flip-flop 603
When generating an “H” output, each of the first to n-th TGs generates a timing pulse toward the waveform forming circuit 4 at an appropriate time corresponding to the user's setting. In this case, the first to n-th TGs can supply a maximum of n timing pulses to the waveform forming circuit 4 within one cycle of the processing executed by the semiconductor test apparatus.

FIG. 3 shows an example of a timing chart realized under the above-mentioned situation, that is, under the situation where the D flip-flop 603 emits "H" output. Under the above situation, as shown in FIGS. 3C and 3D, the first and second TGs are always kept on, that is, in the active state.

FIGS. 3 (E) and 3 (F) show the set values of the first and second TGs, that is, the times when those TGs are set by the user as the timing when the timing pulse should be generated. When the first and second TGs are always in the active state, the timing pulses generated from those TGs are, as shown in FIGS. 3 (G) and (H), after a predetermined delay, the AND circuit 601 and the NAND circuit 602. Therefore, in this case, as shown in FIG.
It is possible to obtain a pin output that inverts the output each time each TG generates a timing pulse within the same cycle.

Next, the influence of the timing dead zone in the timing pulse generation circuit of this embodiment will be described with reference to FIG. FIG. 4 shows that the output signal of D flip-flop 603 is an “H” signal and that
FIG. 9 shows a timing chart realized in a situation where the first TG is set to generate a timing pulse immediately before its end in period 1 as shown in FIG.

As described above, the first TG reads the user's settings every period and generates a timing pulse at a time according to the settings. For this reason, after a timing pulse is generated, a new timing pulse cannot be generated during a predetermined period from completion of processing of timing data and the like. For the above reason, when the timing pulse generation timing of the first TG in the cycle 1 is set immediately before the end of the cycle 1 as shown in FIG. The period is a timing dead zone.

When the timing pulse generation circuit is required to generate a timing pulse at a high speed, the first TG is required to generate a timing pulse within a timing dead zone. Things can happen. In this case, if the output of the D flip-flop 603 is fixed to the “H” output, a desired timing pulse cannot be generated as shown in FIG.
As shown in FIG. 4I, a situation occurs in which the pin output cannot be inverted at a desired timing.

FIG. 5 shows a state in which the output of the D flip-flop 603 is fixed to the "L" output in the timing pulse generating circuit of the present embodiment. When the output of the D flip-flop 603 is an “L” output, the input of the enable circuit 5 depends on the change signal generated by the reference signal generator 3. Therefore, in this case, the odd-numbered T
The G group and the even-numbered TG group alternately become active every cycle.

When the output of the D flip-flop 603 is an “L” output, the AND circuit 601 supplies the output signal of the odd-numbered TG together with the output signal of the even-numbered TG via the OR circuit 607 in the preceding stage. An output signal is provided. Therefore,
In this case, the AND circuit 601 alternately supplies the output of the odd-numbered TG and the output of the even-numbered TG to the waveform forming circuit 4 in each cycle. On the other hand, the D flip-flop 603
Is fixed to the “L” output, the output of the NAND circuit 602 is fixed to the “H” output. Therefore, in this case, no timing pulse is supplied from the NAND circuit 602 to the waveform forming circuit 4.

FIG. 6 shows a timing chart realized under the above-mentioned situation, that is, under the situation where the output of the D flip-flop 603 is fixed to the "L" output. In the timing chart shown in FIG. 6, as shown in FIGS. 6 (E) and (F), the timing pulse generation timing of the first TG is set immediately before the end of period 1, and the second TG
Is realized when the timing pulse generation timing is set immediately before the end of period 2.

The output of the D flip-flop 603 is "L"
When the output is fixed, in the period 1, the timing pulse is emitted from the first TG, but the timing pulse is not emitted from the second TG. Therefore, the second T
G can properly generate a timing pulse immediately after the start of period 2 as shown in FIG. 6 (F).

When the output of the D flip-flop 603 is fixed to the “L” output, the timing pulse generated from the first TG and the timing pulse generated from the second TG are as shown in FIG. ), Both are output from the AND circuit 601. As a result, two timing pulses are generated with no timing dead zone. Therefore, in the above situation, FIG.
As shown in (I), a desired pin point waveform can be formed without being affected by the timing dead zone.

As described above, according to the timing pulse generation circuit of the present embodiment, when it is necessary to generate a timing pulse within one cycle using all of a plurality of TGs corresponding to the same pin, the interleave function is provided. By turning off, it is possible to realize a state in which all the TGs generate timing pulses at appropriately set individual times within the same cycle. Further, when there is a TG that does not need to be used among a plurality of TGs corresponding to the same pin, the interleave function can be turned on to enable timing setting without a timing dead zone.

When the device to be measured is, for example, a high-speed microcomputer or a high-speed synchronous memory,
In order to execute the test, one timing pulse
Only one may be set. On the other hand, when the device to be measured is, for example, an asynchronous memory, it is necessary to set a plurality of timing pulses in one cycle to execute a test.

According to the timing pulse generation circuit of the present embodiment, the number of timing pulses generated in one cycle can be changed, and when an unused TG occurs, the timing dead is generated by using the TG. Zone generation can be prevented. For this reason, according to the timing pulse generation circuit of the present embodiment, various situations required for testing various devices under test can be efficiently realized.

In the present embodiment, the timing pulse generating circuit is mounted on a semiconductor test apparatus having a function of executing a plurality of tests for various devices under test. More specifically, it is used by being mounted on a semiconductor test apparatus having a function of executing a plurality of tests for a high-speed microcomputer, a high-speed synchronous memory, an asynchronous memory, and the like. According to the semiconductor test apparatus of the present embodiment, in addition to the various LSIs described above, for example, various microcomputers with built-in memories,
Tests for LSI can be executed efficiently.

In the above embodiment, the first to n-th TGs correspond to the "timing generating means" of the first aspect, and the waveform forming circuit 4 corresponds to the "waveform forming means" of the first aspect. , The function unit 6 corresponds to the “interleave means” of the first aspect.

In the above embodiment, one of the odd-numbered TG and the even-numbered TG is provided in the "partial timing generating means" according to the second aspect, and the other is provided in the "remaining timing generating means" in the second aspect. Timing generating means ".

Further, in the above embodiment, the first to n-th counters correspond to the “counter” of the third aspect.
The first to n-th verniers correspond to the “vernier” in claim 3.

In the above embodiment, the D flip-flop 603 is used as the "interleave signal generating means" according to the fourth aspect, and the NOR circuits 604 and 605 and the inverter circuit 606 are used as the "interleave signal generating means" according to the fourth or fifth aspect. Logic circuit ".

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIGS. FIG.
FIG. 3 shows a circuit diagram of a timing pulse generation circuit according to a second embodiment of the present invention. The timing pulse generation circuit according to the present embodiment is, like the timing pulse generation circuit according to the first embodiment, a semiconductor test apparatus that executes a predetermined test using an LSI such as a microcomputer or a synchronous or asynchronous memory as a device to be measured. Part of. In FIG. 7,
Components that are the same as the components shown in FIG. 1 are given the same reference numerals, and descriptions thereof will be omitted.

As shown in FIG. 7, in the timing pulse generation circuit of the present embodiment, the first to n-th TGs respectively have first to n-th counters 7. In the present embodiment, the reference signal generator 3 generates a load signal together with the above-described reference signal and change signal. The load signal is a signal composed of a pulse signal at a predetermined interval repeatedly generated in each test cycle. These signals are supplied from the quasi-signal generator 3 to the first to n-th counters 7.

FIG. 8 is a circuit diagram of the first counter 7.
The first to n-th counters 7 have the same configuration. Therefore, here, the structure of the first counter 7 will be described as a representative example thereof. The first counter 7 includes a first counter bank 701 for odd-numbered test cycles and a second counter bank 702 for even-numbered test cycles. The load circuit LD of the first counter bank 701 has an OR circuit 7
Eleven output signals are provided. The OR circuit 711 includes:
A load signal and an inverted signal of a change signal are supplied.

On the other hand, the output signal of the OR circuit 712 is supplied to the load terminal LD of the second counter bank 702. The OR circuit 712 is supplied with a load signal and a change signal. According to the above structure, the load signal supplied to the first and second counter banks 701 and 702 is made invalid every cycle by the change signal. The first and second counter banks 701, 702 are:
The count value is incremented using the reference signal as an input signal,
This is a counter that clears the count value when a pulse signal (edge) is input to the LD terminal. Therefore, the first and second counter banks 701 and 702 respectively
The count value is incremented using the test cycle as one unit.

The first counter 7 has a memory 703. The memory 703 is a memory that stores user settings regarding test execution conditions. The memory 703 outputs the stored setting data D0 (15,0) every cycle. Data D0 (15,0) output from the memory 703 is supplied to latch circuits 704 and 705. Latch circuits 704, 7
05 receives the data D0 (15, 0) in response to the up edge of the output signal or the inverted output signal of the toggle circuit 708, respectively.

The toggle circuit 708 is a circuit for inverting the output using the load signal as a clock signal. According to the above structure, it is possible to cause the latch circuits 704 and 705 to alternately take in the data D0 (15, 0) every test cycle, and to hold the taken-in data in each circuit for two test cycles. it can.

Output data D0 of latch circuits 704 and 705
Are supplied to the comparison circuits 706 and 707, respectively.
The output signals of the first or second counter bank 701, 702 are supplied to the comparison circuits 706, 707, respectively. NAND circuits 713 and 714 are connected to the comparison circuits 706 and 707, respectively. The NAND circuits 713 and 714 are provided in the first or second counter bank 7.
When the count values of the counters 01 and 702 are different from the output data D0 of the latches 704 and 705, the output is maintained at “H”
When they match, an output pulse is generated.

Outputs of the NAND circuits 713 and 714 are supplied to D flip-flops 709 and 710. The D flip-flops 709 and 710 output the outputs of the NAND circuits 713 and 714 to the outside using the delay signal of the reference signal as a clock signal. Hereinafter, D flip-flops 709 and 71
0 outputs to the first bank output and the second bank output, respectively.
This is called bank output.

FIG. 9 is a timing chart for explaining the operation of the first counter 7. In the timing chart shown in FIG. 9, as shown in FIGS. 9J and 9K, in period 1, the latch circuit 704 latches the user's set value “1”, and in period 2, the latch circuit 705 7 is a timing chart realized when the set value “2” is latched and the latch circuit 704 latches the user set value “1” in period 3.

As shown in FIGS. 9 (O) and 9 (P), the first counter 7 alternates with the count value of the first or second counter bank alternately at each cycle. A first bank output and a second bank output are generated. In the present embodiment, the first to n-th counters 7 are characterized in that, as described above, the first to n-th counters 7 are provided with the lines that emit alternate output signals every period.

As shown in FIG. 7, the timing pulse generating circuit of the present embodiment has a plurality of functional units 8. The function unit 8 is provided one for each of two adjacent TGs. Each functional unit 8 includes an OR circuit 804 corresponding to each of the first to n-th counters 7. First and second bank outputs are supplied to the OR circuits 804 from the first to n-th counters 7.

The function unit 8 includes two selection circuits 80
5,806. The selection circuits 805 and 806
It has two input terminals (A terminal and B terminal), a select terminal SL and an output terminal Q. Selection circuit 805,
806 outputs a signal supplied to the A terminal when the “L” signal is supplied to the select terminal SL, and supplies a signal to the B terminal when the “H” signal is supplied to the select terminal SL. This is a circuit that outputs a signal that has been output.

An A terminal and a B terminal of one of the selection circuits 805 have counters 7 provided in odd-numbered TGs, respectively.
Of the first bank and its counter 7
The output of the OR circuit 804 is supplied. The output of the selection circuit 805 is supplied to the corresponding vernier 2.

An A terminal and a B terminal of the other selection circuit 806 respectively include a counter 7 provided in an odd-numbered TG.
And the output of the OR circuit 804 that receives the first and second bank outputs from the even-numbered counter 7. The output of the selection circuit 806 is supplied to the corresponding vernier 2.

The output signals of the D flip-flop 803 are supplied to select terminals SL of the selection circuits 805 and 806. The D flip-flop 803 is controlled by a bus signal supplied from the CPU of the semiconductor test apparatus or by a high-speed signal supplied via a dedicated line, similarly to the D flip-flop 603 in the first embodiment.

The function section 8 includes a two-input AND circuit 801, a two-input NAND circuit 802, an OR circuit 607, and inverter circuits 807 and 808. These are the AND circuit 601, the NAND circuit 602, and the OR circuit 6 in the first embodiment.
As in the case of the inverter circuit 07 and the inverter circuit 608, the output signals of the first to n-th vernier 2 are transmitted to the waveform forming circuit 4 as appropriate in accordance with the output signal of the D flip-flop 803.

Next, the operation of the timing pulse generation circuit of the present embodiment will be described. FIG. 10 shows a state in which the output of D flip-flop 803 is fixed at “H”. When the output of the D flip-flop 803 is fixed at “H”, an “H” output is supplied to the select terminal SL. In this case, the selection circuits 805 and 806
Selects the B input. As a result, the selection circuit 805
The output of the OR circuit 804 corresponding to the odd-numbered TG is supplied to the vernier 2. On the other hand, the selection circuit 806 supplies the output of the OR circuit 804 corresponding to the even-numbered TG to the vernier 2.

The D flip-flop 803 is set to "H".
When an output is generated, the input to one input terminal of the AND circuit 801 is fixed to the “H” input, and the NAND circuit 8
02 is fixed to an “L” input. In this case, the AND circuit 801 supplies the output signal of the vernier 2 included in the odd-numbered TG to the waveform forming circuit 4. Further, the NAND circuit 802 supplies the output signal of the vernier 2 included in the even-numbered TG to the waveform forming circuit 4.

Therefore, the D flip-flop 803 is
When an “H” output is generated, each of the first to n-th TGs can supply a timing pulse to the waveform forming circuit 4 at an appropriate time corresponding to the setting of the user in each test cycle. it can. In this case, the timing pulse generation circuit can generate a maximum of n timing pulses in one test cycle.

FIG. 11 shows an example of a timing chart realized under the above situation, that is, under the situation where the D flip-flop 803 outputs "H" output. Under the above situation, as shown in FIGS. 11 (I) and (J), the first and second verniers 2 each generate a timing pulse at an appropriate time according to the setting of the user in each cycle.

In the above situation, FIG.
As shown in (L), the timing pulses output from the first and second verniers 2 are respectively AND gates 801
And output from the NAND circuit 802. Therefore, in this case, as shown in FIG. 11 (M), a pin output that inverts the output every time each TG generates a timing pulse can be obtained within the same cycle.

Next, with reference to FIG. 12, the influence of the timing dead zone in the timing pulse generation circuit of the present embodiment will be described. FIG. 12 shows a case where the output signal of D flip-flop 803 is an “H” signal, and FIG.
As shown in FIG. 2 (K), in the first cycle,
4 shows a timing chart realized under a situation where a timing pulse is set to be generated just before the end.

The first TG reads the user's settings every period and generates a timing pulse at a time according to the settings. Therefore, after generating the timing pulse,
A new timing pulse cannot be generated during a predetermined period until the processing of the timing data is completed. For the above reason, when the timing pulse generation timing of the first TG in the cycle 1 is set immediately before the end of the cycle 1 as shown in FIG. The period is a timing dead zone.

When the timing pulse generating circuit is required to generate a timing pulse at a high speed, the first TG is required to generate a timing pulse within a timing dead zone. Things can happen. In this case, if the output of the D flip-flop 803 is fixed to the “H” output, a desired timing pulse cannot be generated as shown in FIG.
As shown in FIG. 12 (M), a situation occurs where the pin output cannot be inverted at a desired timing.

FIG. 13 shows a state where the output of the D flip-flop 803 is fixed to the "L" output in the timing pulse generating circuit of the present embodiment. When the output of the D flip-flop 803 is an “L” output, the selection circuit 80
5, 806 selects the A input. Therefore, in this case, the first bank output and the second bank output of the counter included in the odd-numbered TG are supplied to the odd-numbered vernier 2 and the even-numbered vernier 2, respectively.

When the output of the D flip-flop 803 is “L” output, the output signal of the odd-numbered TG and the output signal of the even-numbered TG are output to the AND circuit 801 via the OR circuit 807 in the preceding stage. A signal is provided. Therefore,
In this case, the AND circuit 801 alternately supplies the output of the odd-numbered TG and the output of the even-numbered TG to the waveform forming circuit 4 in each cycle. On the other hand, D flip-flop 803
Is fixed to the “L” output, the output of the NAND circuit 802 is fixed to the “H” output. Therefore, in this case, no timing pulse is supplied from the NAND circuit 902 to the waveform forming circuit 4.

FIG. 14 shows the situation under the above situation, ie, D
9 shows a timing chart realized under a situation where the output of the flip-flop 803 is fixed to the “L” output.
In the timing chart shown in FIG. 14, as shown in FIGS. 14 (I) and (J), the timing pulse generation timing of the first TG is set just before the end of period 1, and the second T
This is realized when the timing pulse generation timing of G is set immediately before the end of period 2.

The output of D flip-flop 803 is "L"
When the output is fixed, in period 1, the first bank output of the first counter is issued as a timing pulse from the first TG, while the timing pulse is emitted from the second vernier 2 (second TG). Absent. Therefore, the second
The vernier 2 can appropriately generate a timing pulse immediately after the start of the period 2 as shown in FIG.

When the output of the D flip-flop 803 is fixed to the “L” output, the timing pulse generated from the first TG and the timing pulse generated from the second TG are as shown in FIG. ),
Both are output from the AND circuit 801. As a result, two timing pulses are generated with no timing dead zone. Therefore, in the above situation, as shown in FIG. 14I, a desired pin point waveform can be formed without being affected by the timing dead zone.

As described above, according to the timing pulse generation circuit of the present embodiment, when it is necessary to generate a timing pulse within one cycle using all of the plurality of TGs corresponding to the same pin, the interleave function is provided. By turning off, it is possible to realize a state in which all the TGs generate timing pulses at appropriately set individual times within the same cycle. Further, when there is a TG that does not need to be used among a plurality of TGs corresponding to the same pin, the interleave function can be turned on to enable timing setting without a timing dead zone. For this reason, according to the timing pulse generation circuit of the present embodiment,
As in the case of the first embodiment, various situations required to test various devices under test can be efficiently realized.

In particular, the timing generation circuit of the present embodiment interleaves only vernier 2
The desired functions described above are realized. By interleaving only vernier 2, it is possible to reduce the memory capacity required for interleaving as compared to a case where both counter 1 and vernier 2 are interleaved. Therefore, according to the timing generation circuit of the present embodiment, it is possible to obtain an effect that a desired function can be realized with a smaller memory capacity than the circuit of the first embodiment.

Further, in the present embodiment, the above-described timing pulse generating circuit is used by being mounted on a semiconductor test apparatus having a function of executing a plurality of tests for various devices under test. More specifically, it is used by being mounted on a semiconductor test apparatus having a function of executing a plurality of tests for a high-speed microcomputer, a high-speed synchronous memory, an asynchronous memory, and the like. According to the semiconductor test apparatus of the present embodiment, in addition to the various LSIs described above,
For example, it is possible to efficiently execute tests on various LSIs such as a microcomputer with a built-in memory and an ASIC with a built-in memory.

In the above embodiment, the first counter bank 701 and the second counter bank 702 are
The functional unit 8 corresponds to the “first bank” and the “second bank”, respectively, and the functional unit 8 corresponds to the “interleave means”.

In the above embodiment, the D flip-flop 803 corresponds to the "interleave signal generating means" according to the eighth aspect, and the OR circuit 804 and the selection circuits 805 and 806 correspond to the "interleave signal generating means" according to the eighth aspect. Selection means "
, Respectively.

[0098]

Since the present invention is configured as described above, it has the following effects. Claim 1
According to the described invention, it is possible to realize a state where all the timing generating means can individually generate timing pulses and a state where the timing dead zone can be avoided by using the unused timing generating means. Therefore, according to the timing pulse generation circuit of the present invention, it is possible to execute tests on various semiconductor devices.

According to the second aspect of the present invention, since some of the timing generating means and the remaining timing generating means generate timing pulses alternately, the desired timing can be continuously obtained without being affected by the timing dead zone. Can be generated.

According to the third aspect of the present invention, a coarse pulse is generated by the counter and the accuracy of the coarse pulse is increased by the vernier, whereby a highly accurate timing pulse can be generated with a simple structure.

According to the fourth aspect of the invention, in the interleave-off state, all the timing generating means are set to the active state, thereby realizing a state in which all of them can individually generate timing. In the interleave-on state, a part of the timing generation means and the remaining timing generation means can be alternately activated in each cycle. In this case, since a request for generating a timing pulse is generated every other cycle for some of the timing generating means and the remaining timing generating means, generation of a timing dead zone can be prevented.

According to the invention described in claim 5, the function described in claim 4 can be realized with a simple structure.

According to the sixth aspect of the present invention, in the interleaved state, it is necessary to store the user setting in both the counter and the vernier for some of the timing generating means, but not for the remaining timing generating means. A desired function can be realized by storing the user's setting in only one of the counter and the vernier. Therefore, according to the present invention, a desired function can be realized with a small memory capacity.

According to the seventh and eighth aspects of the invention, the function of the sixth aspect can be realized with a simple structure.

According to the ninth aspect of the present invention, the timing generation circuit can be applied to various semiconductor devices, and the semiconductor device itself has a function of executing tests on various semiconductor devices. . Therefore, according to the semiconductor test apparatus of the present invention, it is possible to efficiently execute a test using various semiconductor devices as devices to be measured.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a timing pulse generation circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of the timing pulse generation circuit shown in FIG. 1 under an interleave-off state.

FIG. 3 is a timing chart for explaining an operation of the timing pulse generation circuit shown in FIG. 1 in an interleave-off state.

FIG. 4 is a timing chart for explaining the influence of a timing dead zone in the timing pulse generation circuit shown in FIG. 1;

FIG. 5 is a circuit diagram of the timing pulse generation circuit shown in FIG. 1 in an interleave-on state.

FIG. 6 is a timing chart for explaining an operation of the timing pulse generation circuit shown in FIG. 1 in an interleave-on state;

FIG. 7 is a circuit diagram of a timing pulse generation circuit according to a second embodiment of the present invention.

8 is a circuit diagram of a first counter included in the timing pulse generation circuit shown in FIG.

FIG. 9 is a timing chart for explaining the operation of the first counter shown in FIG.

10 is a timing chart for explaining the operation of the timing pulse generation circuit shown in FIG. 7 in an interleave-off state.

11 is a timing chart for explaining an operation of the timing pulse generation circuit shown in FIG. 7 under an interleave-off state.

FIG. 12 is a timing chart for explaining an influence of a timing dead zone in the timing pulse generation circuit shown in FIG. 7;

13 is a circuit diagram of the timing pulse generation circuit shown in FIG. 7 in an interleave-on state.

FIG. 14 is a timing chart for explaining an operation of the timing pulse generation circuit shown in FIG. 1 in an interleave-on state;

FIG. 15 is a circuit diagram of a conventional timing pulse generation circuit.

16 is a timing chart for explaining the influence of a timing dead zone in the timing pulse generation circuit shown in FIG.

FIG. 17 is a circuit diagram of a conventional timing pulse generation circuit having an interleave function.

[Explanation of symbols]

1: 7 first through n-th counters, 2 first through n-th counters
Vernier, 3 reference signal generator, 4 waveform forming circuit, 5 enable circuit, 6;
603; 803 D flip-flop, 805
806 Selection circuit, TG timing generator.

Claims (9)

[Claims] 1. A plurality of timing generating means for generating a timing pulse at a time according to a user setting, a waveform forming means for changing a pin output every time a timing pulse is issued from the plurality of timing generating means, The timing generating means can generate a timing pulse within the same cycle, and some of the timing generating means can generate a timing pulse within the same cycle, and the remaining timing generating means can generate the timing pulse within the same cycle. A timing pulse generating circuit comprising: an interleaving means for realizing an interleave-on state capable of generating a timing pulse in a subsequent cycle. 2. The interleave means includes: a state in which the timing generator generates a timing pulse; and a state in which the remaining timing generator generates a timing pulse while the interleave-on state is realized. 2. The timing pulse generating circuit according to claim 1, wherein the signals are alternately generated for each period. 3. The timing generating means reads a set value of a user, generates a coarse pulse when the set value matches a count value, and reads a set value of the user to read the coarse pulse. 3. The timing pulse generating circuit according to claim 2, further comprising: a vernier that generates an accurate timing pulse based on the timing. 4. The interleave means includes: an interleave signal generation means for generating an interleave off signal and an interleave on signal; and when the interleave off signal is issued, all the timing generation means are activated.
In addition, when the interleave-on signal is issued, only a part of the timing generation means is activated in a situation where the change signal inverted every cycle is at the first level, and the change signal is set to the second level. 4. The timing pulse generation circuit according to claim 1, further comprising: a logic circuit that activates only the remaining timing generation means in a level state. 5. The logic circuit, when the interleave-off signal is issued, always supplies an active signal to enable terminals of all timing pulse generating means, and the interleave-on signal is issued. In this case, one of the change signal and its inverted signal is supplied to an enable terminal of the timing pulse generator, and the enable signal of the change signal and its inverted signal are supplied to an enable terminal of the remaining timing pulse generator. 5. The timing pulse generating circuit according to claim 4, wherein the other is supplied. 6. One of the counter and the vernier included in the partial timing generating means executes a process for alternately generating a timing pulse for each cycle.
A bank and a second bank, wherein the interleave means causes the part of the timing generation means to generate the timing pulse by a built-in counter and vernier while the interleave-on state is realized. In the remaining timing generating means, one of the first and second banks built in the partial timing generating means and one of the counter and vernier built in the remaining timing generating means, and the timing pulse is generated. 4. The timing pulse generation circuit according to claim 3, wherein the timing pulse is generated. 7. The timing pulse generation circuit according to claim 6, wherein said first bank and said second bank are a first counter bank and a second counter bank which generate a coarse pulse every period. 8. An interleave means comprising: an interleave signal generation means for generating an interleave off signal and an interleave on signal; and a first timing generation means included in the part of the timing generation means when the interleave off signal is issued. And an output of the second counter bank is supplied to a vernier included in the timing generation means, and an output of a counter provided in the remaining timing generation means is supplied to a vernier included in the timing generation means to realize an interleave-off state. Further, when the interleave-on signal is issued, the output of the first counter bank included in the partial timing generator is supplied to the vernier included in the timing generator, and the second counter is provided. The output of the bank is Timing pulse generator according to claim 7, characterized by comprising selecting means for realizing interleaving ON state supplies the vernier provided is generating means. 9. A timing pulse generating circuit according to claim 1, further comprising: test processing executing means for executing processing necessary for testing a plurality of types of semiconductor devices. Semiconductor test equipment.