JPH11346320A - Video signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit whose quality is satisfactory by generating high pass frequency signal components corresponding to a picture element under consideration, and adding them to the picture element under consideration, and amplitude-limiting the signal level of the added output between an upper limit value and a lower limit value. SOLUTION: The output of a high pass filter HPF: 8 is inputted to a multiplier 9, and a signal B2 is outputted, and inputted to an adder 10. The adder 10 adds a signal B1 and the signal B2, and outputs a signal B5. The signal B5 is a signal obtained by adding high pass frequency signal components to the signal B1, and this signal B5 is inputted to a maximum value detecting circuit MAX: 11. The MAX: 11 selects the larger one among the signals 4 and 5, and outputs a signal B6. The undershoot part of the signal B5 is removed by the MAX: 11. The signal B6 is inputted to the minimum value detecting circuit MIN: 12. The MIN: 12 selects the smaller one among the signals B3 and B6, and outputs a signal B7. The overshoot part of the signal B6 is removed by the MIN: 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing device for processing a video signal displayed on an image display device such as a television receiver or a display device, and more particularly, to an interpolation circuit for increasing the number of pixels of a video signal. And a contour correction circuit for sharpening the contour of the video signal output from the interpolation circuit.

[0002]

2. Description of the Related Art Conventionally, an interpolation circuit for increasing the number of pixels of a video signal has been used for enlarging a video or converting interlaced scanning to progressive scanning. Here, the interpolation circuit will be described.

FIG. 15 is a waveform chart for explaining the operation of the interpolation circuit. In FIG. 15, (A) shows the original signal before interpolation, and (B) shows the signal after interpolation. The original signal shown in FIG. 15A is expressed by B1 = A1, B2 = 0.5 × A1 + 0.5 ×
A2, B3 = A2, B4 = 0.5 × A2 + 0.5 × A3
The signal shown in FIG. 15 (B) is obtained by linear interpolation as shown in FIG. This doubles the number of pixels.

[0004] This linear interpolation is an example of processing by an interpolation filter described below. FIG.
It is the same waveform as (A). When the number of pixels is doubled, as shown in FIG. 15C, the interpolation points indicated by ● are filled with zeros as shown. The signal shown in FIG. 15C in which the sampling rate has been doubled has a tap gain of (1/1).
Applying a 3-tap interpolation filter of (2, 1, 1/2)
The signal shown in FIG.

[0005] This processing will be described based on frequency characteristics. FIG.
The sampling rate of the signal shown in FIG.
FIG. 16A shows the frequency characteristics. FIG. 16 shows the frequency characteristics of a 3-tap interpolation filter with a sampling rate of 2 fs where the tap gain is (1/2, 1, 1/2).
(B). FIG. 1 interpolated by this interpolation filter
FIG. 16C shows the frequency characteristics of the signal of FIG.
As is clear from FIG. 16C, the high frequency components are reduced. This is because the low-pass characteristic of the interpolation filter attenuates gently.

FIG. 17 shows the above-described interpolation applied to two dimensions. FIG. 17B shows the original pixel of FIG. 17A interpolated twice horizontally and vertically. The coefficients for the interpolation are shown in the figure, and are shown in FIG.
An interpolation point having a tap gain of ４ て ４ て was filled in the original pixel of FIG. It will be.

In the case of two-dimensional interpolation shown in FIG.
As in the case of one-dimensional interpolation, the interpolated video signal becomes a blurred video signal with reduced high-frequency characteristics due to the gradual attenuation characteristics of the low-pass characteristics of the interpolation filter.

[0008]

As described above, in the interpolation circuit for increasing the number of pixels of the video signal, the high-pass characteristic of the low-pass characteristic of the interpolation filter is reduced.
The result is a blurred video signal. In order to reduce the deterioration of the high-frequency characteristic, an interpolation filter for higher-order taps is required. Particularly, two-dimensional hardware requires very large hardware. Further, there is a disadvantage that ringing occurs as the steepness between the pass band and the stop band of the low-pass characteristic occurs.

There is also a method of performing a so-called enhancement process in which a high-frequency component obtained by applying a high-pass filter to an interpolation signal is added to the interpolation signal. In this case, overshoots and undershoots occur at the edge of the signal, and the quality of image quality is impaired.

The present invention has been made in view of such a problem, and in a video signal processing circuit provided with an interpolation circuit for increasing the number of pixels of a video signal, the image quality is impaired without blurring the video signal. It is an object of the present invention to provide a video signal processing circuit capable of obtaining good image quality without adding such unnecessary shoot components.

[0011]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems of the prior art, the present invention provides an interpolation circuit for interpolating pixels of an input video signal, and a contour of a video signal output from the interpolation circuit. And a contour correction circuit that corrects a pixel having a level higher than a central level from a region of at least 5 pixels or more around the pixel of interest in the input video signal as the contour correction circuit. Upper limit detecting means for detecting as an upper limit value, lower limit detecting means for detecting, as a lower limit, a pixel having a level smaller than a central level from an area of at least five pixels or more around the target pixel, and a high frequency signal for the target pixel. A high-frequency signal component generating means for generating a component; an adding means for adding the high-frequency signal component to the pixel of interest; The signal level of the output means, between the lower limit and the upper limit is to provide a video signal processing apparatus characterized by being configured by providing an amplitude limiting means for amplitude limiting.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a contour correcting apparatus according to the present invention. FIG. 1 is a block diagram showing an overall configuration of a video signal processing apparatus according to the present invention, FIG. 2 is a block diagram showing a first embodiment of a contour correction circuit 2000 in FIG. 1, and FIGS. FIG. 5 is a waveform diagram for explaining the operation of the first embodiment, FIG. 5 is a block diagram showing a second embodiment of the contour correction circuit 2000 in FIG. 1, and FIG.
And FIG. 7 are waveform diagrams for explaining the operation of the second embodiment of the contour correction circuit 2000, and FIGS. 8 to 12 are block diagrams showing third to seventh embodiments of the contour correction circuit 2000 in FIG. 1, respectively. 13 and 14 are waveform diagrams for explaining the operation of the fourth and fifth embodiments of the contour correction circuit 2000 shown in FIGS.

In general, a baseband video signal is composed of three primary color signals of red (R), green (G) and blue (B), or a signal of three channels of a luminance signal and two color difference signals. In the following description, only one channel is shown for simplification. That is, the input digital signal is R,
One of the three primary color signals of G and B, or a luminance signal and a color difference signal.

In FIG. 1, a digital video signal is input to an interpolation circuit 1000, and the number of pixels is increased by interpolation of pixels. The interpolation by the interpolation circuit 1000 is based on the above-described conventional interpolation filter. Alternatively, the interpolation may be vertical double when interlaced scanning is converted to sequential scanning. In the case of a still image, interpolation by pixels of even and odd fields is used. In the case of a moving image, motion adaptive interpolation by interpolation in the same field is included. Further, any interpolation such as horizontal interpolation may be used.

The video signal interpolated by the interpolation circuit 1000 is input to a contour correction circuit 2000, where the contour of the video signal is corrected. Hereinafter, a specific configuration of the contour correction circuit 2000 will be described.

<First Embodiment> Referring to FIG.
The input digital signal is sequentially input to D flip-flops 2 to 5 which are one-clock delay elements, and is delayed by one clock. The digital signal input from the input terminal 1 is also input to a maximum value detection circuit 6, a minimum value detection circuit 7, and a high-pass filter (HPF) 8.

The outputs of the D flip-flops 2 to 5 are input to a maximum value detection circuit 6, a minimum value detection circuit 7, and an HPF 8, respectively. The signal B1 delayed by two clocks with respect to the input signal output from the D flip-flop 3 is shown in FIG.
The signal B1 is input to the adder 10. This signal B1 is set as a target pixel.

The maximum value detection circuit 6 detects a pixel of the maximum level from the five inputted pixels centering on the signal B1 as the target pixel, and outputs a signal B3 shown in FIG. That is, the maximum value detection circuit 6 is an upper limit detection unit that detects a maximum value as an upper limit value from the input five pixels. This signal B3 is input to the minimum value detection circuit 12. The minimum value detection circuit 7 detects a pixel of the minimum level from the five input pixels centering on the signal B1, and outputs a signal B4 shown in FIG. That is, the minimum value detection circuit 7 is a lower limit detection unit that detects the minimum value as the lower limit value from the input five pixels. This signal B4 is input to the maximum value detection circuit 11.

The HPF 8 has, as an example, a tap gain of (−1/4, −1, 5/2, −1, − ／).
It is a tap filter. The HPF 8 generates a high frequency signal component at an edge portion of the signal B1 from the input five pixels centered on the signal B1. Note that the high frequency signal component is a signal having no AC component but only an AC component.
The tap gain of the HPF 8 is not limited to this, and may be set appropriately.

The output of the HPF 8 is input to the multiplier 9 and multiplied by 2 assuming that the gain coefficient is 2, for example, and becomes a signal B2 shown in FIG. 3B. This signal B2 is input to the adder 10. The adder 10 receives the input signal B
1 and the signal B2 are added to output a signal B5 shown in FIG. This signal B5 is a signal obtained by adding a high frequency signal component to the signal B1. The signal B5 is input to the maximum value detection circuit 11.

The maximum value detection circuit 11 outputs the signal B4 and the signal B
5 is selected, and the larger one is selected, and the signal B shown in FIG.
6 is output. The undershoot portion of the signal B5 is removed by the maximum value detection circuit 11. The signal B6 is input to the minimum value detection circuit 12. The minimum value detection circuit 12 selects the smaller one of the signals B3 and B6 and outputs a signal B7 shown in FIG. With this minimum value detection circuit 12, an overshoot portion in the signal B6 is removed.

The maximum value detection circuit 11 and the minimum value detection circuit 12 output the signal B5 between the maximum value (upper limit value) of the maximum value detection circuit 6 and the minimum value (lower limit value) of the minimum value detection circuit 7. It can be seen that the device operates as amplitude limiting means for limiting the amplitude.

By the above operation, the signal B7 becomes the signal B1
The inclination near the center of the inclination is doubled as compared with, and the edge becomes steep, so that the contour is corrected without adding a shoot component. The signal B7 is output from the output terminal 13. Note that the slope of the signal B7 near the center of the slope can be freely set by the value of the gain coefficient of the multiplier 29.

As described above, in the present invention, since the maximum level pixel and the minimum level pixel are detected from the area of 5 pixels centering on the target pixel in the video signal, as shown in FIG. Perform the contour correction operation. In the present embodiment, the area is composed of 5 pixels. Of course, the maximum level pixel and the minimum level pixel may be detected from the area of 6 pixels or more, and it is sufficient if at least 5 pixels or more.

Here, consider a case where a signal containing noise is input to the contour correction circuit 2000 of the first embodiment shown in FIG. FIG. 4 shows an example of an operation signal waveform of each unit when a signal mixed with noise is input. In FIG. 4, (A) to (G) show the waveforms of the signals B1 to B7, respectively. In the signal B1 shown in FIG.
N1 and N2 are noises. When such a single noise is added, in the output signal B7, the noise is expanded over the area of three clocks as shown in FIG. 4 (G). That is, the contour correction circuit 2000 of the first embodiment shown in FIG. 2 has poor noise resistance.

<Second Embodiment> The second embodiment shown in FIG. 5 has improved noise resistance. In FIG. 5, digital signals input from an input terminal 21 are sequentially input to D flip-flops 22 to 25, which are one-clock delay elements, and are delayed by one clock. Input terminal 2
The digital signal input from 1 is transmitted to the upper limit detection circuit 26,
It is also input to a lower limit detection circuit 27 and a high pass filter (HPF).

Outputs of the D flip-flops 22 to 25 are respectively an upper limit detection circuit 26, a lower limit detection circuit 27, and an HPF.
28. The signal B1 delayed by two clocks with respect to the input signal output from the D flip-flop 23 is
The signal B1 is a signal shown in FIG.
Input to 0. This signal B1 is set as a target pixel.

The upper limit detection circuit 26 detects not the pixel of the maximum level but the pixel of the second largest level from the five input pixels centering on the signal B1 as the target pixel,
The signal B3 shown in FIG. 6C is output. Note that the upper limit detection circuit 26 detects a pixel having a level higher than the central level, excluding the pixel at the maximum level, from among the input pixels, and the configuration of FIG. Therefore, the pixel is necessarily the second largest pixel. This signal B3 is input to the minimum value detection circuit 32.

The lower limit detection circuit 27 is not a pixel having the lowest level than the input five pixels centered on the signal B1, and is
The pixel having the second lowest level is detected, and a signal B4 shown in FIG. 6D is output. This signal B4 is the maximum value detection circuit 3
1 is input. Note that the lower limit detection circuit 27 detects a pixel of a level lower than the central level, excluding the pixel of the minimum level, from among the input pixels, and in the configuration of FIG. Therefore, the pixel is inevitably the second smallest pixel.

The HPF 28 has a tap gain of (−1/4, −1, 5/2, −1, − ／) as an example.
It is a tap filter. The HPF 28 generates a high frequency signal component at the edge portion of the signal B1 from the input five pixels centered on the signal B1.

Then, assuming that the gain coefficient is 2, for example, the output of the HPF 28 is input to the multiplier 29 and doubled to obtain a signal B2 shown in FIG. 6B. This signal B2
Is input to the adder 30. The adder 30 adds the input signal B1 and the input signal B2, and outputs a signal B5 shown in FIG. This signal B5 is a signal obtained by adding a high frequency signal component to the signal B1. The signal B5 is input to the maximum value detection circuit 31.

The maximum value detection circuit 31 outputs the signal B4 and the signal B
5 and the larger one is selected, and the signal B shown in FIG.
6 is output. The undershoot portion in the signal B5 is removed by the maximum value detection circuit 31. The signal B6 is input to the minimum value detection circuit 32. The minimum value detection circuit 32 selects the smaller one of the signals B3 and B6 and outputs a signal B7 shown in FIG. The minimum value detection circuit 32 removes an overshoot portion in the signal B6.

The maximum value detecting circuit 31 and the minimum value detecting circuit 32 operate as amplitude limiting means for limiting the amplitude of the signal B5 between the upper limit value by the upper limit detecting circuit 26 and the lower limit value by the lower limit detecting circuit 27. You can see that it is.

By the above operation, the signal B7 becomes the signal B1
The inclination near the center of the inclination is doubled as compared with, and the edge becomes steep, so that the contour is corrected without adding a shoot component. The signal B7 is output from the output terminal 33. Note that the slope of the signal B7 near the center of the slope can be freely set by the value of the gain coefficient of the multiplier 29. The signal B7 shown in FIG.
As can be seen by comparing the signal B7 shown in (G), the signal B7 in the configuration of FIG. 5 and the signal B7 in the configuration of FIG.
7 has the same signal waveform.

Here, a case where the same noise as that described in FIG. 4 is mixed in the contour correction circuit 2000 of the second embodiment shown in FIG. 5 will be described with reference to FIG. In FIG. 7, (A) to (G) show the waveforms of the signals B1 to B7, respectively. In the signal B1 shown in FIG.
1 and N2 are noises.

As described above, in the configuration of the second embodiment, the upper limit detection circuit 26 determines the level of a pixel having a level higher than the center level (here, the second level) except for the maximum level pixel among the input pixels. Large level pixels)
The lower limit detection circuit 27 detects a pixel having a level lower than the central level (here, a pixel having the second lowest level) among the input pixels except for the pixel at the minimum level. Accordingly, in the output signal B7, noise is completely removed as shown in FIG. 7G, and the signal waveform becomes the same as that in FIG. 6G. Therefore, according to the second embodiment, it is possible to provide a contour correction device having excellent noise resistance.

As described above, in the configuration in which the upper limit value and the lower limit value are detected from the five input pixels centering on the signal B1 as the target pixel, if noise occurs one shot at a distance of 5 pixels or more, Even if the upper limit value is the maximum value or the second largest level, and the lower limit value is the minimum value or the second smallest level, the obtained waveform is the same. 2 and 5 when noise continues for two or more pixels.
In the above configuration, the obtained waveform will be different. It can be said that the configuration of FIG. 2 is desirable when the contour correction is regarded as important, and the configuration of FIG. 5 is desirable when the noise resistance is regarded as important.

<Third Embodiment> A third embodiment shown in FIG.
This is a two-dimensional extension of the contour correction circuit 2000 of the second embodiment. 8, the digital signal input from the input terminal 50 is sequentially input to the delay elements 51 to 54 for one horizontal period, and is delayed by one horizontal period. Input terminal 5
Digital signals input from 0 are sequentially input to D flip-flops 55 to 58, which are one-clock delay elements, and are delayed by one clock. Delay elements 51-54
The output digital signals are D flip-flops 59 to 62, which are also one-clock delay elements, respectively.
63 to 66, 67 to 70, 71 to 74
Delayed by one clock.

The digital signal input from the input terminal 50 is also input to an upper limit detection circuit 75, a lower limit detection circuit 76, and a two-dimensional high-pass filter (two-dimensional HPF) 77. D
Outputs of the flip-flops 55 to 74 are input to an upper limit detection circuit 75, a lower limit detection circuit 76, and a two-dimensional HPF 77, respectively. As described above, the upper limit detection circuit 75, the lower limit detection circuit 76, and the two-dimensional HPF 77 have the D flip-flop 6
A signal of 25 pixels in total, consisting of 5 pixels in the horizontal direction and 5 pixels in the vertical direction, with the signal B1 output from 4 as the center, is input. The signal B1 is input to the adder 79.

The upper limit detection circuit 75 ranks the input 25 pixels centered on the signal B1 as the target pixel from 1 to 25 in ascending order of the level (or in descending order of level). For example, a pixel at the fourth largest level from the maximum level is detected instead of the pixel at the level, and the signal B3 is output. This signal B3 is output from the minimum value detection circuit 32.
Is input to

The upper limit detection circuit 75 detects a pixel having a level higher than the central level among the input pixels except for the pixel at the maximum level. More preferably, the upper limit detection circuit 75 divides the input pixel from the minimum level to the maximum level into three parts, a small level part, an intermediate level part, and a large level part. Pixels at levels excluding are detected. Therefore, in the configuration of FIG.
The pixel at the fifth highest level or the pixel at the fifth highest level may be used. What level of the pixel is detected by the upper limit detection circuit 75 may be selected in accordance with the relationship between the noise removal effect and the contour correction effect.

The lower limit detection circuit 76 ranks the input 25 pixels centered on the signal B1 from 1 to 25 in ascending (or descending) order of the level. Instead, a pixel at the fourth lowest level from the minimum level is detected and a signal B4 is output.
This signal B4 is input to the maximum value detection circuit 80.

The lower limit detection circuit 76 detects a pixel having a level lower than the central level among the input pixels except for the pixel at the minimum level. More preferably, the lower limit detection circuit 76 divides the input pixel from the minimum level to the maximum level into three parts, a small level part, an intermediate level part, and a large level part. Pixels at levels excluding are detected. Therefore, in the configuration of FIG.
It may be the pixel of the fifth lowest level or the pixel of the fifth lowest level. What level of pixels is detected by the lower limit detection circuit 76 may be selected in accordance with the relationship between the noise removal effect and the contour correction effect.

The two-dimensional HPF 77 sets the tap gain as follows, for example. -1/256 -4/256 -6/256 -4/256 -1/256 -4/256 -16/256 -24/256 -16/256 -4/256 -6/256 -24/256 220 / 256 -24/256 -6/256 -4/256 -16/256 -24/256 -16/256 -4/256 -1/256 -4/25 6 -6/256 -4/256 -1/256 Here, the filter is a 25-tap filter, and the tap gain is symmetric with respect to the center.

The two-dimensional HPF 77 generates a high frequency signal component at the edge of the signal B1 from the input 25 pixels centered on the signal B1. And two-dimensional HPF7
Assuming that the gain coefficient is 2, for example, the output of the multiplier 7 is
8 and doubled to obtain a signal B2. This signal B2 is input to the adder 79.

The adder 79 adds the input signals B1 and B2 and outputs a signal B5. This signal B5
Is a signal obtained by adding a high frequency signal component to the signal B1. The signal B5 is input to the maximum value detection circuit 80.

The maximum value detection circuit 80 outputs the signal B4 and the signal B
5, the larger one is selected, and a signal B6 is output. The undershoot portion in the signal B5 is removed by the maximum value detection circuit 80. The signal B6 is input to the minimum value detection circuit 81. The minimum value detection circuit 81 outputs the signal B
3 and the signal B6, the smaller one is selected, and the signal B7 is output. The minimum value detection circuit 81 removes an overshoot portion in the signal B6. Note that the maximum value detection circuit 80 and the minimum value detection circuit 81 output the signal B5
Is determined by an upper limit value detection circuit 75 and a lower limit detection circuit 76.
It can be seen that the apparatus operates as amplitude limiting means for limiting the amplitude between the lower limit value and the lower limit value.

By the above operation, the signal B7 becomes the signal B1
The inclination near the center of the inclination becomes steeper than that of the above, and the contour is corrected without adding a shoot component. The signal B7 is output from the output terminal 82. The slope near the center of the slope of the signal B7 can be freely set by the value of the gain coefficient of the multiplier 78.

In the third embodiment shown in FIG. 8 as well, the upper limit detection circuit 75 detects a pixel having a level higher than the center level among the input pixels except for the pixel at the maximum level. Among the input pixels, pixels having a level lower than the center level are detected except for the pixels at the minimum level, so that even if noise is mixed in the input signal, the noise is completely removed. Therefore, according to the third embodiment, it is possible to provide a contour correction device having excellent noise resistance.

In the third embodiment described above, the area of the two-dimensional HPF 77 for generating the high frequency signal is 25 taps in the horizontal direction 5 and the vertical direction 5, and the area by the upper limit detection circuit 75 and the lower limit detection circuit 76 is also Although the two regions are set to be the same as 25 pixels in the horizontal direction 5 and the vertical direction 5, it is not always necessary to make them the same. For example, two-dimensional H
Good contour correction can be achieved even if the PF 77 has 25 taps in the horizontal direction 5 and the vertical direction 5 and the upper limit detection circuit 75 and the lower limit detection circuit 76 have 15 pixels in the horizontal direction 5 and the vertical direction 3.

The third embodiment shown in FIG. 8 is a two-dimensional extension of the configuration of the second embodiment shown in FIG. 5 in consideration of the noise resistance, but the input digital signal contains noise. In such a case, the configuration of the first embodiment shown in FIG. 2 may be extended two-dimensionally. In this case, a maximum value detection circuit may be used instead of the upper limit detection circuit 75 and a minimum value detection circuit may be used instead of the lower limit detection circuit 76 in FIG.

The contour correction circuit 2000 according to the first to third embodiments described above can correct a contour without adding a shoot component. By the way, when a display device of a video signal enlarges an image by an optical system and projects the image on a screen like a projection television, a high-frequency signal component of the displayed image is reduced.

As described above, in the case of a display device in which the spatial high frequency characteristics are deteriorated, a blurred image will be displayed even if the contour of the video signal is corrected. Therefore, this problem can be solved by newly generating a high frequency signal component and adding it to the contour-corrected signal in order to correct the spatial frequency characteristics of the display device.

In view of such a point, the fourth to seventh embodiments shown in FIGS. 9 to 12 are designed to intentionally add a shoot component to correct the spatial frequency characteristics. Of course, in this case, since the shoot component acts to correct the spatial frequency characteristics, the visual quality is improved without deteriorating the image quality. 9 to 12, the same portions as those in FIG. 8 are denoted by the same reference numerals, and the description of the same portions will be appropriately omitted.

<Fourth Embodiment> In FIG. 9, the outputs of D flip-flops 55 to 74 are input to a two-dimensional high-pass filter (two-dimensional HPF) 101. 2D HPF
Reference numeral 101, like the two-dimensional HPF 77, generates a high-frequency signal component at the edge of the signal B1 from the input 25 pixels centered on the signal B1. In addition, two-dimensional HPF1
The tap gain of 01 may be the same as the tap gain of the two-dimensional HPF 77, but it is desirable that the two are different from each other in order to make the tap gain of the two-dimensional HPF 101 optimal according to the spatial high frequency characteristics of the display device. .

The output of the two-dimensional HPF 101 is
Is input to The multiplier 102 is provided with a gain coefficient, and the high-frequency signal component output from the two-dimensional HPF 101 is gain-adjusted. The output of the multiplier 102 is the adder 1
03 and added to the contour-corrected signal B7 output from the minimum value detection circuit 81. And the adder 10
3 is output from the output terminal 104. In this manner, in the fourth embodiment shown in FIG. 9, by adding the high frequency signal component, it is possible to intentionally perform contour correction in which a shoot component is additionally generated.

<Fifth Embodiment> A fifth embodiment shown in FIG. 10 corresponds to the two-dimensional HPF 77 and the two-dimensional HPF 10 shown in FIG.
1 and 1 for simplicity. That is, the output of the two-dimensional HPF 77 is input to both the multiplier 78 and the multiplier 102.

The operation of the fourth and fifth embodiments shown in FIGS. 9 and 10 will be described with reference to the waveform chart shown in FIG. FIG. 13 shows a one-dimensional signal waveform for simplification. FIG. 13A shows a signal B7 output from the minimum value detection circuit 81 which has been contour-corrected without adding a shoot component. FIG. 13B shows the state of the multiplier 102.
This is a high-frequency signal component output from the control circuit. FIG.
(C) is a signal obtained by adding the signal B7 shown in FIG. 13A and the high frequency signal component shown in FIG. 13B by the adder 103. The signal shown in FIG. 13 (C) has a waveform close to a signal obtained by slightly adding a shoot component to the signal B7.

As can be seen from the above description, FIGS.
At 0, the multiplier 102 and the adder 103 add a high-frequency signal component to the signal whose amplitude has been limited by the maximum value detection circuit 80 and the minimum value detection circuit 81 constituting the amplitude limiting means, thereby forming a shoot component. It operates as a shoot component generating means for additionally generating.

<Sixth Embodiment> A sixth embodiment shown in FIG. 11 is configured to add a shoot component by another configuration. 11, a signal B3 output from the upper limit detection circuit 75 and a signal B4 output from the lower limit detection circuit 76 are input to the subtractor 110. Subtractor 110
Subtracts signal B4 from signal B3, and outputs signal B3 and signal B
The difference value with the value of 4 is input to the multiplier 111. Multiplier 111
Is given a constant gain coefficient, and the output of the subtracter 110 is multiplied by the gain coefficient. If the gain coefficient is, for example, 0.1, the output of the multiplier 111 is
0.1 × (upper limit value−lower limit value).

The output of the multiplier 111 is input to the adder 112 and the subtractor 113. The subtractor 113 subtracts the output of the multiplier 111 from the signal B4, which is the lower limit, to reduce the undershoot clip level to a level lower than the lower limit, and inputs the same to the maximum value detection circuit 80. The adder 112 adds the signal B3, which is the upper limit, to the output of the multiplier 111 to set the clip level of overshoot to a level higher than the upper limit, and inputs the clip level to the minimum value detection circuit 81.

As a result, finally, the minimum value detection circuit 8
An overshoot and an undershoot are added to the signal B7 output from 1. The amount of the shoot component is determined by the gain coefficient multiplied by the multiplier 111. Therefore, a shoot component can be arbitrarily added as needed. Also in this case, the signal B7 is
The signal is as shown in FIG.

<Seventh Embodiment> A seventh embodiment shown in FIG. 12 is obtained by slightly changing the structure of FIG. That is, in FIG. 11, the difference value between the signal B3 and the signal B4 output from the subtracter 110 is input to the multiplier 111, and the output of the multiplier 111 is input to the adder 112 and the subtractor 113. 12, the difference value between the signal B3 and the signal B4 output from the subtractor 110 is input to the multipliers 111 and 114, and the output of the multiplier 111 is output to the subtractor 113.
, And the output of the multiplier 114 is input to the adder 112.

The multipliers 111 and 114 are given a constant gain coefficient, and multiply the output of the subtracter 110 by the gain coefficient and output the result. If the gain coefficient is, for example, 0.1, the outputs of the multipliers 111 and 114 have a value of 0.1 × (upper limit value−lower limit value).

The subtracter 113 subtracts the output of the multiplier 111 from the signal B4, which is the lower limit, to set the undershoot clip level to a level lower than the lower limit, and inputs the same to the maximum value detection circuit 80. The adder 112
By adding the signal B3, which is the upper limit, to the output of the multiplier 114, the overshoot clip level is set to a level higher than the upper limit, and is input to the minimum value detection circuit 81.

As a result, finally, the minimum value detection circuit 8
An overshoot and an undershoot are added to the signal B7 output from 1. The amount of the shoot component is determined by the gain coefficient multiplied by the multipliers 111 and 114. Therefore, a shoot component can be arbitrarily added as needed. Also in this case, the signal B7 is
The signal is as shown in FIG.

As can be understood from the above description, the multiplier 111, the adder 112, and the subtractor 113 in FIG. 11 and the multipliers 111 and 114, the adder 112,
The subtractor 113 increases the upper limit value by the upper limit detection circuit 75 and decreases the lower limit value by the lower limit detection circuit 76, thereby limiting the amplitude by the maximum value detection circuit 80 and the minimum value detection circuit 81 constituting the amplitude limiting means. The signal operates as a shoot component generating means for additionally generating a shoot component as a result.

In general, a video signal display device has a so-called gamma characteristic in which the relationship between an input signal and an output signal is non-linear. For example, a cathode ray tube (CR
In the case of T), when the signal level is normalized from 0 to 1, it is said that the signal level has characteristics close to the 2.2th power of the signal level. For this reason, comparing the case where the high-frequency small-amplitude signal is superimposed on a dark video signal and the case where it is superimposed on a bright video signal, the latter has a larger amplitude.

Therefore, when a shoot component is added to correct the spatial frequency characteristic, it is desirable to use a shoot component corresponding to the gamma characteristic. For example, in order to cope with the gamma characteristic of the CRT, the amplitude of the negative polarity portion of the high frequency signal component (shoot component) may be made larger than the amplitude of the positive polarity portion. Which of the positive portion and the negative portion of the shoot component is increased depends on the nonlinear characteristics of the display device. If there is a display device having characteristics opposite to the gamma characteristic of the CRT, the amplitude of the positive polarity portion may be made larger than the amplitude of the negative polarity portion.

Of the fourth to seventh embodiments shown in FIGS. 9 to 12, in the fourth, fifth and seventh embodiments, the positive and negative portions of the shoot component can be asymmetric. It is.
It is a more preferable embodiment to make the size of the positive portion and the negative portion of the chute component different from each other in accordance with the non-linear characteristics of the display device so as to be asymmetric.

First, in FIG. 9 and FIG. 10, the magnitudes of the positive polarity part and the negative polarity part of the high frequency signal component input to the adder 103 are made different. That is, the multiplier 10
When multiplying the high frequency signal component output from the two-dimensional HPF 101 by the gain coefficient by 2, the coefficient in the positive polarity part and the coefficient in the negative polarity part may be different. As an example of the specific configuration, the two-dimensional HPF 10
A discriminator for discriminating the polarity of the output of No. 1 is provided, and a gain coefficient in a positive polarity portion and a gain coefficient in a negative polarity portion are switched by a switch according to the output of the discriminator.

As another configuration example, a non-linear processing circuit is provided between the multiplier 102 and the adder 103 to make the magnitudes of the positive and negative parts of the high frequency signal component asymmetric. As described above, various configurations are conceivable in which the positive portion and the negative portion of the high frequency signal component are asymmetric, and as a result, the positive portion and the negative portion of the shoot component are asymmetric.

On the other hand, in FIG.
By making the gain coefficient given to 114 different, the positive and negative portions of the shoot component can be made asymmetric. The multiplier 111 determines the level at which the undershoot clip level decreases from the lower limit, and the multiplier 114 determines the level at which the overshoot clip level increases from the upper limit. Therefore, when the gain coefficient of the multiplier 111 is set to be larger than the gain coefficient of the multiplier 114, the amplitude of the negative portion of the shoot component may be made larger than that of the positive portion so as to correspond to the gamma characteristic of the CRT. it can.

FIG. 14 shows waveforms when the positive and negative portions of the shoot component in FIGS. 9 and 10 are asymmetric. FIG. 14 also shows a one-dimensional signal waveform for simplification. FIG.
(A) is a signal B7 output from the minimum value detection circuit 81 that has been contour-corrected without adding a shoot component.
FIG. 14B shows a high-frequency signal component output from the multiplier 102 in which the positive and negative portions are asymmetric. FIG. 14C shows the result of FIG.
This is a signal obtained by adding the signal B7 shown in (A) and the high frequency signal component shown in FIG. 14 (B).

In FIG. 12, the signal B7 output from the minimum value detection circuit 81 has the same waveform as that of FIG.

9 to 12, if the noise resistance is not regarded as important, a maximum value detection circuit may be used instead of the upper limit detection circuit 75, and a minimum value detection circuit may be used instead of the lower limit detection circuit 76.

In the first and second embodiments described above, the upper and lower limits are detected from five pixels in the horizontal direction. In the third to seventh embodiments, the upper and lower limits are detected from 25 pixels in the horizontal and vertical directions. And the lower limit are detected. It is also possible to configure to detect the upper limit value and the lower limit value from five pixels in the vertical direction.
In this case, an effect is exerted on noise in the vertical direction. The upper limit value and the lower limit value may be detected from an area of at least 5 pixels in the horizontal or vertical direction with the target pixel as the center.

[0078]

As described above in detail, the video signal processing apparatus of the present invention interpolates the pixels of the input video signal and corrects the contour of the video signal output from the interpolation circuit. In the video signal processing apparatus provided with the contour correction circuit, as the contour correction circuit, a pixel having a level higher than the central level from an area of at least five pixels or more around the target pixel in the input video signal is detected as an upper limit value. Upper limit detecting means, a lower limit detecting means for detecting, as a lower limit, a pixel having a level smaller than the central level from an area of at least five pixels or more around the target pixel, and a high range for generating a high frequency signal component for the target pixel. Frequency signal component generating means, adding means for adding a high frequency signal component to the pixel of interest, and a signal level of the output of the adding means, Since the configuration is provided with the amplitude limiting means for limiting the amplitude between the lower limit and the lower limit, it is possible to obtain good image quality without blurring the image and without adding unnecessary shoot components that impair the image quality. Can be.

By setting the upper limit value to pixels excluding the pixels at the maximum level and setting the lower limit value to pixels excluding the pixels at the minimum level, noise can be removed even if noise is mixed in the input video signal. This makes it possible to provide a video signal processing device having excellent noise resistance. Therefore, this case is extremely effective when displaying an image on a large screen display.

Further, if a shoot component generating means for additionally generating a shoot component is provided, the shoot component can be arbitrarily added as needed.
The spatial frequency characteristics of the display device can be corrected, and the contour can be corrected more favorably. At this time, if means for making the amplitude of the positive and negative portions of the chute component asymmetric is included, the contour can be corrected even better in response to the non-linear characteristics (gamma characteristics) of the display device. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the contour correction circuit 2000 in FIG.

FIG. 3 is a waveform chart for explaining the operation of the first embodiment of the contour correction circuit 2000;

FIG. 4 is a waveform chart for explaining the operation of the first embodiment of the contour correction circuit 2000;

FIG. 5 is a block diagram showing a second embodiment of the contour correction circuit 2000 in FIG. 1;

FIG. 6 is a waveform diagram for explaining an operation of the second embodiment of the contour correction circuit 2000;

FIG. 7 is a waveform chart for explaining an operation of the second embodiment of the contour correction circuit 2000;

FIG. 8 is a block diagram showing a third embodiment of the contour correction circuit 2000 in FIG.

FIG. 9 is a block diagram showing a fourth embodiment of the contour correction circuit 2000 in FIG.

FIG. 10 is a block diagram showing a fifth embodiment of the contour correction circuit 2000 in FIG.

FIG. 11 is a block diagram showing a sixth embodiment of the contour correction circuit 2000 in FIG.

FIG. 12 is a block diagram showing a seventh embodiment of the contour correction circuit 2000 in FIG. 1;

FIG. 13 is a waveform chart for explaining the operation of the contour correction circuit 2000 in the fourth and fifth embodiments.

FIG. 14 is a waveform chart for explaining the operation of the contour correction circuit 2000 in the fourth and fifth embodiments.

FIG. 15 is a waveform chart for explaining the operation of the interpolation circuit.

FIG. 16 is a diagram showing frequency characteristics for explaining the operation of the interpolation circuit.

FIG. 17 is a diagram for explaining the operation of the two-dimensional interpolation circuit.

[Explanation of symbols]

2-5, 22-25, 55-74 D flip-flop 6 Maximum value detection circuit (upper limit detection means) 7 Minimum value detection circuit (lower limit detection means) 8, 28 High pass filter (high frequency signal component generation means) 9, 29, 78, 102, 111, 114 Multiplier 10, 30, 79 Adder (addition means) 11, 31, 80 Maximum value detection circuit (amplitude restriction means) 12, 32, 81 Minimum value detection circuit (amplitude restriction means) 26, 75 Upper limit detection circuit (upper limit detection means) 27, 76 Lower limit detection circuit (lower limit detection means) 77, 101 Two-dimensional high-pass filter (high frequency signal component generation means) 103, 112 Adders 110, 113 Subtractors 1000 Interpolation Circuit 2000 Contour correction circuit

Claims (6)

[Claims] 1. A video signal processing device comprising: an interpolation circuit for interpolating pixels of an input video signal; and a contour correction circuit for correcting a contour of a video signal output from the interpolation circuit. Upper limit detecting means for detecting, as an upper limit, a pixel having a level higher than a central level from an area of at least 5 pixels or more around the target pixel in the input video signal; and at least 5 pixels or more around the target pixel. A lower limit detecting unit that detects a pixel having a level smaller than a central level as a lower limit value from the region, a high frequency signal component generating unit that generates a high frequency signal component for the pixel of interest, and An adding unit for adding a frequency signal component, and a signal level of an output of the adding unit, the amplitude of which is between the upper limit and the lower limit. A video signal processing apparatus characterized by being configured by providing an amplitude limiting means for limited. 2. The video signal processing device according to claim 1, wherein said upper limit value is a pixel of a maximum level, and said lower limit value is a pixel of a minimum level. 3. The video signal processing apparatus according to claim 1, wherein the upper limit value is a pixel excluding a pixel of a maximum level, and the lower limit value is a pixel excluding a pixel of a minimum level. apparatus. 4. The video signal processing apparatus according to claim 1, wherein a shot component is additionally generated by adding a high-frequency signal component to the signal whose amplitude has been limited by said amplitude limiting means. A video signal processing device characterized by comprising a shoot component generating means for causing the video signal to be generated. 5. The video signal processing device according to claim 1, wherein the upper limit value is increased and the lower limit value is reduced, so that a shoot component is added to an output of the amplitude limiting means. A video signal processing apparatus characterized by comprising a shoot component generating means for generating a video signal. 6. The video signal processing apparatus according to claim 4, wherein said shoot component generating means includes means for making the amplitude of a positive part and a negative part of the shoot component asymmetric. A video signal processing device.