JPH11345973A - Thin film transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor wherein degradation of crystallinity, disconnection, etc., which are to be caused by irregularities of a substrate of a semiconductor layer constituting a channel region and a source-drain region, may not occurs, and a manufacturing method of the thin film transistor. SOLUTION: A gate electrode material layer is formed on a light transmission substrate 11, and a resist pattern 13 is formed so as to cover a gate electrode region. Anodic oxidation is performed by using the resist pattern 13 as a mask, and a planarization insulating film 14 is formed on the side part of a gate electrode 15. A gate insulating layer 16 and a polysilicon layer 17 are formed in order on the surface flattened by the film 14, and a thin film transistor is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an active matrix type liquid crystal display (LCD) and a thin film transistor (Thin Film Transistor) used for a memory integrated circuit.
or: hereinafter abbreviated as TFT) and a method for manufacturing the same.

[0002]

2. Description of the Related Art A TFT using amorphous silicon (a-Si) and a polycrystalline silicon (p-S) are used for a TFT used for driving an image display of a liquid crystal TV or a personal computer.
Some use i). p-Si TFT is a-Si TFT
It is expected that a higher definition can be achieved in terms of characteristics than a TFT, and a driver circuit can be formed on a substrate, so that a reduction in cost can be realized. The p-Si TFT includes a high-temperature type and a low-temperature type depending on the temperature when polycrystallizing Si.
Since a glass substrate can be used for the low-temperature type,
Large area is possible. In order to realize the large area, a low-resistance wiring material is required, and Al, Cu, and the like correspond thereto.

Therefore, a conventional method for manufacturing a TFT array using Al as a wiring material will be described below with reference to a manufacturing process sectional view shown in FIG.

[0004] SiO _{2 is formed} on a transparent substrate 21 such as glass.
After forming a base insulating film 22 made of Al, a conductive film made of Al is formed thereon and etched into a predetermined shape using a resist pattern 23 to form a gate electrode 24 (FIG. 2A). . Next, a gate insulating layer 25 made of SiO ₂ is formed thereon (FIG. 2B). Then, a-
A film of Si is formed, etched and patterned into a predetermined shape, and a-Si is crystallized using an excimer laser to form a polysilicon layer 26 serving as a semiconductor layer (FIG. 2C).

Next, a source region 26b and a drain region 26c are formed in the polysilicon layer 26 by ion-implanting an impurity through the resist pattern 27 through the resist pattern 27 with the channel region 26a interposed therebetween. (FIG. 2D). After removing the resist pattern 27, an interlayer insulating film 28 made of SiO _{2 is} formed on the polysilicon layer 26 by a normal pressure CVD method (FIG. 2).
(E)). Next, a contact hole 29 is opened, and finally, a source / drain electrode 210 is formed to complete a thin film transistor (FIG. 2F).

[0006]

However, the above-mentioned conventional thin film transistor has the following problems.

In the process of FIG. 2A, when the gate electrode is formed by dry etching or wet etching using a resist pattern, the cross-sectional shape of the gate electrode becomes almost rectangular by dry etching, and becomes substantially rectangular by wet etching. Also has a shape with a steep taper of about 50 degrees. Therefore, when an inverted staggered TFT array in which the gate electrode is located under the semiconductor layer as shown in FIG. 2 is to be formed, the semiconductor layer (FIG. Is formed on a substrate having a step having a convex region called a gate electrode.

As a result, there arises a problem that the crystallinity of the semiconductor layer becomes non-uniform due to the influence of the unevenness of the base. Note that the gate electrode has a thickness of 100 nm or more, whereas the semiconductor layer has a thickness of about several tens of nanometers. In the worst case, disconnection occurs at a pattern step portion of the gate electrode, At the cross portion of the source electrode, a short circuit or disconnection between the gate and the source is caused, which causes a problem that the yield is reduced.

In view of the above problems, the present invention provides a thin film transistor and a method for manufacturing the same, which do not cause deterioration in crystallinity or disconnection due to unevenness of a substrate of a semiconductor layer constituting a channel region and a source / drain region. It is the main purpose.

[0010]

According to the present invention, there is provided a thin film transistor, comprising: a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; A semiconductor layer formed thereon and having a channel region, a source region, and a drain region;
A planarizing insulating layer formed on the side of the gate electrode.

Further, in the method of manufacturing a thin film transistor according to the present invention, a step of forming a gate electrode having a planarizing insulating layer on a side portion on a substrate; a step of forming a gate insulating layer on the gate electrode; The semiconductor device is configured to include a step of selectively forming a semiconductor layer on a layer and a step of implanting an impurity serving as a donor or an acceptor into the semiconductor layer to form a source region and a drain region in the semiconductor layer.

In the above structure, it is preferable that the flattening insulating layer is formed by anodic oxidation of the gate electrode material because the process can be simplified.

According to the above configuration, since the surface irregularities due to electrode formation are reduced by anodic oxidation other than the pattern of the Al or Ta electrode, the crystallinity of the semiconductor layer formed thereon is improved. Although the reason is not clear, it is considered that the crystal growth was homogenized. By homogenizing the film quality of the semiconductor layer, a thin film transistor with a high yield can be obtained, and at the cross portion between the gate electrode and the source electrode, the coverage of the interlayer insulating film is improved by forming the taper of the gate electrode, and the short between the gate and the source is improved. And disconnection disappear.

In the case where the flattening insulating layer is formed by anodic oxidation, the volume of Al increases about 1.4 times, so that the thickness of the oxide film becomes larger than that of the Al metal part. However, since the change is gradual, a stepped portion defect does not occur.
Further, the portion to be anodized can be limited to only the transistor portion.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin film transistor and a method of manufacturing the same according to an embodiment of the present invention will be described below with reference to FIGS.

(First Embodiment) First, a method of manufacturing a thin film transistor according to a first embodiment of the present invention will be described with reference to FIG.

On a transparent substrate 11 such as glass, SiO ₂
The base insulating film 12 made of
Then, a conductive film (gate electrode material layer) made of Ta is formed to a thickness of 200 nm. Thereafter, a predetermined resist pattern 13 is formed in the gate electrode region on the Ta film by photolithography (FIG. 1A). Next, the Ta film is formed into a resist pattern 1
3 to form a flattened insulating layer 14 made of an anodized film. The condition is 5 mA / c with a 1% aqueous oxalic acid solution.
m ² and 100 V for 20 minutes (FIG. 1B). As a result, the planarization insulating layer 14 obtained by anodizing the gate electrode material layer on the side of the gate electrode 15 is formed.

Next, after removing the resist pattern 13,
A gate insulating layer 16 made of SiO _{2 is} formed to a thickness of 200 nm at 270 ° C. by a plasma CVD method (FIG. 1).
(C)) Further, a-Si is further formed thereon by plasma CVD.
The film is formed using an apparatus at 270 ° C. so as to have a film thickness of 50 nm. Thereafter, the above-mentioned a-Si is crystallized using a XeCl excimer laser having a wavelength of 308 nm to form a polysilicon layer 17 serving as a semiconductor layer (FIG. 1D).

Next, a resist pattern 18 is formed again so as to cover the channel region.
By implanting impurities such as phosphorus and boron into the polysilicon layer 17 by ion doping using the mask as a mask, a source region 17b and a drain region 17c are formed in the polysilicon layer 17 with the channel region 17a interposed therebetween (FIG. 1 (e)). Thereafter, an interlayer insulating film 19 made of SiO _{2 is} formed to a thickness of 400 nm by a normal pressure CVD method (FIG. 1).
(F)). Then, a contact hole 110 is opened,
A Ti film and an Al film are formed to have a thickness of 80 nm and 350 nm, respectively. Finally, a Ti and an Al film are formed in a predetermined shape by dry etching and wet etching, respectively, to form a source / drain electrode 111, and a polysilicon TFT is completed (FIG. 1 (g)).

As described above, according to the present embodiment, the semiconductor layers constituting the channel region, the source region, and the drain region are formed on the surface planarized by the planarization insulating layer. It is possible to prevent the crystallinity of the semiconductor layer from being lowered due to the convex shape of the gate electrode and the occurrence of disconnection or the like.

Actually, when the tape is formed by the conventional method, the taper of the Ta electrode has an inclination of 45 degrees or more, and when the crystal state of the semiconductor layer is observed by TEM, non-uniformity is observed in some places. Irregularities also occurred. However, in the polycrystalline TFT formed by the method of the present embodiment, the semiconductor crystal was also uniformly formed, and the crystal was large and the size was uniform. Therefore, the transistor characteristics in the substrate were stabilized, and the yield was improved.

The present invention can be variously modified. For example, although polycrystalline silicon is used as the semiconductor, single crystal silicon, a polycrystal of an Si—Ge compound, or a single crystal may be used. Although the film thickness is set to 50 nm, the thickness is not limited to this and may be 10 nm or more for forming a channel. However, considering the stability of the film formation and the photoconductivity, the thickness is preferably from 20 nm to 150 nm.

As a method of forming a gate insulating layer, a-Si and SiO ₂ were continuously formed by using plasma CVD, but normal pressure CVD, sputtering, low pressure CVD, and ECR-
SiO ₂ can also be deposited by a CVD method or the like. further,
Other than the above, as the source / drain electrodes, Al alloy, Ta, Cr, Ti, Mo, Mo-Ta alloy, Mo-
Metals such as W alloys, Cu, various kinds of silicides and the like, and laminated films thereof may be used, but from the viewpoint of resistance value, Al alloys and Cu
It is desirable to include

When a resist pattern for forming a channel portion is formed, a self-aligned pattern is formed by performing backside exposure. On the other hand, if exposure is performed from the surface, after ion doping, the poly-Si portion between the gate width and the channel width becomes an offset portion, and the off-leak characteristic of the transistor can be improved.

Further, in this embodiment, a material obtained by anodizing the gate electrode material layer is used as the flattening insulating layer.
It is not necessary to use an anodic oxide layer, and an insulating layer may be formed on the side of the gate electrode. However, in this embodiment mode, patterning of the gate electrode and formation of the planarization insulating layer can be performed at the same time in the state where one resist pattern is formed.

Embodiment 2 Next, a method of manufacturing a thin film transistor according to Embodiment 2 of the present invention will be described with reference to FIG.

On a light transmitting substrate 11 such as glass, SiO ₂
The base insulating film 12 made of
Then, a conductive film containing Al as a main component is formed to a thickness of 200 nm. After that, a predetermined resist pattern 13 formed so as to cover the gate electrode region with the Al film is formed (FIG. 1A).

Next, the Al film is anodized using the resist pattern 13. The conditions were a 1% mixed solution of citric acid and ethylene glycol at 1 mA / cm ² at 140 V for 20 minutes (FIG. 1 (b)). After removing the resist pattern 13, a gate insulating layer 16 made of SiO _{2 is} formed by plasma CVD so as to have a thickness of 200 nm at 270 ° C. (FIG. 1C). Thereafter, a-Si is formed into a film having a thickness of 50 nm at 270 ° C. by a plasma CVD apparatus, and is crystallized using a XeCl excimer laser having a wavelength of 308 nm to form polycrystalline silicon 6 serving as a semiconductor layer ( FIG. 1 (d)). Impurities such as phosphorus and boron are ion-implanted into the polysilicon layer 17 by ion doping using the resist as a mask, thereby forming a source region 17b and a drain region 17c in the polysilicon layer 17 with the channel region 17a interposed therebetween ( FIG. 1 (e)).

Next, an interlayer insulating film 19 made of SiO _{2 is} formed to a thickness of 400 nm by normal pressure CVD (FIG. 1F). Thereafter, a contact hole 110 is opened, and a Ti film and Al
The films are formed to have a thickness of 80 nm and 350 nm, respectively. Finally, Ti and Al films are formed in a predetermined shape by dry etching and wet etching, respectively, to form source / drain electrodes 111, and a polysilicon TFT is completed (FIG. 1 (g)).

Also in this embodiment, since the unevenness of the surface on which the semiconductor layer is formed is reduced, a polysilicon layer having excellent crystallinity can be obtained as in the first embodiment. Actually, when the Al electrode is formed by the conventional method, the taper of the Al electrode has an inclination of 45 degrees, and when the crystal state of the semiconductor layer is observed by TEM, unevenness in crystallinity is observed in some places, and surface irregularities occur. I was However, in the polycrystalline TFT formed by the method of the present embodiment, the semiconductor crystal was also uniformly formed, and the crystal was large and the size was uniform.
Therefore, the transistor characteristics in the substrate were stabilized, and the yield was improved.

It is needless to say that various modifications can be made in the present embodiment as in the first embodiment.

[0032]

According to the present invention, a TFT having an inverted staggered structure in which a poly-Si semiconductor layer is formed via a gate insulating layer because, for example, a gate electrode material layer is flattened by anodic oxidation.
In the case of an array, since there is almost no irregularity of the Si base, crystallization can be performed homogeneously, and the characteristics of the transistor can be improved. By the flattening of the gate electrode wiring, a short circuit at the cross portion with the source electrode wiring is also eliminated, and the yield is improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a manufacturing process of a thin film transistor according to an embodiment of the present invention.

FIG. 2 is a sectional view of a manufacturing process of a conventional thin film transistor.

[Explanation of symbols]

REFERENCE SIGNS LIST 11 translucent substrate 12 base insulating film 13 resist pattern 14 planarization insulating layer 15 gate electrode 16 gate insulating layer (SiO ₂ ) 17 polysilicon layer 17 a channel region 17 b source region 17 c drain region 18 resist pattern 19 interlayer insulating film (SiO ₂ ) 110 contact hole 111 source / drain electrode (Al / Ti) 21 translucent glass substrate 22 base insulating film 23 resist pattern 24 gate electrode 25 gate insulating layer (SiO ₂ ) 26 polysilicon layer 27 resist pattern 26 a channel region 26 _b Source region 26c drain region 27 resist pattern 28 interlayer insulating film (SiO ₂ ) 29 contact hole 210 source / drain electrode (Al / Ti)

Claims (5)

[Claims] A gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; a semiconductor layer formed on the gate insulating layer and having a channel region, a source region, and a drain region. And a planarization insulating layer formed on a side portion of the gate electrode. 2. The method according to claim 1, wherein the planarizing insulating layer is formed by anodic oxidation of a gate electrode material.
3. The thin film transistor according to claim 1. 3. The thin film transistor according to claim 1, wherein the gate electrode is made of a metal containing Al or Ta as a main component. 4. A step of forming a gate electrode having a planarization insulating layer on a side portion on a substrate, a step of forming a gate insulating layer on the gate electrode, and selectively forming a semiconductor layer on the gate insulating layer. Forming a source region and a drain region in the semiconductor layer by injecting an impurity serving as a donor or an acceptor into the semiconductor layer. 5. After forming a gate electrode material layer on a substrate,
Forming a resist pattern covering a gate electrode region, and thereafter anodizing the gate electrode material layer in a region where the resist pattern is not formed, thereby forming a planarization insulating layer on the side of the gate electrode. Claim 4
3. The method for manufacturing a thin film transistor according to item 1.