JPH11345952A - Semiconductor device and operation thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the semiconductor device which can achieve high-speed operation, low voltage and low power consumption, and operates as a non- volatile memory in the long life with the high holding action being maintained. SOLUTION: On the surface of a silicon substrate 31, an n-type well region 32 is formed. At the surface of the well region, a source region 33 comprising WSi2 is embedded. At the other position of the surface of the n-type well region 32, a drain region 34 comprising an n<+> layer is formed. On the n-type well region 32, the source region 33 and the drain region 34, the first gate insulating film 35 comprising SiO2 is formed. On the film 35, a floating gate electrode 36 comprising silicon nitride(SiN) is formed. On the floating gate electrode 36, the second gate insulating film 37 comprising SiO2 is formed. Over the film 37, a control gate electrode 38 comprising polysilicon is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device having a Schottky contact and a method of operating the same.

[0002]

2. Description of the Related Art In manufacturing a conventional MOSFET (metal oxide semiconductor field effect transistor), a gate insulating film and a gate electrode are sequentially provided on a semiconductor substrate. Then, by performing ion implantation using the gate electrode as a mask, a source region and a drain region aligned with the gate electrode in a self-aligned manner are formed.

On the other hand, EPROM (Erasable and Programmable Read Only) is a semiconductor memory that can be substituted for a hard disk and a floppy disk as magnetic memories.
y Memory) and EEPROM (Electrically Erasable an)
Non-volatile memories such as d Programmable Read Only Memory) have attracted attention. In EPROM and EEPROM memory cells, carriers are stored in a floating gate electrode, data is stored depending on the presence or absence of carriers, and data is read out by detecting a change in threshold voltage due to the presence or absence of carriers. . In particular, EEPRO
M is a flash EEPROM which erases data in the entire memory cell array or divides the memory cell array into arbitrary blocks and erases data in block units.
There is ROM. The flash EEPROM is used in various portable devices because it has features of being capable of increasing capacity, lowering power consumption, increasing speed, and having excellent shock resistance.

[0004]

SUMMARY OF THE INVENTION Conventional flash EE
In a PROM, a writing operation of injecting carriers into the floating gate electrode and an erasing operation of discharging carriers from the floating gate electrode require 10 V between the control gate electrode and the substrate.
It is necessary to apply the above voltage. In order to retain carriers in the floating gate electrode for a long period of time, the thickness of the oxide film surrounding the floating gate electrode cannot be reduced to 8 to 10 nm or less. Therefore, it is said that it is difficult to lower the voltage in the memory cell unless the structure itself of the memory cell is changed (NIKKEI MICRODEV).
(See the special article in the ICES January and February 1997 issues.)

It is an object of the present invention to provide a semiconductor device which operates as a non-volatile memory capable of high-speed operation, low voltage, and low power consumption while maintaining a long life and high holding operation.

[0006]

According to the present invention, there is provided a semiconductor device comprising: a first layer made of a semiconductor of one conductivity type; a second layer in Schottky contact with the first layer; And an electrode unit for applying an electric field to the interface for changing the thickness of a Schottky barrier formed at the interface between the first layer and the second layer. The point is to have a larger band gap.

That is, a Schottky barrier is formed at the interface between at least one of the source region and the drain region and the semiconductor substrate. Therefore, the thickness of the Schottky barrier formed at the interface can be changed by applying an electric field to the interface between the first layer and the second layer by the electrode portion. Thus, current flowing between the first layer and the second layer can be controlled.

In this case, the thickness of the Schottky barrier is determined by the impurity concentration of the semiconductor of one conductivity type and the intensity of the electric field applied by the electrode portion. The impurity concentration of a semiconductor of one conductivity type can be controlled with high accuracy. Therefore, a semiconductor device which can be highly integrated without increasing the cost and can be manufactured with high accuracy can be obtained. The electrode portion includes a first insulating film formed over the second layer, a first electrode layer formed over the first insulating film, and a first insulating film formed over the first electrode layer. 2 insulating film, and a second electrode layer formed on the second insulating film.

In this case, by applying a voltage to the second electrode layer, an electric field can be applied to the interface between the first and second layers via the first insulating film. When a bias is applied between the first layer and the second layer, electrons transmitted through the Schottky barrier are rapidly accelerated by an electric field formed by the bias to become hot electrons.
It is implanted into the first electrode layer. Accordingly, carriers can be efficiently injected into the first electrode layer without applying a high voltage to the electrode portion.

The energy of the carrier is determined by the bias applied between the first layer and the second layer, and the probability of the carrier passing through the Schottky barrier is determined by the electric field applied to the interface by the second electrode layer. It is determined. in this case,
Since carriers having low energy can be injected into the first electrode layer, the first insulating film is prevented from being damaged by the carriers injected into the first electrode layer. Therefore, a semiconductor device which operates as a nonvolatile memory capable of high-speed operation, low voltage, and low power consumption while maintaining high holding operation can be obtained.

Further, a material having a larger band gap than the first layer is used as a material of the first electrode layer. As a result, the energy required to excite electrons from the valence band to the conduction band in the first electrode layer becomes larger than that in the first layer, and even if high-energy electrons are injected into the first electrode layer. Hot holes are not easily generated, and holes are hardly injected into the first insulating film. Therefore, it is possible to suppress the deterioration of the insulating film, which is said to progress rapidly due to the injection of holes, and provide a long-life nonvolatile memory with a large number of data rewrites.

It is preferable that the first electrode layer has a band gap smaller than the band gap of the first insulating film and the band gap of the second insulating film. In addition, the first layer and the second layer
It is desirable that the length from the interface with the first layer to the end of the electrode portion on the first layer side is 50 nm or more. In this case, the electrode portion covers a region of the first layer in which carriers transmitted from the second layer through the Schottky barrier to the first layer side are accelerated to an energy exceeding the barrier of the first insulating film. Therefore, carriers are easily injected from the first layer into the electrode portion. Therefore, a nonvolatile memory is realized.

Further, the electrode portion may be arranged so as to form an angle larger than 0 degree with respect to the interface between the first layer and the second layer. In this case, an electric field for changing the thickness of the Schottky barrier by the electrode portion can be easily applied to the interface. The method of operating a semiconductor device according to the present invention may further comprise the steps of:
And a second layer that is in Schottky contact with the first layer, wherein a voltage is applied to an interface between the first layer and the second layer by an electrode portion, and The point is that data is written by injecting hot carriers from the layer into the electrode portion, and data is erased by injecting hot carriers of the opposite conductivity type to the electrode portion at the time of data writing. And

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (1) First Embodiment FIG. 1 is a schematic sectional view of a nonvolatile memory according to a first embodiment of the present invention. In FIG. 1, an n-type well region 32 having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ is formed on a surface of a p-type single crystal silicon substrate 31. A 200 nm-thick source region 33 made of WSi ₂ is embedded in the surface of the n-type well region 32. At another position on the surface of the n-type well region 32, a drain region 34 made of an n ⁺ layer is formed.

On the n-type well region 32, the source region 33 and the drain region 34, a film of SiO _{2 having a} thickness of 5 nm is formed.
Of the first gate insulating film 35 is formed. On the first gate insulating film 35, a 250 nm-thick floating gate electrode 36 made of silicon nitride (SiN) is formed. On the floating gate electrode 36, a 5 nm-thick second gate insulating film 37 made of SiO ₂ is formed. Further, a control gate electrode 38 made of polysilicon and having a thickness of about 250 nm is formed on the second gate insulating film 37.

A source electrode 39 is formed on the source region 33, and a drain electrode 40 is formed on the drain region 34. The source electrode 39 is a source line (not shown)
And the drain electrode 40 is connected to a bit line (not shown).
, And the control gate electrode 38 is connected to a word line (not shown). Note that the distance L1 from the interface 204 between the source region 33 and the n-type well region 32 to the drain region 34 is set to 50 nm or more.

A source potential VS is applied to the source electrode 39, a drain potential VD is applied to the drain electrode 40, and a control gate potential VCG is applied to the control gate electrode 38. In the present embodiment, the source potential VS is a predetermined negative potential, and the drain potential VD is a predetermined positive potential.
As a result, a reverse bias is applied to the interface 204 between the n-type well region 32 and the source region 33.

Next, the write operation of the nonvolatile memory of FIG. 1 will be described with reference to the energy band diagram of FIG. -3 V is applied to the source electrode 39 and the drain electrode 4
+3 V is applied to 0, and +3 V is applied to the control gate electrode 38. Note that the potential of the silicon substrate 31 is kept at 0V. Thus, the positive potential of 3 to 6 V is applied to the control gate electrode 38.
Is applied, the thickness of the Schottky barrier at the interface 204 near the first gate insulating film 35 is reduced, and a reverse current flows through the Schottky barrier. When a reverse bias of 6 V is applied to the Schottky barrier formed at the interface 204, electrons transmitted (tunneled) through the Schottky barrier generate 3.2 eV or more over a short distance equal to or less than the mean free path of the electrons due to a strong electric field generated near the Schottky barrier. Accelerated to
3.2 eV is the first value as viewed from the conduction band of the n-type well region 32.
Is the height of the barrier of the gate insulating film 35.

As a result, almost all of the electrons transmitted through the Schottky barrier acquire energy exceeding the barrier of the first gate insulating film 35 and become hot electrons.
Due to the positive potential applied to the control gate electrode 38, it is injected into the floating gate electrode 36 with extremely high efficiency. As described above, since hot electrons are injected into the floating gate electrode 36 with extremely high efficiency, a high-speed write operation can be performed.

In this case, the energy of the electrons can be adjusted by the voltage applied between the source region 33 and the drain region 34, and the probability of the electrons passing through the Schottky barrier is controlled by the control gate potential applied to the control gate electrode 38. It can be adjusted by VCG. Therefore, when the hot electrons obtain energy slightly exceeding the barrier 3.2 eV of the first gate insulating film 35, the floating gate electrode 36
Can be injected. Thus, compared to the conventional method of injecting electrons by FN tunnel current (Fowler-Nordheim Tunnel Current), the electrons injected into the floating gate electrode 36 have a low energy of 1/2 to 1/3 of the conventional method.

The thickness of the Schottky barrier when no voltage is applied is determined by the type of metal that is brought into contact with the silicon substrate, the conductivity type (n-type or p-type) of the silicon substrate, and the impurity concentration. The impurity concentration can be controlled more precisely than the processing accuracy. Therefore, a non-volatile memory having a certain performance can be manufactured with high accuracy irrespective of processing accuracy, and the degree of integration can be easily improved.

Further, it is not necessary to generate a high voltage of 10 to 20 V using a charge pump at the time of a write operation, and a compact memory chip with low power consumption can be manufactured. Further, in the present invention, the floating gate electrode 3
As a material of No. 6, the band gap is larger than that of Si, and the first gate insulating film 35 and the second gate insulating film 37 are used.
Silicon nitride (SiN) having a smaller band gap than (SiO ₂ ) is used. As a result, the energy required to excite electrons from the valence band to the conduction band becomes larger than that of silicon in the floating gate electrode 36, and hot holes are generated even when high-energy electrons are injected into the floating gate electrode 36. It is difficult to inject holes into the first gate insulating film 35. Therefore, it is possible to suppress the deterioration of the insulating film, which is said to progress rapidly due to the injection of holes, and provide a nonvolatile memory in which data is frequently rewritten.

Here, in the nonvolatile memory of FIG.
The control gate potential VCG applied to the control gate electrode 38 is changed.
Simulation of the change in the thickness of the Schottky barrier when
Data. In this calculation, the source potential VS is
-3 V, drain potential VD +3 V, silicon
The potential of the substrate 31 is set to 0 V, and the control gate potential VCG is set to-
The voltage was changed from 3V to + 6V. n-type well region 32
The impurity concentration is 1 × 10 ^Fifteencm^-3And the first gate insulation
The thickness of the film 35 was 8 nm. Table 1 shows the calculation results.
You.

[0024]

[Table 1]

As shown in Table 1, the control gate voltage VCG
Was changed from −3 V to +6 V, the thickness of the Schottky barrier at the interface 204 between the n-type well region 32 and the source region 33 changed from 170 nm to 1.6 nm. As described above, the thickness of the Schottky barrier at the interface 204 can be changed by changing the control gate potential VCG.

Next, the relationship between the change in electrical resistance when electrons or current flows through the Schottky barrier at the interface 204 and the change in the thickness of the Schottky barrier was derived from comparison with literature data. In this calculation, the source potential VS was -1 V, the drain potential VD was 0 V, the potential of the silicon substrate 31 was 0 V, and the control gate potential VCG was 0 V. Also,
The impurity concentration of the n-type well region 32 was set to 1 × 10 ²⁰ cm ⁻³ and 1 × 10 ¹⁹ cm ^−3, and the thickness of the first gate insulating film 35 was set to 8 nm.

The impurity concentration of the n-type well region 32 is 1 × 1
At 0 ²⁰ cm ^-3 , the thickness of the Schottky barrier is 1.6 n
m. On the other hand, according to literature data, the impurity concentration of the n-type well region is set to 1 × 10 ²⁰ cm ⁻³ , and WSi ₂ /
The electric resistance when electrons are tunneled by applying a reverse bias to the Schottky barrier at the Si interface is sufficiently low at 100Ω / μm ² or less.

The impurity concentration of the n-type well region 32 is 1 × 1
The thickness of the Schottky barrier at 0 ¹⁹ cm ^-3 is 4.8 nm.
It became. On the other hand, according to literature data, the impurity concentration of the n-type well region is set to 1 × 10 ¹⁹ cm ⁻³ , and WSi ₂ / S
When a reverse bias is applied to the Schottky barrier at the i interface to tunnel electrons, the electric resistance is 10 ⁹ Ω / μm ² or more. Table 2 shows the results.

[0029]

[Table 2]

From Tables 1 and 2, the relationship between the control gate potential VCG and the electrical resistance of the Schottky barrier was determined using the thickness of the Schottky barrier as a medium. Table 3 shows the results.

[0031]

[Table 3]

From Table 3, the control gate potential VCG is set to -3V
And 6V, the electrical resistance when electrons tunnel through the Schottky barrier in the vicinity of the first gate insulating film 35 is from 1 × 10 ⁹ Ω / μm ² or more to 100 Ω / μm ^2.
It was found to change to below μm ² . As shown in Table 3, when the control gate potential VCG is 6 V, electrons are accelerated to 3.2 eV, which is required when electrons are injected into the floating gate electrode 36 beyond the barrier of the first gate insulating film 35. Is 20 nm. 3e in substance
The mean free path of the electrons of V is 10 to 20 nm, and 1e
Since the mean free path of the electrons of V is about 100 nm, it is considered that almost all the electrons accelerated in the vicinity of the first gate insulating film 35 are accelerated to 3.2 eV or more.

That is, when the control gate potential VCG is 6 V, the acceleration is made to 3.2 eV over a short distance equal to or less than the mean free path. Therefore, almost all the electrons accelerated in the vicinity of the first gate insulating film 35 are accelerated to 3.2 eV or more and injected into the floating gate electrode 36 very efficiently. In the present embodiment, since the position where the injection of electrons occurs is set near one end of the floating gate electrode 36, the injection of electrons occurs from one end of the floating gate electrode 36 toward the center and the other end. . The electrons accelerated to 3.2 eV or more are injected into the floating gate electrode 36 if the trajectory can be slightly changed in the direction of the floating gate electrode 36 by the electric field received from the control gate electrode 38, so that the injection efficiency and the injection speed are increased. Become.

By the way, in the erasing operation of the nonvolatile memory shown in FIG. 1, +3 V is applied to the source electrode 39, the drain electrode 40 is opened, and -3 V is applied to the control gate electrode 38.
Is applied. Note that the potential of the silicon substrate 31 is kept at -2V. By setting such a potential relationship,
The n-well region 32 is depleted, and the first gate insulating film 35
, The thickness of the Schottky barrier with respect to the hole at the interface 204 near the hole is reduced, and holes that have passed through the thinned Schottky barrier from the source region 33 to the n-well region 32 are injected. Through this Schottky barrier (tunneling)
The generated holes are accelerated by a strong electric field generated near the Schottky barrier.

As a result, almost all of the holes transmitted through the Schottky barrier acquire energy exceeding the barrier of the first gate insulating film 35 and become hot holes, and are extremely reduced by the negative potential applied to the control gate electrode 38. It is injected into the floating gate electrode 36 with high efficiency. As a result, in the nonvolatile memory, the hot electrons previously injected into the floating gate electrode 36 are canceled by the newly injected hot holes, thereby erasing the written data.

Since the hot holes are injected into the floating gate electrode 36 with extremely high efficiency, similarly to the above-mentioned hot electrons, a high-speed erasing operation can be performed. In addition,
The n-type well region 32 functions as a drain as it is,
When the n-type well region 32 is fixed at a constant potential or when a voltage or current is taken out from the drain, a drain region 34 made of an n ⁺ layer is provided on the surface of the n-type well region 32 as in the present embodiment. Is preferred.

It is preferable that the thickness of the first gate insulating film 35 and the second gate insulating film 37 be 5 nm or less. As a result, it is possible to realize an improvement in the driving capability of the element and a reduction in the voltage, as well as writing, reading, and reading.
High-speed erasing operations can be realized. Further, in recent years, the thickness of a gate insulating film used in an LSI has been reduced in thickness with the development of fine processing technology.
By thinning the gate insulating film 35 and the second gate insulating film 37, the conditions of the manufacturing process can be standardized, and the process can be simplified.

(Second Embodiment) FIG. 3 is a schematic sectional view of a nonvolatile memory cell according to a second embodiment of the present invention. In FIG. 3, an n-type well region 42 having an impurity concentration of 1 × 10 ¹⁵ cm ⁻³ is formed on a surface of a p-type single crystal silicon substrate 41.
Are formed. LOCO is formed on the n-type well region 42.
A field oxide film 49 is formed by using the S method.
At the center of the n-type well region 42, a drain region 44 composed of an n ⁺ layer is formed.

In this embodiment, the common drain region 44
And a pair of memory cells 40a, 40
b is formed. Note that the drain region 44 actually exists at a position different from the cross section in FIG. On the surface of the n-type well region 42 on both sides of the drain region 44, a source region 43 of WSi _{2 having a} thickness of 100 nm is formed.
Is embedded. A 5 nm-thick first gate insulating film 45 made of SiO ₂ is formed on the n-type well region 42 and the source region 43. On the first gate insulating film 45, a floating gate electrode 46 made of polysilicon and having a thickness of 100 nm is formed.

On the floating gate electrode 46 and the first gate insulating film 45, a 5 nm-thick second gate insulating film 47 made of SiO ₂ is formed. Further, on the second gate insulating film 47, a film thickness of about 30
A control gate electrode 48 of 0 nm is formed. Each of the memory cells 40a and 40b includes an n-type well region 42, a source region 43, a drain region 44, a first gate insulating film 45, a floating gate electrode 46, a second gate insulating film 47, and a control gate electrode 48. Is done. Upper structure (not shown) consisting of a wiring layer and the like sequentially on control gate electrode 48
Forming an integrated circuit.

The source region 43 and the n-type well region 4
The distance L2 from the interface 205 to the drain region 44 to the end of the floating gate electrode 46 is set to 50 nm or more. A source potential VS is applied to the source region 43, a drain potential VD is applied to the drain region 44, and a control gate potential VCG is applied to the control gate electrode 48. In the present embodiment, the source potential VS is a predetermined negative potential, and the drain potential VD is a predetermined positive potential.
As a result, a reverse bias is applied to the interface 205 between the n-type well region 42 and the source region 43.

Next, the write operation of the memory cells 40a and 40b in FIG. 3 will be described. -3V is applied to the source region 43, + 2V is applied to the drain region 44, and + 3V is applied to the control gate electrode 48. Thus, the thickness of the Schottky barrier at the interface 205 near the first gate insulating film 45 is reduced, and a reverse current flows through the Schottky barrier. At this time, the electrons transmitted through the Schottky barrier are rapidly accelerated by the electric field applied between the source region 43 and the drain region 44 to become hot electrons and injected into the floating gate electrode 46.

Therefore, it is not necessary to generate a high voltage of 10 to 20 V using a charge pump during a write operation, and a compact memory chip with low power consumption can be manufactured. The memory cells 40a, 40 in FIG.
In the erasing operation of 0b, +3 V is applied to the source region 43,
The drain region 44 is opened, and -3 V is applied to the control gate electrode 48. The potential of the silicon substrate 41 is kept at -2V.

By setting such a potential relationship, the n-well region 42 is depleted, the thickness of the Schottky barrier for holes at the interface 205 near the first gate insulating film 45 is reduced, and the Holes penetrating the thinned Schottky barrier are injected into the well region 42. The holes transmitted (tunneled) through the Schottky barrier are accelerated by a strong electric field generated near the Schottky barrier.

As a result, almost all of the holes transmitted through the Schottky barrier acquire energy exceeding the barrier of the first gate insulating film 45 to become hot holes, and extremely low due to the negative potential applied to the control gate electrode 48. It is injected into the floating gate electrode 46 with high efficiency. As a result, in the nonvolatile memory, the hot electrons previously injected into the floating gate electrode 46 are canceled by the newly injected hot holes, thereby erasing the written data.

Since the hot holes are injected into the floating gate electrode 46 with extremely high efficiency, similarly to the above-mentioned hot electrons, a high-speed erasing operation can be performed. In addition,
The n-type well region 42 works as a drain as it is,
When the n-type well region 42 is fixed at a constant potential or when a voltage or current is taken out from the drain, a drain region 43 made of an n ⁺ layer is provided in the n-type well region 42 as in this embodiment.

(Third Embodiment) FIG. 4 is a schematic sectional view of a nonvolatile memory according to a third embodiment of the present invention.
In FIG. 4, on the surface of a p-type single crystal silicon substrate 51,
A drain region 52 made of an n ⁺ layer is formed. On drain region 52, n ⁻ layer 53 is formed.
On n ⁻ layer 53, source region 54 made of WSi ₂ is formed.

N^-On both sides of the layer 53 and the source region 54
Is SiO_TwoThrough a first gate insulating film 55 made of
The floating gate electrodes 56a and 56b made of polysilicon are
Each is formed. Floating gate electrodes 56a, 56
b on the top and side surfaces _TwoSecond gate consisting of
A control gate electrode made of polysilicon is provided via an insulating film 57.
Poles 58a and 58b are formed respectively.

In this embodiment, the memory cell 50 is located on both sides of the common n ⁻ layer 53 and the source region 54.
a, 50b are formed. Memory cells 50a, 50
b each include a drain region 52, an n ⁻ layer 53, a source region 54, a first gate insulating film 55, and a floating gate electrode 56.
a, 56b, a second gate insulating film 57, and control gate electrodes 58a, 58b.

The distance L3 from the interface 206 between the n ^- layer 53 and the source region 54 to the ends of the floating gate electrodes 56a and 56b toward the drain region 52 is set to 50 nm or more. The source potential VS is applied to the source region 54, the drain potential VD is applied to the drain region 52, and the control gate potential VCG is applied to the control gate electrodes 58a and 58b. In the present embodiment, the source potential V
S is a predetermined negative potential, and the drain potential VD is a predetermined positive potential. Thereby, n ⁻ layer 53 and source region 54
A reverse bias is applied to the interface 206 with.

Next, the write operation of the memory cell 50a of FIG. 4 will be described. A voltage of −3 V is applied to the source region 54, a voltage of +2 V is applied to the drain region 52, and a control gate electrode 58 is applied.
+ 3V is applied to a. Thereby, the control gate electrode 5
On the 8a side, the thickness of the Schottky barrier at the interface 206 near the first gate insulating film 55 is reduced, and a reverse current flows through the Schottky barrier. At this time, the electrons transmitted through the Schottky barrier are transferred to the source region 54 and the drain region 52.
Are rapidly accelerated by the electric field applied between them and become hot electrons, which are injected into the floating gate electrode 56a.

Therefore, it is not necessary to generate a high voltage of 10 to 20 V using the charge pump during the write operation, and a compact memory chip with low power consumption can be manufactured. In the erasing operation of the memory cell 50a in FIG. 4, +3 V is applied to the source region 54, the drain region 52 is opened, and -3 V is applied to the control gate electrode 58a. Note that the potential of the silicon substrate 51 is −
Hold at 2V.

By setting such a potential relationship, n ⁻ layer 53 is depleted, the thickness of the Schottky barrier for holes at interface 206 near first gate insulating film 55 is reduced, and n ⁻ layer 53 is reduced from source region 54 to n. ^- a hole passing through the thinned Schottky barrier layer 53 is injected. The holes transmitted (tunneled) through the Schottky barrier are accelerated by a strong electric field generated near the Schottky barrier.

As a result, almost all of the holes transmitted through the Schottky barrier acquire energy exceeding the barrier of the first gate insulating film 55 to become hot holes, and are extremely reduced by the negative potential applied to the control gate electrode 58a. It is injected into the floating gate electrode 56a with high efficiency. as a result,
In a nonvolatile memory, the floating gate electrode 5
The hot electrons injected into 6a are canceled by the newly injected hot holes, thereby erasing the written data.

The hot holes are formed with the floating gate electrode 56a with extremely high efficiency similarly to the above-mentioned hot electrons.
, A high-speed erase operation can be performed. (Fourth Embodiment) FIG. 5 is a schematic sectional view of a nonvolatile memory according to a fourth embodiment of the present invention.

In FIG. 5, a p-type single crystal silicon substrate 6
1 on the surface⁺A drain region 62 composed of a layer is formed.
Have been. On the drain region 62, a concave n^-Layer 63
Are formed. n^-On the layer 63, WSi_TwoConsists of
A T-shaped source region 64 is formed. n^-Layer 63
And SiO 2 on both sides of the source region 64._TwoConsisting of
1 through a gate insulating film 65.
The idle gate electrodes 66a and 66b are formed respectively.
You. On the upper and side surfaces of the floating gate electrodes 66a and 66b
Is SiO _TwoThrough a second gate insulating film 67 made of
The control gate electrodes 68a and 68b made of polysilicon are
Each is formed.

In this embodiment, the memory cells 60 are located on both sides of the common n ⁻ layer 63 and the source region 64.
a and 60b are formed. Memory cells 60a, 60
b each include a drain region 62, an n ⁻ layer 63, a source region 64, a first gate insulating film 65, and a floating gate electrode 66.
a, 66b, a second gate insulating film 67, and control gate electrodes 68a, 68b.

The distance L4 from the interface 207 between the n ⁻ layer 63 and the source region 64 to the ends of the floating gate electrodes 66a and 66b toward the drain region 62 is set to 50 nm or more. A source potential VS is applied to the source region 64, a drain potential VD is applied to the drain region 62, and a control gate potential VCG is applied to the control gate electrodes 68a and 68b. In the present embodiment, the source potential V
S is a predetermined negative potential, and the drain potential VD is a predetermined positive potential. Thereby, n ⁻ layer 63 and source region 64
A reverse bias is applied to the interface 207 with.

Next, the write operation of the memory cell 60a of FIG. 5 will be described. A voltage of −3 V is applied to the source region 64, a voltage of +2 V is applied to the drain region 62, and a control gate electrode 68 is applied.
+ 3V is applied to a. Thereby, the control gate electrode 6
On the 8a side, the thickness of the Schottky barrier at the interface 207 near the first gate insulating film 65 is reduced, and a reverse current flows through the Schottky barrier. At this time, the electrons transmitted through the Schottky barrier are converted into the source region 64 and the drain region 62.
Are rapidly accelerated by the electric field applied between them and become hot electrons, which are injected into the floating gate electrode 66a.

In this case, since a part of the interface 207 forms an angle smaller than 90 ° with respect to the side surface of the floating gate electrode 66a, electrons are injected into the floating gate electrode 66a at a predetermined angle. Therefore, the electron injection efficiency increases. In the erasing operation of the memory cell 60a in FIG. 5, +3 V is applied to the source region 64, the drain region 62 is opened, and -3 V is applied to the control gate electrode 68a. The potential of the silicon substrate 61 is kept at -2V.

By setting such a potential relationship, n ⁻ layer 63 is depleted, the thickness of the Schottky barrier against holes at interface 207 near first gate insulating film 65 is reduced, and n ⁻ layer 63 is reduced from source region 64 to n. ^- a hole passing through the thinned Schottky barrier layer 63 is injected. The holes transmitted (tunneled) through the Schottky barrier are accelerated by a strong electric field generated near the Schottky barrier.

As a result, almost all of the holes transmitted through the Schottky barrier acquire energy exceeding the barrier of the first gate insulating film 65 and become hot holes, and are extremely reduced by the negative potential applied to the control gate electrode 68a. It is injected into the floating gate electrode 66a with high efficiency. as a result,
In the non-volatile memory, the floating gate electrode 6
The hot electrons injected into 6a are canceled by the newly injected hot holes, thereby erasing the written data.

This hot hole forms the floating gate electrode 66a with extremely high efficiency similarly to the above-mentioned hot electron.
, A high-speed erase operation can be performed. FIG.
8 to FIG. 8 mainly show the source region 6 of the nonvolatile memory shown in FIG.
4 is a process cross-sectional view illustrating a forming method of No. 4; FIG. First, FIG.
As shown in (a), a SiN film 70 is formed on a p-type single crystal silicon substrate 61, and is patterned by patterning.
An opening 71 is formed at 0. Next, as shown in FIG. 6B, an SiO ₂ film 72 is formed on the entire surface. And FIG.
As shown in (c), the SiO ₂ film 72 is etched,
An SiO ₂ spacer 72 a is formed on the side surface of the SiN film 70 in the opening 71.

Next, as shown in FIG. 7D, the p-type single crystal silicon substrate 61 is etched using the SiN film 70 and the SiO ₂ spacer 72a as a mask to form a concave portion 73. Further, as shown in FIG. 7E, the SiO ₂ spacer 72a in the opening 71 is removed by wet etching. Thereafter, as shown in FIG.
Then, a source region 64 made of WSi ₂ is formed in the opening 71.

Next, as shown in FIG. 8G, the silicon substrate 61 is etched using the source region 64 as a mask. (Fifth Embodiment) FIG. 9 is a schematic sectional view of a nonvolatile memory according to a fifth embodiment of the present invention.

In FIG. 9, a p-type single crystal silicon substrate 8
1 on the surface⁺A drain region 82 composed of a layer is formed.
Have been. On the drain region 82, a concavely curved
N with face^-A layer 83 is formed. n^-On layer 83
Is a WSi having a convexly curved lower surface._TwoSaw consisting of
A semiconductor region 84 is formed. n^-Layer 83 and source area
On both sides of region 84, SiO_TwoThe first gate consisting of
Floating gate electrode made of polysilicon via edge film 85
86a and 86b are formed respectively. Floating gate
SiO 2 is formed on the upper and side surfaces of the electrodes 86a and 86b. _TwoFrom
From polysilicon through a second gate insulating film 87
Control gate electrodes 88a and 88b are formed, respectively.
ing.

In this embodiment, the memory cells 80 are located on both sides of the common n ⁻ layer 83 and the source region 84.
a, 80b are formed. Memory cells 80a, 80
Each of b is a drain region 82, an n ⁻ layer 83, a source region 84, a first gate insulating film 85, a floating gate electrode 86
a, 86b, a second gate insulating film 87, and control gate electrodes 88a, 88b.

A source potential VS is applied to the source region 84, a drain potential VD is applied to the drain region 82, and a control gate potential VCG is applied to the control gate electrodes 88a and 88b. In the present embodiment, the source potential VS
Is a predetermined negative potential, and the drain potential VD is a predetermined positive potential. Thereby, a reverse bias is applied to interface 208 between n ⁻ layer 83 and source region 84.

Next, the write operation of the memory cell 80a of FIG. 9 will be described. A voltage of −3 V is applied to the source region 84, a voltage of +2 V is applied to the drain region 82, and a control gate electrode 88 is applied.
+ 3V is applied to a. Thereby, the control gate electrode 8
On the 8a side, the thickness of the Schottky barrier at the interface 208 near the first gate insulating film 85 is reduced, and a reverse current flows through the Schottky barrier. At this time, the electrons transmitted through the Schottky barrier are transmitted to the source region 84 and the drain region 82.
Are rapidly accelerated by the electric field applied between them and become hot electrons, which are injected into the floating gate electrode 86a.

In this case, since a part of the interface 208 forms an angle smaller than 90 ° with respect to the side surface of the floating gate electrode 86a, electrons are injected into the floating gate electrode 86a at a predetermined angle. Therefore, the electron injection efficiency increases. In the erasing operation of the memory cell 80a in FIG. 9, +3 V is applied to the source region 84, the drain region 82 is opened, and -3 V is applied to the control gate electrode 88a. Note that the potential of the silicon substrate 81 is kept at -2V.

By setting such a potential relationship, n ⁻ layer 83 is depleted, the thickness of the Schottky barrier against holes at interface 208 near first gate insulating film 85 is reduced, and n ⁻ layer 83 is reduced from source region 84 to n. ^- a hole passing through the thinned Schottky barrier layer 83 is injected. The holes transmitted (tunneled) through the Schottky barrier are accelerated by a strong electric field generated near the Schottky barrier.

As a result, almost all of the holes that have passed through the Schottky barrier acquire energy exceeding the barrier of the first gate insulating film 85 and become hot holes, and are extremely reduced by the negative potential applied to the control gate electrode 88a. It is injected into the floating gate electrode 86a with high efficiency. as a result,
In the nonvolatile memory, the floating gate electrode 8
The hot electrons injected into 6a are canceled by the newly injected hot holes, thereby erasing the written data.

This hot hole forms the floating gate electrode 86a with extremely high efficiency similarly to the above-mentioned hot electron.
, A high-speed erase operation can be performed. FIG.
0 is a schematic process sectional view mainly showing a method of forming the source region 84 in the nonvolatile memory of FIG. First,
As shown in FIG. 10A, a p-type single crystal silicon substrate 8
1, a SiN film 90 is formed, and Si
An opening 91 is formed in the N film 90. And FIG.
As shown in (b), the p-type single-crystal silicon substrate 81 is hemispherically wet-etched using the SiN film 90 as a mask to form a curved concave portion 92.

Further, as shown in FIG. 10C, the source region 8 made of WSi ₂ is formed in the recess 92 and the opening 91.
4 is formed. Thereafter, as shown in FIG. 10D, the silicon substrate 81 is etched using the source region 84 as a mask. (Sixth Embodiment) FIG. 11 is a schematic sectional view of a nonvolatile memory according to a sixth embodiment of the present invention.

Referring to FIG. 11, an n-type well region 102 is formed on a surface of a p-type single crystal silicon substrate 101. A source region 103 made of WSi ₂ is buried in the surface of the n-type well region 102. Source area 10
3 has an angle smaller than 90 ° with respect to the surface of the n-type well region 102. A drain region 104 made of an n ⁺ layer is formed at another position of the n-type well region 102.

N-type well region 102, source region 103
A 250 nm thick floating gate electrode 106 made of polysilicon is formed on the drain region 104 with a 5 nm thick first gate insulating film 105 made of SiO ₂ interposed therebetween. On the floating gate electrode 106, SiO ₂
A control gate electrode 108 made of polysilicon and having a thickness of 250 nm is formed via a second gate insulating film 107 made of and having a thickness of 5 nm.

A source electrode 109 is formed on the source region 103, and a drain electrode 110 is formed on the drain region 104.
Are formed. The source electrode 109 has a source potential V
S is applied, and the drain potential V
D is applied, and the control gate potential VCG is applied to the control gate electrode 108. In the present embodiment, the source potential V
S is a predetermined negative potential, and the drain potential VD is a predetermined positive potential. As a result, a reverse bias is applied to the interface 209 between the n-type well region 102 and the source region 103.

Next, the write operation of the nonvolatile memory shown in FIG. 11 will be described. When -3 V is applied to the source region 103,
+2 V is applied to the drain region 104, and +3 V is applied to the control gate electrode 108. Thus, the thickness of the Schottky barrier at the interface 209 in the vicinity of the first gate insulating film 105 is reduced, and a reverse current flows through the Schottky barrier. At this time, the electrons transmitted through the Schottky barrier are rapidly accelerated by the electric field applied between the source region 103 and the drain region 104 to become hot electrons.
It is injected into the floating gate electrode 106.

In this case, the interface 209 is connected to the floating gate electrode 1
Since an angle is smaller than 90 ° with respect to the lower surface of the semiconductor substrate 06, electrons are injected into the floating gate electrode 106 at a predetermined angle. Therefore, the electron injection efficiency increases. FIG.
In the erasing operation of the nonvolatile memory of No. 1, +3 V is applied to the source region 103, the drain region 104 is opened, and -3 V is applied to the control gate electrode 108. In addition,
The potential of the silicon substrate 101 is kept at -2V.

By setting such a potential relationship, the n-well region 102 is depleted, the thickness of the Schottky barrier against holes at the interface 209 near the first gate insulating film 45 is reduced, and the
Holes that have passed through the thinned Schottky barrier are injected into the well region 102. The holes transmitted (tunneled) through the Schottky barrier are accelerated by a strong electric field generated near the Schottky barrier.

As a result, almost all of the holes transmitted through the Schottky barrier acquire energy exceeding the barrier of the first gate insulating film 105 and become hot holes, and are extremely reduced by the negative potential applied to the control gate electrode 108. It is injected into the floating gate electrode 106 with high efficiency. As a result, in the nonvolatile memory, the hot electrons previously injected into the floating gate electrode 106 are canceled by the newly injected hot holes, thereby erasing the written data.

The hot holes are formed with the floating gate electrode 106 with extremely high efficiency similarly to the above-mentioned hot electrons.
, A high-speed erase operation can be performed. (Seventh Embodiment) FIG. 12 is a schematic sectional view of a nonvolatile memory according to a seventh embodiment of the present invention.

The nonvolatile memory of FIG. 12 differs from the nonvolatile memory of FIG. 4 in the following points. On the surface of a p-type single crystal silicon substrate 51, a drain region 52 composed of an n ⁺ layer is formed.
a, 52b are formed at predetermined intervals. Drain region 52a, it is formed on the silicon substrate 51 between 52 b p ^-
Layer 59 is formed, p ^- n on the layer 59 ^- layer 53 and WSi
_Two source regions 54 are sequentially formed.

P ⁻ layer 59, n ⁻ layer 53 and source region 54
Floating gate electrodes 56a and 56b are formed on both side surfaces of the floating gate electrodes 56a and 56b, respectively, with a first gate insulating film 55 interposed therebetween. 58a and 58b are formed respectively. In the present embodiment, the common p ⁻ layer 5
9, the memory cells 50a and 50b are formed on both sides of the n ⁻ layer 53 and the source region 54 with the center as the center. The memory cell 50a includes a silicon substrate 51, a drain region 52
a, p ⁻ layer 59, n ⁻ layer 53, source region 54, first gate insulating film 55, floating gate electrode 56a, second gate insulating film 57, and control gate electrode 58a. The memory cell 50b includes a silicon substrate 51, a drain region 52b, a p ⁻ layer 59, an n ⁻ layer 53, a source region 54,
The first gate insulating film 55, the floating gate electrode 56b, the second
Of the gate insulating film 57 and the control gate electrode 58b.

In the read operation of the memory cell 50a,
A positive source potential Vs (for example, +3
V), a positive control gate potential VC is applied to the control gate electrode 58a.
G (for example, +3 V) is applied, and the drain region 52a is grounded. Then, when electrons are not accumulated in the floating gate electrode 56a, an n-type channel is formed in the p ⁻ layer 59 near the interface with the first gate insulating film 55, and the source region 54 and the drain region 52a Current flows between them. Conversely, when electrons are accumulated in the floating gate electrode 56a, no n-type channel is formed in the p ⁻ layer 59,
No current flows between the source region 54 and the drain region 52a.

As described above, in the nonvolatile memory of this embodiment, the presence or absence of electrons in the floating gate electrodes 56a and 56b can be determined by the same operation as that of the conventional nonvolatile memory. (Eighth Embodiment) FIG. 13 is a schematic sectional view of a nonvolatile memory according to an eighth embodiment of the present invention.

The nonvolatile memory of FIG. 13 differs from the nonvolatile memory of FIG. 5 in the following point. On a surface of a p-type single crystal silicon substrate 61, a drain region 62 made of an n ⁺ layer is formed.
a, 62b are formed at predetermined intervals. Drain region 62a, is formed on the silicon substrate 61 between 62b p ^-
A layer 69 is formed, and a concave n ⁻ layer 63 and a T-shaped source region 64 made of WSi ₂ are sequentially formed on the p ⁻ layer 69.

P ⁻ layer 69, n ⁻ layer 63 and source region 64
Floating gate electrodes 66a and 66b are formed on both sides of the floating gate electrodes 66a and 66b, respectively, with a first gate insulating film 65 interposed therebetween. 68a and 68b are formed respectively. In the present embodiment, the common p ⁻ layer 6
9, memory cells 60a and 60b are formed on both sides of the n ⁻ layer 63 and the source region 64, respectively. The memory cell 60a includes a silicon substrate 61, a drain region 62
a, p ⁻ layer 69, n ⁻ layer 63, source region 64, first gate insulating film 65, floating gate electrode 66a, second gate insulating film 67, and control gate electrode 68a. The memory cell 60b includes a silicon substrate 61, a drain region 62b, a p ⁻ layer 69, an n ⁻ layer 63, a source region 64,
The first gate insulating film 65, the floating gate electrode 66b, the second
Of the gate insulating film 67 and the control gate electrode 68b.

At the time of the read operation of the memory cell 60a,
A positive source potential Vs (for example, +3
V), a positive control gate potential VC is applied to the control gate electrode 68a.
G (for example, +3 V) is applied, and the drain region 62a is grounded. Then, when electrons are not accumulated in the floating gate electrode 66a, an n-type channel is formed in the p ⁻ layer 69 near the interface with the first gate insulating film 65, and the source region 64 and the drain region 62a Current flows between them. Conversely, when electrons are accumulated in the floating gate electrode 66a, no n-type channel is formed in the p ⁻ layer 69,
No current flows between the source region 64 and the drain region 62a.

As described above, in the nonvolatile memory of the present embodiment, the presence or absence of electrons in the floating gate electrodes 66a and 66b can be determined by the same operation as that of the conventional nonvolatile memory. (Ninth Embodiment) FIG. 14 is a schematic sectional view of a nonvolatile memory according to a ninth embodiment of the present invention.

The nonvolatile memory of FIG. 14 differs from the nonvolatile memory of FIG. 9 in the following points. On a surface of a p-type single crystal silicon substrate 81, a drain region 82 composed of an n ⁺ layer is formed.
a, 82b are formed at predetermined intervals. Drain region 82a, is formed on the silicon substrate 81 between 82b p ^-
A layer 89 is formed, an n ⁻ layer 83 having a concavely curved upper surface on the p ⁻ layer 89 and a W having a convexly curved lower surface.
Source regions 84 made of Si ₂ are sequentially formed.

The p ^- layer 89, the n ^- layer 83 and the source region 84
Floating gate electrodes 86a and 86b are formed on both side surfaces of the floating gate electrodes 86a and 86b with a first gate insulating film 85 interposed therebetween. 88a and 88b are formed respectively. In the present embodiment, the common p ⁻ layer 8
9, memory cells 80a and 80b are formed on both sides of the n ⁻ layer 83 and the source region 84 as a center. The memory cell 80a includes a silicon substrate 81, a p ⁻ layer 89, a drain region 82a, a p ⁻ layer 89, an n ⁻ layer 83, and a source region 8.
4, the first gate insulating film 85, the floating gate electrode 86a,
It is composed of a second gate insulating film 87 and a control gate electrode 88a. The memory cell 80b has a silicon substrate 8
1, p ⁻ layer 89, drain region 82b, n ⁻ layer 83, source region 84, first gate insulating film 85, floating gate electrode 86b, second gate insulating film 87, and control gate electrode 8
8b.

In the read operation of the memory cell 80a,
A positive source potential Vs (for example, +3
V), a positive control gate potential VC is applied to the control gate electrode 88a.
G (for example, +3 V) is applied, and the drain region 82a is grounded. Then, when electrons are not accumulated in the floating gate electrode 86a, an n-type channel is formed in the p ⁻ layer 89 near the interface with the first gate insulating film 85, and the source region 84 and the drain region 82a Current flows between them. Conversely, when electrons are accumulated in the floating gate electrode 86a, no n-type channel is formed in the p ⁻ layer 89,
No current flows between the source region 84 and the drain region 82a.

As described above, in the nonvolatile memory of this embodiment, the presence or absence of electrons in the floating gate electrodes 86a and 86b can be determined by the same operation as that of the conventional nonvolatile memory. In the above embodiment, the following changes may be made, and even in such a case, the same or more advantageous effects can be obtained.

(1) As a material of the floating gate electrode 36,
Silicon carbide (SiC) is used instead of SiN. (2) In the first, second, and sixth embodiments, the nonvolatile memory is formed in the n-type well regions 32, 42, 102 on the surfaces of the p-type single-crystal silicon substrates 31, 41, 101. A nonvolatile memory may be formed on an n-type single crystal silicon substrate.

(3) The conductivity type of each layer is reversed. (4) Source regions 33, 43, 54, 64, 84, and 10
WSi as material 3 _TwoInstead of silicon
Other materials that form the yoke barrier, eg, W, Ti,
Metals such as Pt and Au, metal nitrides such as TiN, and other metals
Using a multi-layer film such as silicide, W laminated on TiN, etc.
You.

(5) First gate insulating films 35, 45, 5
5, 65, 85, 105 and the second gate insulating film 37,
As the material of 47, 67, 87, and 107, another oxide film or nitride film such as SiON, SiOF, or SiN is used instead of SiO ₂ . (6) Control gate electrodes 38, 48, 58, 68, 88,
As the material 108, polycide such as tungsten silicide or titanium silicide is used instead of polysilicon.

(7) Although the source region is formed of a material that forms a Schottky barrier with respect to silicon, the drain region may be formed of a material that forms a Schottky barrier with respect to silicon. (8) Data is written into the floating gate electrode by injecting hot electrons, and data is erased by injecting hot holes.
This may be set in the reverse relationship.

In each of the above embodiments, the n-type well regions 32, 42, 102 and the n ⁻ layers 53, 63, 83
Correspond to the first layer, and the source regions 33, 43, 54, 6
4, 84 and 103 correspond to the second layer. The first gate insulating films 35, 45, 55, 65, 85, 105 correspond to the first insulating films, and the floating gate electrodes 36, 46, 5
6, 66, 86 and 106 correspond to the first electrode layer,
Gate insulating films 37, 47, 57, 67, 87, 107
Correspond to the second insulating film, and the control gate electrodes 38, 48,
58, 68, 88 and 108 correspond to the second electrode layer.

[0100]

According to the present invention, it is possible to provide a semiconductor device which operates as a non-volatile memory capable of high speed operation, low voltage and low power consumption while maintaining a long life and high holding operation. .

[Brief description of the drawings]

FIG. 1 is a MOSFET according to a first embodiment of the present invention.
FIG. 3 is a schematic sectional view of FIG.

FIG. 2 is an energy band diagram in the nonvolatile memory of FIG. 1;

FIG. 3 is a schematic sectional view of a nonvolatile memory according to a second embodiment of the present invention.

FIG. 4 is a schematic sectional view of a nonvolatile memory according to a third embodiment of the present invention.

FIG. 5 is a schematic sectional view of a nonvolatile memory according to a fourth embodiment of the present invention.

FIG. 6 is a schematic process sectional view showing a method for forming mainly a source region of the nonvolatile memory of FIG. 5;

FIG. 7 is a schematic cross-sectional view showing a step of a method for mainly forming a source region of the nonvolatile memory in FIG. 5;

FIG. 8 is a schematic process sectional view showing a method of forming mainly a source region of the nonvolatile memory of FIG. 5;

FIG. 9 is a schematic sectional view of a nonvolatile memory according to a fifth embodiment of the present invention.

10 is a schematic process cross-sectional view showing a method of mainly forming a source region of the nonvolatile memory of FIG. 9;

FIG. 11 is a schematic sectional view of a nonvolatile memory according to a sixth embodiment of the present invention.

FIG. 12 is a schematic sectional view of a nonvolatile memory according to a seventh embodiment of the present invention.

FIG. 13 is a schematic sectional view of a nonvolatile memory according to an eighth embodiment of the present invention.

FIG. 14 is a schematic sectional view of a nonvolatile memory according to a ninth embodiment of the present invention.

[Explanation of symbols]

31, 41, 51, 61, 81, 101 p-type single-crystal silicon substrate 32, 42, 102 n-type well region 33, 43, 54, 64, 84, 103 source region 34, 44, 52a, 52b, 62a, 62b , 82
a, 82b, 104 Drain regions 35, 45, 55, 65, 85, 105 First gate insulating films 36, 46, 56a, 56b, 68a, 68b, 88
a, 88b, 106 Floating gate electrodes 37, 47, 57, 67, 87, 107 Second gate insulating films 38, 48, 58a, 58b, 68a, 68b, 88
a, 88b, 108 Control gate electrode 53, 63, 83 n ^- layer 59, 69, 89 p ^- layer 204, 205, 206, 207, 208, 209 Interface

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (6)

[Claims] A first layer made of a semiconductor of one conductivity type; a second layer in Schottky contact with the first layer; and an interface formed between the first layer and the second layer. An electrode portion for applying an electric field to the interface for changing the thickness of the Schottky barrier, wherein the first electrode layer has a larger band gap than the first layer. Semiconductor device. A first insulating film formed on the second layer; a first electrode layer formed on the first insulating film; and a first electrode formed on the first insulating film. The second formed on the layer
2. The semiconductor device according to claim 1, wherein the semiconductor device comprises: an insulating film of (1); and a second electrode layer formed on the second insulating film. 3. 3. The semiconductor device according to claim 2, wherein the first electrode layer has a band gap smaller than a band gap of the first insulating film and a band gap of the second insulating film. 4. The method according to claim 1, wherein a distance from an interface between the first layer and the second layer to an end of the electrode portion on the first layer side is 50 nm or more. 13. The semiconductor device according to claim 1. 5. The electrode section includes the first layer and the second layer.
2. The semiconductor device according to claim 1, wherein the semiconductor device is arranged so as to form an angle larger than 0 degree with respect to the interface with the layer. 6. A method of operating a semiconductor device comprising: a first layer made of a semiconductor of one conductivity type; and a second layer that makes Schottky contact with the first layer, wherein the electrode unit is provided with: Data is written by applying a voltage to the interface between the first layer and the second layer and injecting hot carriers from the first layer into the electrode portion. And erasing data by injecting the conductive hot carriers into the electrode portion.