JPH09260517A - Non-volatile semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device where erasing voltage is low and storage holding capacity is high. SOLUTION: An SiO2 film 33 being a tunnel insulating film, a P-type polycrystalline Si film 34, an N-type polycrystalline Si film 35, an SiO2 film 36 being an insulating film for capacitive coupling and a tungsten polycide layer 41 being a gate electrode are sequentially stacked on an Si substrate 31. Electrons accumulated in the polycrystalline Si film 35 are not discharged to the Si substrate 31 through the SiO2 film 33 even if the SiO2 film 33 is such a thin one that tunneling can directly be executed owing to a potential barrier by means of P-N junction between the polycrystalline Si films 34 and 35 and even if voltage is not applied to the gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electrically writable and erasable nonvolatile semiconductor memory device called an EEPROM.

[0002]

2. Description of the Related Art FIG. 6 shows a floating gate type nonvolatile semiconductor memory device which is a first conventional example of an EEPROM.
In this first conventional example, as shown in FIGS.
An SiO ₂ film 12 for Fowler-Nordheim tunneling, a polycrystalline Si film 13 as a floating gate, an SiO ₂ film 14 for capacitive coupling, and a polycrystalline Si film as a control gate with a film thickness of about 5 nm are formed on an i substrate 11. 15 are sequentially laminated, and the Si substrates 11 on both sides of the polycrystalline Si films 13, 15 and the like are laminated.
A diffusion layer 16 as a source / drain is formed therein.

FIG. 6 (a) shows an initial state in which electrons are not accumulated in the polycrystalline Si film 13, and when a voltage V _CG is applied to the polycrystalline Si film 15 in this initial state, electrons are induced in the channel region. As a result, the drain current I _D flows as indicated by a in FIG. Therefore, the threshold voltage at this time is 1V.

On the other hand, when a positive high voltage is applied to the polycrystalline Si film 15 with respect to the Si substrate 11, as shown in FIG. 6B, the polycrystalline S film is transferred from the Si substrate 11 via the SiO ₂ film 12.
Electrons are injected into the i film 13, electrons are accumulated in the polycrystalline Si film 13, and a write state is set. FIG. 6D shows an energy band diagram, in which electrons are accumulated in the conduction band 17 of the polycrystalline Si film 13.

When a voltage V _CG is applied to the polycrystalline Si film 15 in this written state, no electrons are induced in the channel region and the drain current I _D does not flow at 1 V, as shown by b in FIG. 6 (c). A drain current I _D flows through. Therefore, the threshold voltage at this time is 5V.

From the writing state of FIG. 6B to FIG.
In order to perform the erasing for returning to the initial state, the negative high voltage is applied to the poly-Si film 15 to the poly-Si film 13 so that the poly-Si film 13 and the Si ₂ film 12 pass through Si.
Electrons are emitted to the substrate 11.

FIG. 7 shows a MONOS type non-volatile semiconductor memory device which is a second conventional example of an EEPROM. In this second conventional example, as shown in FIG.
SiO 2 for direct tunneling with a film thickness of about 2 nm on
₂ film 22, SiN film 23 and SiO ₂ film 24 for capacitive coupling
And a polycrystalline Si film 25 which is a gate electrode are sequentially laminated, and a diffusion layer 26 as a source / drain is formed in the Si substrate 21 on both sides of the polycrystalline Si film 25 and the like.

FIG. 7 (b) shows an energy band diagram, in which SiN is transferred from the Si substrate 21 through the SiO ₂ film 22.
The electrons injected into the film 23 are conducted in the SiN film 23, and the trap level 27 or SiN in the SiN film 23 is conducted.
It is trapped and accumulated in the interface state between the film 23 and the SiO ₂ film 24.

[0009]

However, in the first example of the floating gate type shown in FIG. 6, electrons are injected and emitted through the SiO ₂ film 12 for tunneling having a film thickness of about 5 nm. A high write / erase voltage of 10 V or higher is required, and low voltage driving cannot be performed. On the other hand, in the second conventional example of the MONOS type shown in FIG. 7, since the SiO ₂ film 22 for tunnel is as thin as about 2 nm, the write / erase voltage may be low. However, the SiO ₂ film 22
The memory retention capacity is low because the film thickness is as thin as about 2 nm.

In other words, it is difficult for the conventional EEPROM to make both the write / erase voltage low and the memory retention ability high, and conventionally, an EEPROM having a low write / erase voltage and a high memory retention ability is provided. Was difficult.

[0011]

A nonvolatile semiconductor memory device according to claim 1, wherein a tunnel insulating film, a first conductive type semiconductor film, a second conductive type semiconductor film, a capacitive coupling insulating film, and a gate. The electrodes are sequentially laminated on the semiconductor substrate.

According to a second aspect of the present invention, there is provided the non-volatile semiconductor memory device according to the first aspect, wherein the first conductivity type is P type and the second conductivity type is N type. There is.

A non-volatile semiconductor memory device according to a third aspect is the non-volatile semiconductor memory device according to the first aspect, wherein the first conductivity type is N type and the second conductivity type is P type. There is.

A non-volatile semiconductor memory device according to a fourth aspect is the non-volatile semiconductor memory device according to the first aspect, wherein the semiconductor film is a polycrystalline Si film.

A non-volatile semiconductor memory device according to a fifth aspect is the non-volatile semiconductor memory device according to the first aspect, characterized in that the semiconductor film is a SiN film.

In the nonvolatile semiconductor memory device according to the present invention, the potential barrier is formed by the PN junction between the first conductivity type semiconductor film on the tunnel insulating film side and the second conductivity type semiconductor film on the capacitive coupling insulating film side. There is.

Therefore, the second-conductivity-type carriers in the first and second-conductivity-type semiconductor films exist in the second-conductivity-type semiconductor film on the capacitive coupling insulating film side even when no voltage is applied to the gate electrode. Even if the tunnel insulating film is accumulated and is thin enough to allow direct tunneling, the tunnel insulating film does not pass through the tunnel insulating film and is not discharged to the semiconductor substrate.

[0018]

DETAILED DESCRIPTION OF THE INVENTION First to third embodiments of the present invention will be described below with reference to FIGS. In order to manufacture the nonvolatile semiconductor memory device of the first embodiment,
As shown in (a), the SiO ₂ film 32 for element isolation is formed on the Si substrate 31 by the LOCOS method, and as shown in FIG. 2 (b), direct tunneling is possible by rapid thermal oxidation under the following conditions. A different SiO ₂ film 33 is formed on the surface of the element active region. O ₂ : 2SLM Temperature: 800 ° C

Next, as shown in FIG. 2C, a polycrystalline Si film 3 having a thickness of about 100 nm is formed by thermal CVD under the following conditions.
4 is deposited. SiH ₄ : 100SCCM He: 400SCCM N ₂ : 200SCCM Pressure: 70Pa Temperature: 610 ° C

Next, as shown in FIG. 2D, the polycrystalline Si film 34 is made into a P type by ion implantation under the following conditions. Ion species: BF ₂ ⁺ energy: 30 keV Dose amount: 4.0 × 10 ¹² atoms / cm ²

Next, as shown in FIG. 2 (e), polycrystalline Si
The polycrystalline Si film 35 is formed by thermal CVD under the same conditions as the case of the film 34.
Is deposited, and as shown in FIG. 3A, the polycrystalline Si film 35 is made N-type by ion implantation under the following conditions. Ion species: As ⁺ energy: 20 keV Dose amount: 3.0 × 10 ¹² atoms / cm ²

Next, as shown in FIG. 3B, a SiO ₂ film 36 having a film thickness of about 6 nm is deposited by thermal CVD under the following conditions. SiH ₄ : 5SCCM O ₂ : 10SCCM Pressure: 1Pa Temperature: 850 ° C

Next, as shown in FIG. 3C, an N-type polycrystalline Si film 37 is deposited, and as shown in FIG. 3D, WS is deposited.
By depositing the i film 38, the polycrystalline Si film 37 and the WSi film 3 are deposited.
And 8 form a tungsten polycide layer 41. Then, as shown in FIG. 3E, the tungsten polycide layer 41, the SiO ₂ film 36, and the polycrystalline Si films 35 and 34 are processed into a gate electrode pattern by dry etching.

Next, as shown in FIG. 4A, the low concentration diffusion layer 42 for the LDD structure is formed into Si by ion implantation of impurities using the tungsten polycide layer 41 and the like and the SiO ₂ film 32 as a mask. It is formed on the substrate 31. Then, FIG.
As shown in FIG. 5, sidewall spacers made of SiO ₂ film 43 or the like are formed on the polycrystalline Si films 34 and 35 and the tungsten polycide layer 41.

Next, as shown in FIG. 4C, a high-concentration diffusion layer as a source / drain is formed by ion implantation of impurities using the tungsten polycide layer 41 and the like and the SiO ₂ films 32 and 43 as masks. 44 is formed on the Si substrate 31. Then, as shown in FIG. 4D, Si as an interlayer insulating film is formed.
The O ₂ film 45 is deposited.

Next, as shown in FIG. 5A, a contact hole 46 is formed in the SiO ₂ film 45 or the like, and then an Al film 47 is deposited as shown in FIG. 5B. And FIG.
As shown in (c), the Al film 47 is processed into a wiring pattern, and a surface protective film (not shown) or the like is further formed to complete the first embodiment.

FIG. 1A shows the first manufactured as described above.
1 shows an essential part of the embodiment, and in order to write data to the nonvolatile semiconductor memory device of the first embodiment, FIG.
As shown in (b), a positive voltage is applied to the tungsten polycide layer 41, which is the gate electrode, and a negative voltage is applied to the Si substrate 31. As a result, from the Si substrate 31 to SiO
_{2 The} electrons passing through the direct tunneling through the film 33 are P
Type polycrystalline Si film 34.

At this time, PN between the polycrystalline Si films 34 and 35
The junction is reverse-biased, electrons are excited from the valence band of the polycrystalline Si films 34 and 35 to the conduction band in the vicinity of the PN junction, and the excited electrons move in the N-type polycrystalline Si film 35. Then, it reaches and accumulates near the interface with the SiO ₂ film 36. On the other hand, the holes generated by the elimination of the electrons move in the P-type polycrystalline Si film 34 toward the Si substrate 31 and are combined with the electrons passing through the SiO ₂ film 33 from the Si substrate 31 to disappear. To do.

As shown in FIG. 1C, when the application of voltage to the tungsten polycide layer 41 and the Si substrate 31 is stopped, the injection of electrons from the Si substrate 31 to the polycrystalline Si film 34 is also stopped. Due to the potential barrier due to the PN junction between the polycrystalline Si films 34 and 35, the electrons accumulated in the N-type polycrystalline Si film 35 are retained without moving toward the P-type polycrystalline Si film 34. It

In order to erase the written data, as shown in FIG. 1D, a negative voltage is applied to the tungsten polycide layer 41 which is the gate electrode and a positive voltage is applied to the Si substrate 31. . As a result, the polycrystalline Si film 3
The PN junction between 4 and 35 is forward biased, and the electrons accumulated in the N-type polycrystalline Si film 35 pass through the PN junction and the SiO ₂ film 33 and are emitted to the Si substrate 31.

Next, the nonvolatile semiconductor memory device of the second embodiment will be described. In order to manufacture the nonvolatile semiconductor memory device of the second embodiment, the first embodiment described above is used except that the SiO ₂ film 36 having a film thickness of about 6 nm is formed by thermal oxidation under the following conditions. Substantially the same steps as those for manufacturing are performed. H _2: 2SLM O _2: 8SLM temperature: 850 ℃

Next, the nonvolatile semiconductor memory device of the third embodiment will be described. In order to manufacture the nonvolatile semiconductor memory device according to the third embodiment, the polycrystalline Si film 34,
35 is substantially the same as the case of manufacturing the above-described first embodiment, except that the SiN film having a thickness of about 100 nm is deposited by thermal CVD under the following conditions instead of depositing 35 by thermal CVD. Perform the process of. Even for SiN film, S
If the content of i is high and the band gap is narrow, it functions as a semiconductor.

SiH ₂ Cl ₂ : 50SCCM NH ₃ : 10SCCM N ₂ : 200SCCM Pressure: 70Pa Temperature: 760 ° C.

In any of the above-described first to third embodiments, the P-type semiconductor film on the SiO ₂ film 33 side and the SiO ₂ film 33 are formed.
Electrons are accumulated with the N-type semiconductor film on the side of the _2nd film 36, but an N-type semiconductor film is formed on the side of the SiO ₂ film 33 to form SiO 2.
_The holes may be accumulated by forming a P-type semiconductor film on the side of the _second film 36.

Further, in any of the above-described first to third embodiments, the reverse biased polycrystalline Si film 3 is used.
In the vicinity of the PN junction between 4 and 35, electrons excited from the valence band to the conduction band are accumulated, and holes generated by the elimination of the electrons are coupled with the electrons that have passed through the SiO ₂ film 33 from the Si substrate 31. However, the reverse bias is weakened to excite electrons from the valence band to the conduction band in the vicinity of the PN junction, and the electrons that have passed through the SiO ₂ film 33 from the Si substrate 31 may be accumulated. .

[0036]

In the nonvolatile semiconductor memory device according to the present invention, the second conductivity type carriers in the first and second conductivity type semiconductor films are on the side of the capacitive coupling insulating film even when the voltage is not applied to the gate electrode. Even if the tunnel insulating film is so thin that it is accumulated in the second conductive type semiconductor film and can be directly tunneled, it does not pass through the tunnel insulating film and is not emitted to the semiconductor substrate. High retention capacity.

[Brief description of drawings]

FIG. 1 shows a first embodiment of the present invention, in which (a) is a side sectional view of a main part, and (b), (c), and (d) are energies at the time of writing, holding and erasing data, respectively. It is a band figure.

FIG. 2 is a side sectional view sequentially showing a first step for manufacturing the first embodiment.

FIG. 3 is a side sectional view sequentially showing a step following FIG.

FIG. 4 is a side sectional view sequentially showing a step following FIG.

FIG. 5 is a side sectional view sequentially showing a step following FIG.

FIG. 6 shows a first conventional example of the present invention, in which (a) is a side sectional view in an initial state, (b) is a side sectional view in a written state, and (c) is a threshold value in an initial state and a written state. A graph showing voltage, (d) is an energy band diagram.

FIG. 7 shows a second conventional example of the present invention, in which (a) is a side sectional view and (b) is an energy band diagram.

[Explanation of symbols]

31 Si Substrate 33 SiO ₂ Film 34 Polycrystalline Si Film 35 Polycrystalline Si Film 36 SiO ₂ Film 41 Tungsten Polycide Layer

Claims (5)

[Claims] 1. A tunnel insulating film, a first conductive type semiconductor film, a second conductive type semiconductor film, a capacitive coupling insulating film, and a gate electrode are sequentially stacked on a semiconductor substrate. And a nonvolatile semiconductor memory device. 2. The first conductivity type is P-type, and the second conductivity type is P-type.
The nonvolatile semiconductor memory device according to claim 1, wherein the conductivity type is N type. 3. The first conductivity type is N-type, and the second conductivity type is N-type.
The nonvolatile semiconductor memory device according to claim 1, wherein the conductivity type is P type. 4. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor film is a polycrystalline Si film. 5. The nonvolatile semiconductor memory device according to claim 1, wherein the semiconductor film is a SiN film.