JPH11340802A - Variable delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit configuration and a component layout for realizing a variable delay circuit, that has a high delay time resolution and an satisfactory linearity. SOLUTION: Variable delay blocks 10, each consisting of pluralities of variable delay gates 1a-1x, are formed in an area partitioned off by power supply wires 2, a buffer 5 is provided to an output section of each variable delay block 10, so that an output wire capacity when viewed from the variable delay gate 1x of an output stage of each variable delay block 10 is the same as the output wiring capacity of the variable delay gates 1a, 1b and so on, placed at the other blocks 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable delay circuit for obtaining a desired timing of a clock signal or a data signal using a digital circuit, and more particularly to a variable delay circuit having improved resolution and linearity.

[0002]

2. Description of the Related Art A variable delay circuit is used for a circuit for adjusting data generation and sampling timing of a measuring instrument such as an LSI tester and a pulse pattern generator, and for adjusting a clock and a data skew on a printed circuit board. ing. The performance required of the variable delay circuit is high delay time resolution and linearity of the delay time. The linearity of the delay time is evaluated by a linearity error which is a difference between the delay time and the ideal delay straight line. Generally, the magnitude of the resolution and the magnitude of the linearity error are almost the same.

FIG. 11 (a) shows a configuration diagram of a conventional variable delay circuit, and FIG. 11 (b) is a detailed configuration diagram focusing on a 2-input NOR2 portion. FIG. 12 shows an equivalent circuit of the variable delay circuit shown in FIG. As shown in FIG. 11, the conventional variable delay circuit includes a delay signal input terminal (I1), a delay time control terminal (S1), an inverter I (NV1), a two-input NOR gate (2NOR1, NOR2), and a delay signal output terminal. (O1).

The delay time of the falling signal passing through this gate is adjusted by a delay time control signal. This delay time is based on the charge (C) stored in the gate capacitance of the next gate.
gs). The discharge is performed from the discharge paths FET1 and FET2 (see FIG. 11 (b)). The number of paths is changed to 1 (FET1 only) or 2 (FET1 and FET1) by changing the delay time control signal.
2) can be selected. Therefore, the delay time is adjusted by changing the number of discharge paths.

For example, when S1 (delay time adjustment signal) is set to L
(Low) (see FIG. 12A), the charge Cgd
Is discharged from the two paths of FET1 and FET2, so that the discharge time, that is, the delay time is reduced. on the other hand,
When S1 (delay time adjustment signal) is H (High) (FIG. 12)
(See (b).) Since the charge Cgs is discharged from only one path of the FET 1, the delay time is increased.

[0006] By connecting a plurality of the present delay gates configured as described above in series, a delay circuit having a large delay time variable width can be configured.

[0007]

The conventional variable delay circuit is configured as described above, and is configured to adjust the delay time by controlling the number of discharge paths of the gates constituting the delay stage. However, since the delay time of the variable delay gate greatly depends on the size of the output capacitance composed of the output wiring, the gate capacitance of the next stage, etc. Even if the delay time is made variable, the delay time resolution (=
The increase in the delay time of the variable delay gate) increases, and if the wiring capacitance varies in each stage, the increase in the delay time in each stage varies and the linearity error of the delay time resolution increases. is there.

Further, as in another conventional example shown in FIG. 13, when a power supply line for supplying power to each gate is arranged at a certain interval on a chip, when variable delay gates are connected in series, The power supply wiring and the variable delay gate may be laid out in the same place. In the conventional example in which the elements are laid out as shown in FIG. 13, the wiring capacitance is different between a delay gate laid out at the same place as the power supply wiring and a delay gate placed at a different place from the power supply wiring.
There is a problem that the amount of increase in the delay time varies and the linearity error of the delay time resolution increases.

The present invention has been made to solve the above problems, and a variable delay circuit having high delay time resolution and good linearity has been implemented by improving the circuit configuration and element layout. It is an object of the present invention to provide a variable delay circuit.

[0010]

According to a first aspect of the present invention, there is provided a variable delay circuit in which a plurality of variable delay gates are connected in series. The output stage of the variable delay gate having a large output capacitance due to the capacitance is provided with an output capacitance adjusting element for equalizing the output capacitance of each of the variable delay gates.

According to a second aspect of the present invention, in the variable delay circuit according to the first aspect,
A buffer is used as the output capacitance adjusting element.

According to a third aspect of the present invention, in the variable delay circuit according to the second aspect,
A dummy buffer for adjusting the fan-out of each variable delay gate is provided in parallel with the buffer.

According to a fourth aspect of the present invention, in the variable delay circuit according to the second aspect,
A two-input NOR gate for adjusting the fan-out of each variable delay gate is provided in parallel with the buffer.

According to a fifth aspect of the present invention, in the variable delay circuit according to the first aspect,
A dummy variable delay gate is used as the output capacitance adjusting element.

In a variable delay circuit according to a sixth aspect of the present invention, in the variable delay circuit comprising a plurality of variable delay gates connected in series, the input capacitance due to the wiring capacitance among the serially connected variable delay gates is provided. In the input stage of the variable delay gate having a large value, an input capacitance adjusting element for equalizing the input capacitance in each of the variable delay gates is provided.

The variable delay circuit according to a seventh aspect of the present invention is the variable delay circuit according to the sixth aspect,
A buffer is used as the input capacitance adjusting element.

The variable delay circuit according to claim 8 of the present invention is the variable delay circuit according to claim 7,
A dummy buffer for adjusting the fan-out of each variable delay gate is provided in parallel with the buffer.

According to a ninth aspect of the present invention, in the variable delay circuit according to the seventh aspect,
A two-input NOR gate for adjusting the fan-out of each variable delay gate is provided in parallel with the buffer.

A variable delay circuit according to a tenth aspect of the present invention is the variable delay circuit according to the sixth aspect, wherein a dummy variable delay gate is used as the input capacitance adjusting element.

The variable delay circuit according to an eleventh aspect of the present invention is the variable delay circuit comprising a plurality of variable delay gates connected in series. An output capacitance adjusting element for equalizing the output capacitance of each of the variable delay gates is provided at an output stage of the variable delay gate having a large size. Among the variable delay gates connected in series, the variable delay gate having a large input capacitance due to a wiring capacitance is provided. The input stage has an input capacitance adjusting element for equalizing the input capacitance of each of the variable delay gates.

According to a twelfth aspect of the present invention, in the variable delay circuit according to the eleventh aspect, a buffer is used as each of the input capacitance adjusting element and the output capacitance adjusting element. It is.

A variable delay circuit according to a thirteenth aspect of the present invention is the variable delay circuit according to the eleventh aspect, wherein an inverter is used as each of the input capacitance adjusting element and the output capacitance adjusting element. It is.

According to a fourteenth aspect of the present invention, in the variable delay circuit according to the eleventh aspect, a parallel circuit comprising an inverter and a two-input NAND gate is used as the output capacitance adjusting element. A two-input NAND gate is used as an input capacitance adjusting element.

A variable delay circuit according to a fifteenth aspect of the present invention is the variable delay circuit comprising a plurality of variable delay gates connected in series, wherein a buffer is provided before and after each variable delay gate, Input at the gate,
The output capacity is equalized.

A variable delay circuit according to a sixteenth aspect of the present invention is the variable delay circuit according to any one of the first, sixth, eleventh, and fifteenth aspects, wherein each of the variable delay gates comprises a plurality of variable delay gates. As one block, and each block is arranged in a region where it is difficult to add a wiring capacitance.

According to a seventeenth aspect of the present invention, in the variable delay circuit according to the sixteenth aspect, each of the variable delay gates constituting each of the variable delay blocks is arranged adjacent to each other. The output wiring lengths for connecting the variable delay gates are equalized.

In a variable delay circuit according to claim 18 of the present invention, in a variable delay circuit in which a plurality of variable delay gates are connected in series, variable delay gates of more stages than required are connected in series. However, among these serially connected variable delay gates, gates with a large delay time increase amount are disabled and used by disabling them.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a variable delay circuit according to the present invention will be described with reference to the drawings.

Embodiment 1 FIG. 1 is a diagram showing a board layout configuration of the variable delay circuit according to the first embodiment of the present invention. As described above, among a plurality of wires connecting the variable delay gates, a wire capacitance added to the output of the delay gate due to a reason that the wire length is longer than others and that the wire crosses the power supply wire. When the delay time increases, the delay time increase amount increases, and the linearity of the delay time deteriorates. Thus, in the first embodiment, a region where wiring capacitance such as a power supply wiring is difficult to be provided is provided, a variable delay gate is arranged in the region, and a substrate layout of the variable delay gate is devised so as not to intersect with the power supply wiring. The variable delay gate is divided into n blocks so that it can be easily arranged in the region, and a buffer is inserted immediately after the output part of the delay gate so that the wiring capacity added to the output is equal to the others. It is something to do. Note that the buffer used here refers to a circuit that separates the input stage and the output stage of the circuit in terms of wiring capacitance, but can basically output without changing the logic.

In the figure, 1 is a variable delay gate,
Its configuration is the same as that shown in the conventional example. The variable delay block 10 is configured by connecting a plurality of the variable delay gates in series. In addition, the variable delay block 10
Are connected in series in a zigzag manner, but one buffer 5 is provided between the variable delay blocks 10 in series. One end of the variable delay block 10 at the first stage becomes the delay time signal input 3 and the last stage One end of the variable delay block 10 is a delay time signal output 4.

Next, the function and effect will be described. A plurality of variable delay gates 1 are combined into one variable delay block 10
By arranging them so as not to intersect with the power supply wiring 2, it is possible to prevent variations in wiring capacitance due to wiring intersection. The wiring length of the wiring L2 connecting the variable delay gates 1 between the variable delay blocks 10 and the wiring L1 connecting the variable delay gates 1 in the variable delay blocks 10 are different. Buffer 5
Is provided, the time required for the variable delay gate 1x located at the output stage of each variable delay block 10 to charge the wiring L2 is shortened, and apparently, all the variable delay gates 1a to 1x are formed by wiring at equal intervals. This is the same as the connection of the variable delay gates, and the wiring capacitances added to the outputs of the respective variable delay gates 1a to 1x can be equalized by the variable delay gates existing in all the variable delay blocks 10. The linearity of the delay time resolution can be improved.

As described above, according to the first embodiment, a plurality of variable delay gates 1
forming a variable delay block 10 in units of a to 1x;
A buffer 5 is provided at an output section of each variable delay block 10,
Variable delay gate 1x at the output stage of each variable delay block 10
Since the output wiring capacitance as viewed from the outside is the same as the output wiring capacitance of the variable delay gates 1a, 1b,... Located at other places, variation in the wiring capacitance between the variable delay gates due to crossing of the wiring is prevented. Since the output wiring capacitance between the variable delay gates can be equalized, the linearity of the delay time resolution of the variable delay circuit can be prevented from lowering.

Embodiment 2 FIG. FIG. 2 is a diagram showing a configuration of a variable delay circuit according to a second embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
Reference numeral 1 denotes a dummy buffer provided in parallel with the buffer 5 inserted immediately after the variable delay block 10. The meaning of the dummy buffer used below is that the output stage is not connected anywhere or is connected to another circuit other than the present variable delay circuit. It indicates a buffer in a connected state that has no effect.

The operation and effect will be described below. In the configuration of the first embodiment, the wiring lengths of the variable delay gate 1x immediately before the buffer 5 and the variable delay gates 1a, 1b,. Variation can be reduced,
The variable delay gate 1x immediately before the buffer 5 and the other variable delay gates 1a, 1b,... Have different fan-out numbers, so that the amount of increase in the delay time is not constant. Specifically, the variable delay gate 1x immediately before the buffer 5 has one logic element (buffer 5) at the subsequent stage, and the variable delay gates 1a, 1b,. And 2NOR: see FIG. 11 (a)). Therefore, as shown in FIG. 2, in order to equalize the number of fan-outs between the respective delay gates (to 2), a dummy buffer 21 is connected in parallel with the buffer 5 so that each of the variable delay gates 1a and 1b is connected. ,... 1x can be equalized, and the linearity of the delay time resolution of the variable delay circuit can be further improved.

Embodiment 3 FIG. FIG. 3 is a diagram showing a configuration of a variable delay circuit according to a third embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
Reference numeral 1 denotes a dummy two-input NOR gate provided in place of the dummy buffer 21 shown in FIG. The meaning of the dummy two-input NOR gate used below means that the output stage is not connected anywhere or is connected to another circuit other than the present variable delay circuit, and if the variable delay circuit is used, the delay amount It shows a two-input NOR gate in a connected state that does not affect the variable operation at all.

Next, the function and effect will be described. In the second embodiment, in order to equalize the number of fan-outs in each of the variable delay gates 1a, 1b,.
1 is provided, but originally at the subsequent stage of the variable delay gate, FIG.
As shown in FIG. 1 (a), the next-stage variable delay gate is formed by connecting an inverter and a two-input NOR circuit. Therefore, if the number of fan-outs is made identical, the gate capacitance varies. Become. Therefore, by providing a dummy two-input NOR gate 31 in place of the dummy buffer 21, the gate capacitance of the variable delay gate 1x can be made smaller than that of the second embodiment by using the other variable delay gates 1a and 1a.
b, ... can be closer to the gate capacitance,
The linearity of the delay time resolution of the variable delay circuit can be further improved.

Embodiment 4 FIG. FIG. 4 is a diagram showing a configuration of a variable delay circuit according to a fourth embodiment of the present invention. In the figure, the same reference numerals as those in FIG.
Reference numeral 1 denotes a dummy variable delay gate provided in place of the buffer 5 shown in FIG. The meaning of the dummy variable delay gate used below is not used as a variable stage constituting the variable delay circuit, and has a structure in which a control signal is not input to the control terminal S1 constituting the variable delay gate in FIG. Assume a variable delay gate.

Next, the function and effect will be described. In the third embodiment, the output of the variable delay gate 1x is provided by providing the dummy variable delay gate 41 as compared with the case where the dummy buffer 5 and the dummy two-input NOR gate 31 are provided in parallel immediately after the variable delay gate 1x. It is possible to make the wiring section completely equal to the other variable delay gates 1a, 1b,..., Including its layout, and the linearity of the delay time resolution of the variable delay circuit is further improved as compared with the third embodiment. can do.

Embodiment 5 FIG. 5 is a diagram showing a configuration of a variable delay circuit according to a fifth embodiment of the present invention. In the drawing, the same reference numerals as those in FIG.
Reference numeral 1 denotes a buffer provided before the first stage variable delay gate 1a constituting each variable delay block 10, and when an input wiring capacitance added to the input of the variable delay gate increases, a buffer for a signal input to the variable delay gate is provided. Since the fall time increases, the amount of increase in the delay time increases, and the linearity of the delay time resolution of the variable delay circuit deteriorates. In order to make the (input) wiring capacitance added to the input equal to that of the other variable delay gates (1b,..., 1x), a buffer 51 similar to that of the first embodiment is inserted immediately after the input of the variable delay gate 1a. It is.

As a result, the wiring capacitance to be added to the input of each variable delay gate 1x is reduced by the other variable delay gates (1b,
, 1x), and the linearity of the delay time resolution of the variable delay circuit can be improved accordingly.

In the fifth embodiment, an example is shown in which the buffer 51 similar to the buffer 5 shown in FIG. 1 is used as an element to be inserted immediately before the variable delay gate 1a. The parallel circuit of the buffer 5 and the dummy buffer 21, the parallel circuit of the buffer 5 and the dummy two-input NOR gate 31 shown in the third embodiment, and the dummy variable delay gate 41 shown in the fourth embodiment are used. It may be.

Embodiment 6 FIG. FIG. 6 is a diagram showing a configuration of a variable delay circuit according to a sixth embodiment of the present invention. In the drawing, the same reference numerals as in FIG.
Reference numeral 1 denotes an inverter inserted immediately after the variable delay gate 1x located at the output stage of each variable delay block 10, and 62 denotes a variable delay block 1 to which the delay time signal 3 is input first.
The inverter is inserted immediately before the variable delay gate 1a located at the first input stage of the variable delay block 10 other than 0.

Next, the function and effect will be described. When the above-described configuration of the first embodiment and the configuration of the fifth embodiment are simultaneously performed, a total of two buffers are added to both ends of the wiring that increases the wiring capacitance added to the input of the variable delay gate. , But this is divided into two inverters 61,
By replacing with 62, the power consumption of one stage of the buffer can be reduced as compared with the case where Embodiment 1 and Embodiment 5 are simply combined. That is, in a circuit or the like generally using a compound semiconductor, the buffer is composed of two stages of inverters. However, by using the configuration shown in FIG. Power consumption for one stage of the buffer can be reduced.

Embodiment 7 FIG. FIG. 7 is a diagram showing a configuration of a variable delay circuit according to a seventh embodiment of the present invention. In the drawing, the same reference numerals as those in FIG. 1 denote the same or corresponding parts.
Reference numeral 1 denotes a parallel circuit which is inserted immediately after each variable delay gate 10 and is formed by connecting a buffer 71b and a two-input NOR gate 71a in parallel. Reference numeral 72 denotes a two-input NOR connected to the output stage of the parallel circuit 71. The gate.

Next, the function and effect will be described. In the seventh embodiment, the fourth embodiment aims to equalize the output wiring capacitance.
Fifth Embodiment for Equalizing Input Wiring Capacitance and Configuration
In the case of implementing in combination with the above configuration, the parallel circuit 71 and the two-input NOR gate 72 can constitute a one-stage variable delay gate corresponding to the dummy variable delay gate 41 shown in FIG. The configuration corresponding to the buffer 51 shown in FIG. 5 by the gate 72 makes it possible to provide one stage of the variable delay gate compared to the configuration obtained by simply combining the configuration of the fourth embodiment and the configuration of the fifth embodiment. Power consumption can be reduced.

Embodiment 8 FIG. FIG. 8 is a diagram showing a main configuration of a variable delay circuit according to an eighth embodiment of the present invention. In the figure, reference numeral 81 denotes a buffer inserted before and after all the variable delay gates 1. Next, the operation and effect will be described. FIG.
By arranging the buffers 81 before and after each variable delay gate 1 as shown in (1), the wiring capacitances between the variable delay gates 1 are all equal. Therefore, the wiring length of the variable delay gate 1 is included. Layout can be performed freely.

Embodiment 9 FIG. FIG. 9 is a diagram showing a main configuration of a variable delay circuit according to a ninth embodiment of the present invention. In the figure, reference numerals 1 denote variable delay gates laid out adjacent to each other. An output wiring 91 for connecting to the adjacent variable delay gate 1 is provided.

Next, the function and effect will be described. In the configurations shown in the first to eighth embodiments, by applying the above configuration, the layout of each gate and the layout between the gates are made identical, and the wiring capacitance added to the input / output of each variable delay gate 1 is made equal. It is possible to improve the resolution of the variable delay circuit, and to reduce the element variation of each variable delay gate 1, thereby improving the linearity of the delay time resolution of the variable delay circuit. Can be.

Embodiment 10 FIG. FIG. 10 is a diagram showing a variable delay circuit according to a tenth embodiment of the present invention. In the figure, reference numerals 1 denote variable delay gates laid out adjacent to each other, and the variable delay gate of the conventional example shown in FIG. In the variable delay circuits connected in series, the delay when the delay time selection signal of each variable delay gate 1 is changed by connecting the variable delay gates 1 of more stages than the required number of stages derived from the delay time variable width in series. The delay time selection signal of the variable delay gate whose time increase width is significantly larger than other delay gates is invalidated, and the delay time is adjusted by the delay time selection signal of only the gates having the same delay time increase width. is there.

That is, in FIG. 10A, when the required number of variable delay circuits is n, n + α (α is a natural number) stages of delay gate circuits are provided, and the state shown in FIG. In this case, the delay time selection signal of the variable delay gate 110 whose delay time increase is significantly larger than the other delay gates is invalidated, and only the remaining variable delay gates having the same delay time increase as shown in FIG. By configuring the variable delay circuit using the variable delay circuit, the linearity of the delay time resolution of the variable delay circuit can be improved.

In each of the above embodiments, the element for adjusting the input / output capacitance of the variable delay gate is arranged immediately before and after the variable delay gate. Other circuits and wirings that do not impair the effect may be interposed between the element and the variable delay gate.

[0052]

As described above, according to the variable delay circuit according to the first aspect of the present invention, in a variable delay circuit in which a plurality of variable delay gates are connected in series, the variable delay gate connected in series The output capacitance adjusting element for equalizing the output capacitance of each of the variable delay gates is provided immediately after the variable delay gate having a large output capacitance due to the wiring capacitance, so that the output capacitance of each variable delay gate can be kept constant. Thus, there is an effect that the linearity of the delay time resolution of the variable delay circuit can be improved.

According to the variable delay circuit of the second aspect of the present invention, in the variable delay circuit of the first aspect, a buffer is used as the output capacitance adjusting element. The output capacitance of the delay gate is adjusted by the buffer to be equal to other variable delay gates, the output capacitance of each variable delay gate can be kept constant, and the linearity of the delay time resolution of the variable delay circuit is improved. There is an effect that can be.

A variable delay circuit according to a third aspect of the present invention is the variable delay circuit according to the second aspect,
Since a dummy buffer for adjusting the fan-out of each variable delay gate is provided in parallel with the buffer, the number of fan-outs in each variable delay gate becomes equal, and the output capacitance of each variable delay gate is made more constant. There is an effect that can be.

The variable delay circuit according to a fourth aspect of the present invention is the variable delay circuit according to the second aspect,
Since a two-input NOR gate for adjusting the fan-out of each variable delay gate is provided in parallel with the buffer,
The gate capacitance of each variable delay gate can be made uniform, and the output capacitance of each variable delay gate can be made more constant than in the case of the third aspect.

According to the variable delay circuit of the fifth aspect of the present invention, in the variable delay circuit of the first aspect, a dummy variable delay gate is used as the output capacitance adjusting element. The output wiring section of the variable delay gate can be made completely equal to the other variable delay gates including the layout thereof, and the linearity of the delay time resolution of the variable delay circuit can be reduced as compared with the case of the fourth aspect. There is an effect that it can be further improved.

A variable delay circuit according to claim 6 of the present invention is a variable delay circuit comprising a plurality of variable delay gates connected in series. In the input stage of the variable delay gate having a large value, an input capacitance adjusting element for equalizing the input capacitance in each of the variable delay gates is provided, so that the input capacitance of each variable delay gate can be kept constant, and There is an effect that the linearity of the delay time resolution can be improved.

According to a seventh aspect of the present invention, in the variable delay circuit according to the sixth aspect, a buffer is used as the input capacitance adjusting element. The input capacitance of the gate is adjusted by the buffer to be equal to other variable delay gates, the input capacitance of each variable delay gate can be kept constant, and the linearity of the delay time resolution of the variable delay circuit can be improved. There is an effect that can be.

The variable delay circuit according to claim 8 of the present invention is the variable delay circuit according to claim 7,
A dummy buffer for adjusting the fan-out of each variable delay gate is provided in parallel with the buffer, so that the number of fan-outs in each variable delay gate becomes equal, and the input capacitance of each variable delay gate is made more constant. The variable delay circuit according to the ninth aspect of the present invention is the variable delay circuit according to the seventh aspect, wherein the variable delay circuit for adjusting the fan-out of each variable delay gate in parallel with the buffer. Since the two-input NOR gate is provided, the gate capacitance of each variable delay gate can be made uniform, and the input capacitance of each variable delay gate can be made more constant than in the case of the eighth aspect.

According to a tenth aspect of the present invention, in the variable delay circuit according to the sixth aspect, a dummy variable delay gate is used as the input capacitance adjusting element. Can be made completely equal to the other variable delay gates including the layout thereof, and the linearity of the delay time resolution of the variable delay circuit is further improved as compared with the case of the ninth aspect. There is an effect that can be.

Further, according to the variable delay gate of the present invention, in the variable delay circuit formed by connecting a plurality of variable delay gates in series, the variable delay gates connected in series among the series connected An output capacitance adjusting element for equalizing the output capacitance of each of the variable delay gates is provided at an output stage of the variable delay gate having a large output capacitance. Of the serially connected variable delay gates, a variable delay gate having a large input capacitance due to a wiring capacitance is provided. Since the input stage of the delay gate is provided with an input capacitance adjusting element for equalizing the input capacitance of each of the variable delay gates, the input capacitance and the output capacitance of each of the variable delay gates can be made constant. There is an effect that the linearity of the delay time resolution can be further improved.

According to a twelfth aspect of the present invention, in the variable delay circuit according to the eleventh aspect, a buffer is used as each of the input capacitance adjustment element and the output capacitance adjustment element. The input and output capacitances of the variable delay gates interleaved in the buffer are adjusted by the buffer to be equal to other variable delay gates, and the input capacitance and output capacitance of each variable delay gate can be constant. There is an effect that the linearity of the delay time resolution of the variable delay circuit can be improved.

According to a thirteenth aspect of the present invention, in the variable delay circuit according to the eleventh aspect, an inverter is used as each of the input capacitance adjusting element and the output capacitance adjusting element. As compared with the case of the twelfth aspect, it is possible to reduce the power consumption of one stage of the buffer for each variable delay gate.

According to a fourteenth aspect of the present invention, in the variable delay circuit according to the eleventh aspect, a parallel circuit comprising an inverter and a two-input NAND gate is used as the output capacitance adjusting element. Since a two-input NAND gate is used as the input capacitance adjusting element, a configuration corresponding to the dummy variable delay gate shown in claim 5 is realized by the parallel circuit and the two-input NOR gate. Thus, a buffer equivalent to the buffer shown in claim 7 can be realized, and the power consumption of one stage of the variable delay gate is different from the combination of the structure of claim 5 and the structure of claim 7. There is an effect that it can reduce.

A variable delay circuit according to a fifteenth aspect of the present invention is a variable delay circuit comprising a plurality of variable delay gates connected in series, wherein a buffer is provided before and after each variable delay gate. Since the input and output capacitances of the variable delay gates are equalized, the wiring capacitances between the variable delay gates are all equal, and the layout including the wiring length of the variable delay gate 1 can be freely performed. effective.

A variable delay circuit according to a sixteenth aspect of the present invention is the variable delay circuit according to any one of the first, sixth, eleventh, and fifteenth aspects, wherein each of the variable delay gates has a predetermined number. As one block, and each block is arranged in a region where it is difficult to add a wiring capacitance. Therefore, it is possible to prevent an increase in wiring capacitance due to wiring crossing without interfering with a layout such as a power supply wiring. This has the effect.

A variable delay circuit according to a seventeenth aspect of the present invention is the variable delay circuit according to the sixteenth aspect, wherein each of the variable delay gates constituting each of the variable delay blocks is arranged adjacent to each other. Since the output wiring length for connecting the variable delay gates is made equal, the layout of each gate and the layout between the gates can be made the same, and the wiring capacitance added to the input / output of each variable delay gate is made equal. The delay time resolution of the variable delay circuit can be improved, and the variation in the elements of each variable delay gate 1 can be reduced, and the linearity of the delay time resolution of the variable delay circuit can be improved. There is an effect that can be.

In a variable delay circuit according to claim 18 of the present invention, in a variable delay circuit having a plurality of variable delay gates connected in series, more variable delay gates are connected in series than necessary, and Of the variable delay gates connected in series, the gate having a large delay time increase amount is disabled and used by disabling, so that the linearity of the delay time resolution of the variable delay circuit can be improved. There is.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a variable delay circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a variable delay circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a variable delay circuit according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a variable delay circuit according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a variable delay circuit according to a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a variable delay circuit according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a variable delay circuit according to a seventh embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a variable delay circuit according to an eighth embodiment of the present invention.

FIG. 9 is a diagram showing a configuration of a variable delay circuit according to a ninth embodiment of the present invention.

FIG. 10A is a diagram showing a configuration of a variable delay circuit according to a tenth embodiment of the present invention, and FIG.
(b) and (c).

FIG. 11 is a diagram showing a configuration of a conventional variable delay circuit.

FIG. 12 is a diagram showing an equivalent circuit of the conventional variable delay circuit.

FIG. 13 is a diagram showing a configuration of another conventional variable delay circuit.

[Description of Signs] 1, 1a, 1b, 1x Variable delay gate, 2 power supply wiring, 3 delay time signal input, 4 delay time signal output,
5, 51, 81 buffers, 21 dummy buffers, 3
1 Dummy 2-input NOR gate, 41 Dummy variable delay gate, 61, 62 inverter, 71 parallel circuit, 7
22 2-input NOR gate, 91 output wiring, 110 Variable delay gate with large delay time increase, wiring connecting between L1 variable delay gates, wiring connecting between L2 variable delay blocks.

Claims (18)

[Claims] 1. A variable delay circuit comprising a plurality of variable delay gates connected in series, wherein each of said variable delay gates is connected to an output stage of a variable delay gate having a large output capacitance due to a wiring capacitance. A variable delay circuit comprising an output capacitance adjusting element for equalizing an output capacitance of a delay gate. 2. The variable delay circuit according to claim 1, wherein a buffer is used as the output capacitance adjusting element. 3. The variable delay circuit according to claim 2, wherein a dummy buffer for adjusting a fan-out of each variable delay gate is provided in parallel with said buffer. 4. The variable delay circuit according to claim 2, wherein a two-input NOR gate for adjusting a fan-out of each variable delay gate is provided in parallel with said buffer. 5. The variable delay circuit according to claim 1, wherein a dummy variable delay gate is used as the output capacitance adjusting element. 6. A variable delay circuit comprising a plurality of variable delay gates connected in series, wherein each of the variable delay gates connected in series is connected to an input stage of a variable delay gate having a large input capacitance due to a wiring capacitance. A variable delay circuit comprising an input capacitance adjusting element for equalizing an input capacitance of a delay gate. 7. The variable delay circuit according to claim 6, wherein a buffer is used as the input capacitance adjusting element. 8. The variable delay circuit according to claim 7, wherein a dummy buffer for adjusting a fan-out of each variable delay gate is provided in parallel with said buffer. 9. The variable delay circuit according to claim 7, wherein a two-input NOR gate for adjusting a fan-out of each variable delay gate is provided in parallel with said buffer. 10. The variable delay circuit according to claim 6, wherein a dummy variable delay gate is used as said input capacitance adjusting element. 11. A variable delay circuit comprising a plurality of variable delay gates connected in series, wherein each of said variable delay gates is connected to an output stage of a variable delay gate having a large output capacitance due to a wiring capacitance. An output capacitance adjusting element for equalizing the output capacitance of the delay gate is provided. Of the serially connected variable delay gates, an input capacitance of each of the variable delay gates is provided at an input stage of the variable delay gate having a large input capacitance due to a wiring capacitance. A variable delay circuit provided with an input capacitance adjusting element for equalizing. 12. The variable delay circuit according to claim 11, wherein a buffer is used as each of the input capacitance adjustment element and the output capacitance adjustment element. 13. The variable delay circuit according to claim 11, wherein an inverter is used as each of the input capacitance adjustment element and the output capacitance adjustment element. 14. The variable delay circuit according to claim 11, wherein said output capacitance adjusting element includes an inverter and a two-input NA.
A variable delay circuit using a parallel circuit composed of ND gates and using a two-input NAND gate as the input capacitance adjusting element. 15. A variable delay circuit comprising a plurality of variable delay gates connected in series, wherein a buffer is provided before and after each variable delay gate to equalize the input and output capacitance of each variable delay gate. Variable delay circuit. 16. The variable delay circuit according to claim 1, wherein a predetermined number of each of said variable delay gates is one block, and said variable delay gate is located in an area where wiring capacitance is difficult to add. A variable delay circuit, wherein each block is arranged. 17. The variable delay circuit according to claim 16, wherein each of the variable delay gates constituting each of the variable delay blocks is arranged adjacent to each other, and an output wiring length for connecting the variable delay gates is set. A variable delay circuit characterized by being equal. 18. A variable delay circuit comprising a plurality of variable delay gates connected in series, wherein variable delay gates of a greater number of stages than necessary are connected in series, and among these serially connected variable delay gates, A variable delay circuit characterized in that a gate having a large delay time increase amount is disabled and used by disabling the gate.