JPH11353873A - Input/output timing-controlled integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make performable a precise delay control operation without using many external input terminals in order to decide the delay amount in an input/ output timing-controlled integrated circuit. SOLUTION: A signal which is used to decide the delay amount is controlled by a memory element 3 and a memory element 9. The memory elements 3, 9 for timing control are constituted of a shift register, and they are controlled by an external terminal 1 and an external terminal 2. In addition, in order to eliminate an irregularity in a wiring delay between a delay element 5 and a delay element 10, the delay elements 5, 10 are built in an input/output cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit for controlling input / output signal timing.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional input / output timing control integrated circuit disclosed in, for example, Japanese Patent Application Laid-Open No. Hei 5-173666. In the figure, 21, 22, 30 are input buffer gates, 23 to 29, 31 to 37 are gates (buffers), 38 to 42 are selection circuits (multiplexers), 43 is a delay circuit, 44 is a clock distribution circuit, CK
L, S0, S1, SA to SC are external input terminals, RF1 to
RF3 is a register.

A conventional input / output timing control integrated circuit is constructed as described above. For example, a gate 23 and a gate 2
4, 25 or a circuit consisting of gates 26-29,
Whether or not to pass is controlled by selection circuits 39-41.
These selection circuits 39 to 41 are connected to external terminals SA to
Controlled by a signal from the SC. As a result, by controlling the selection circuits 39 to 41, the number of gate stages 0, 1 to 7 can be selected as the delay amount of the signal passing through the delay circuit 43.

[0004]

In the conventional input / output timing control integrated circuit as described above, since all the signals for determining the delay amount are controlled from the external input terminals SA to SC, a highly accurate and optional When the delay circuit 43 with many components is built in, many external input terminals SA to
There is a problem that it is necessary to occupy the SC. Also,
Depending on where the delay elements 23 to 29 are arranged in the integrated circuit, the wiring delay between the elements differs, and there is a problem that accurate delay control cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has an input / output timing control capable of performing accurate delay control without using a large number of external input terminals for determining a delay amount. It is an object to provide an integrated circuit.

[0006]

An input / output timing control integrated circuit according to a first aspect of the present invention connects a storage element to an input / output signal delay circuit and operates the storage element by a signal via an external terminal. Thus, the delay circuit is controlled.

In the input / output timing control integrated circuit according to the second invention, a storage element is connected to a delay circuit for input / output signals, and the storage element is operated by a signal via an external terminal to control the delay circuit. In addition, a direction control buffer for temporarily storing a signal passing through the delay circuit in accordance with the direction function of the bidirectional terminal is inserted between the delay circuit and the input / output shared bidirectional terminal.

According to a third aspect of the present invention, there is provided an input / output timing control integrated circuit according to the first or second aspect.
A delay logic circuit is built in an input / output cell.

According to a fourth aspect of the present invention, there is provided an input / output timing control integrated circuit according to the first or second aspect.
The delay logic circuit is configured as a hard macro in an internal logic configuration area of the integrated circuit.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 FIG. 1 is a circuit diagram showing an embodiment of the first invention of the present invention. In the figure, 1 is an input terminal for serially inputting timing control data, 2 is a clock terminal for shifting the timing control data to successive storage elements 3 and 9, 3.
Is a timing control storage element having a terminal D connected to the input terminal 1, a terminal T connected to the clock terminal 2, and a terminal Q serving as an output terminal, and 4 is an input terminal required for normal functions of the integrated circuit. .

Reference numeral 5 denotes a delay element connected to the input terminal 4;
Is a multiplexer connected to the terminal Q, the input terminal 4 and the delay element 5 of the storage element 3 and having a signal 6a. A delay circuit is formed by a circuit including the delay element 5 and the multiplexer 6, and the delay circuit and the storage element 3 An input terminal delay logic circuit 7 is configured. 8 is a normal logic circuit required for normal functions of the integrated circuit, 8a is its output signal, 9
Is a timing control storage element having a terminal Q connected to the storage element 3, a terminal D connected to the clock terminal 2, and a terminal Q serving as an output terminal.

Reference numeral 10 denotes a delay element connected to the normal logic circuit 8, 11 denotes a terminal Q of the storage element 9, the delay element 10, an output terminal 12 necessary for normal functions of the normal logic circuit 8 and the integrated circuit.
A delay circuit is formed by a circuit including the delay element 10 and the multiplexer 11, and a delay logic circuit 13 for the output terminal is formed by the delay circuit and the storage element 9.

Next, the operation of this embodiment will be described.
The signal input to the input terminal 4 is input to the multiplexer 6 directly and via the delay element 5. Here, the multiplexer 6 is controlled by the output of the terminal Q of the storage element 3, and one of the inputs to the multiplexer 6 is output as a signal 6a. The signal 6a is normally input to the logic circuit 8, and the output signal 8a is selected by the multiplexer 11 and output from the output terminal 12 as described above.

The amount of delay of the input signal from input terminal 4 is determined by the logical value of storage element 3, and the amount of delay to output terminal 12 is determined by the logical value of storage element 9. The setting of the logical values for the storage elements 3 and 9 is performed by controlling the input terminal 1 and the clock terminal 2. here,
Control when setting the logical values “1” and “0” to the storage elements 3 and 9 will be described.

First, when a logical value “0” is set to the input terminal 1 and then a clock is applied to the clock terminal 2, the logical value “0” is set to the storage element 3 and the value is still set to the storage element 9. It is in a state where it is not performed. Next, when a logical value “1” is set to the input terminal 1 and then a clock is applied to the clock terminal 2, the logical value “1” is set to the storage element 3,
The logic state "0" is set in the storage element 9. Thus, the multiplexers 6 and 11 are controlled by the outputs of the terminals Q of the storage elements 3 and 9.

In the figure, the input terminal 4 and the output terminal 12
Although each of them is shown one by one, even in a plurality of integrated circuits, by connecting the delay logic circuits 7 and 13 in the same manner, only the input terminal 1 and the clock terminal 2 as external terminals for timing control are provided. Can be controlled by

Thus, the external terminals of the integrated circuit are
By using only the present invention, it is possible to absorb the variation in the delay at the time of manufacturing the integrated circuit and the variation in the delay on the substrate on which the manufactured integrated circuit is incorporated after the system is constructed. Also, DRA
It can be connected to a sinter interface with a component requiring strict control of timing such as M without an external timing adjustment element.

Embodiment 2 FIG. FIG. 2 is a delay logic circuit for input terminals showing another embodiment of the first invention of the present invention. In FIG. 1, the delay element 5
, Or a circuit including one delay element 5 is selected. In FIG. 2, a plurality of delays can be selected. That is, a plurality of delay elements 5 are connected in series, this connection point is connected to a multiplexer 6, a terminal Q at a preceding stage and a terminal D at a subsequent stage of the plurality of storage elements 3 are connected, and a terminal Q at each stage is connected. The multiplexer 6 is controlled by the output of. At this time, for the n inputs of the multiplexer 6, the storage element 3
Requires log ₂ n (rounded up after the decimal point).

Embodiment 3 FIG. 3 is a delay logic circuit diagram for a bidirectional terminal showing an embodiment of the second invention of the present invention. In FIG. 1, the input terminal 4 and the output terminal 12 are provided, but in FIG. 3, the input terminal 4 and the output terminal 12 can be used for a bidirectional terminal. That is, a bidirectional terminal 15 for input / output is provided in place of the input terminal 4 in FIG.
A direction control buffer 17 controlled by a bidirectional control signal 16 is connected between the multiplexer 5 and the multiplexer 11 to form a delay logic circuit 18 for a bidirectional terminal.

The direction control buffer 17 is controlled by a bidirectional control signal 16, and stops output when the bidirectional terminal 15 has the function of an input terminal, and outputs when the bidirectional terminal 15 has the function of an output terminal. Emits.

Embodiment 4 FIG. 7 shows an embodiment of the third invention of the present invention, in which a delay logic circuit 7 for an input terminal, a delay logic circuit 13 for an output terminal, and a delay logic circuit 18 for a bidirectional terminal are shown.
Are respectively incorporated in input / output cells (not shown). As a result, the wiring delay for the signal whose delay is to be controlled is fixed, and accurate delay control can be performed.

Embodiment 5 FIG. 9 shows another embodiment of the third invention of the present invention, in which the input terminal delay logic circuit 7 shown in FIG.
In the output terminal delay logic circuit 13 and the bidirectional terminal delay logic circuit 18, a logic circuit excluding the storage elements 3, 9 or one of them is incorporated in an input / output cell. Thus, similarly to the fourth embodiment, the wiring delay for the signal whose delay is to be controlled is fixed, and accurate delay control can be performed.

Embodiment 6 FIG. This shows an embodiment of the fourth invention of the present invention, wherein the logic circuit incorporated in the input / output cell in the fifth embodiment is made into a hard macro. Generally, a semiconductor integrated circuit is developed by combining logic primitives (libraries) provided by a semiconductor manufacturer. The logic primitive is designed in the physical layer in advance by a semiconductor maker, and device characteristics (such as signal transmission speed) inside the logic primitive are fixed.

The hard macro is obtained by designing a larger logical block in the physical layer in advance and fixing device characteristics inside the logical block. In this way, as in the second and third embodiments, the wiring delay is fixed in the path of the signal to be controlled, and accurate delay control is possible.

[0025]

As described above, according to the first aspect of the present invention, a storage element is connected to a delay circuit for input / output signals, and the storage element is operated by a signal via an external terminal to control the delay circuit. According to the second invention, a storage element is connected to a delay circuit for input / output signals, and the storage element is operated by a signal via an external terminal to control the delay circuit. A direction control buffer for temporarily storing a signal passing through a delay circuit in accordance with the direction function of the bidirectional terminal is inserted between the shared bidirectional terminal.

Thus, by using two or less external terminals of the integrated circuit, variations in delay during manufacture of the integrated circuit,
Variations in delay on a substrate incorporating a manufactured integrated circuit can be absorbed after system construction. Also, D
It can also be connected to a sine interface with a component requiring strict control of timing, such as a RAM, without using an external timing adjustment element.

In the third invention, the delay logic circuit is built in the input / output cell, and in the fourth invention, the delay logic circuit is configured as a hard macro in the internal logic configuration area of the integrated circuit. , The wiring delay is fixed, and accurate delay control can be performed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing Embodiment 1 of the present invention.

FIG. 2 is a circuit diagram showing Embodiment 2 of the present invention.

FIG. 3 is a circuit diagram showing Embodiment 3 of the present invention.

FIG. 4 is a circuit diagram showing a conventional input / output timing control integrated circuit.

[Explanation of symbols]

1 external terminal (input terminal), 2 external terminal (clock terminal), 3 timing control storage element, 4 input terminal,
Reference Signs List 5 delay element, 6 multiplexer, 7 delay logic circuit for input terminal, 9 storage element for timing control, 10 delay element, 11 multiplexer, 12 output terminal, 13
Output terminal delay logic circuit, 15 bidirectional terminals, 17 direction control buffer.

Claims (4)

[Claims] 1. A delay circuit for selectively controlling a delay of an input / output signal of a semiconductor integrated circuit, and a delay circuit connected to the delay circuit and operated by a signal passing through an external terminal of the integrated circuit to control the delay circuit. An input / output timing control integrated circuit comprising a delay logic circuit having a storage element. 2. A delay circuit for selectively controlling a delay of an input / output signal of a semiconductor integrated circuit having a bidirectional terminal commonly used for input / output, and a delay circuit connected to the delay circuit and passing through an external terminal of the integrated circuit. A storage element that operates to control the delay circuit, a direction control buffer inserted between the delay circuit and the bidirectional terminal and temporarily storing a signal passing through the delay circuit corresponding to a direction function of the bidirectional terminal; I / O timing control integrated circuit comprising a delay logic circuit having: 3. The input / output timing control integrated circuit according to claim 1, wherein the delay logic circuit is built in an input / output cell of the semiconductor integrated circuit. 4. The input / output timing control integrated circuit according to claim 1, wherein the delay logic circuit is configured as a hard macro in an internal configuration area of the semiconductor integrated circuit.