JPH11340623A - Manufacture of flexible printed board - Google Patents

Manufacture of flexible printed board

Info

Publication number
JPH11340623A
JPH11340623A JP14484198A JP14484198A JPH11340623A JP H11340623 A JPH11340623 A JP H11340623A JP 14484198 A JP14484198 A JP 14484198A JP 14484198 A JP14484198 A JP 14484198A JP H11340623 A JPH11340623 A JP H11340623A
Authority
JP
Japan
Prior art keywords
laminate
film
plating
metal layer
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP14484198A
Other languages
Japanese (ja)
Inventor
Hideki Ando
秀樹 安藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP14484198A priority Critical patent/JPH11340623A/en
Publication of JPH11340623A publication Critical patent/JPH11340623A/en
Withdrawn legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a flexible printed board by which a plating film does not overlap a metal film on the surface of a laminated board, front-rear conducting holes can be plated selectively, and plating liquid does not infiltrate into between the surface of the laminated board and a mask, by masking the surface of the laminated board having front-rear conducting holes with a film except on the front-rear conducting holes. SOLUTION: On a laminated board 3, having metal layers 1 on the both front and rear planes of an insulating layer, a front-rear conducting hole 4 that penetrates the metal layer 1 is formed, and a plating film is formed on the inner plane of the front-rear conducting hole 4 in a method for manufacturing a flexible printed board. The method includes a process of adhering a film on the surface of the laminated board 3 except on the front-rear conducting hole 4, a process of forming a plating film 6 by plating the front-rear conducting hole 4 of the laminated board 3, and a process of peeling the film from the surface of the laminated board 3 after plating and polishing the surface of the laminated board 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、電気・電子機器に
使用されるフレキシブルプリント配線板(以下FPCと
略す)の製造方法に関し、詳しくはメッキを施した表裏
導通穴を有するFPCの製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a flexible printed wiring board (hereinafter abbreviated as FPC) used for electric and electronic equipment, and more particularly to a method of manufacturing an FPC having plated front and back conduction holes. .

【0002】[0002]

【従来の技術】FPCは、携帯端末や携帯電話、小型ビ
デオ機器、小型電子カメラ等の電子機器や、コンピュー
タの記憶媒体であるハードディスクやCD−ROM等に
広く用いられている。これらの電子機器の小型・軽量化
や記憶媒体の機能性・信頼性向上等のため、より高性能
のFPCが求められている。
2. Description of the Related Art FPCs are widely used in electronic devices such as portable terminals, cellular phones, small video devices, and small electronic cameras, as well as hard disks and CD-ROMs as storage media for computers. In order to reduce the size and weight of these electronic devices and to improve the functionality and reliability of storage media, higher performance FPCs are required.

【0003】FPCとして、その表面から裏面への導通
用の穴を有するものが用いられている。従来の該FPC
の製造方法を、図4a〜図4dを用いて説明する。すな
わち、絶縁層2の表裏両面に金属層1を有する積層板3
に表裏導通穴4を開け、積層板3に表裏導通のためのメ
ッキを施しメッキ皮膜6、11を形成して、メッキを施
した表裏導通穴を有する積層板3を得る。次いで、得ら
れた積層板3の表裏面にエッチング法等で回路8を形成
してFPC9を得る。
An FPC having a hole for conduction from the front surface to the back surface is used. Conventional FPC
Will be described with reference to FIGS. 4A to 4D. That is, the laminated plate 3 having the metal layer 1 on both front and back surfaces of the insulating layer 2
Then, a front and back conduction hole 4 is opened, and plating for front and back conduction is performed on the laminate 3 to form plating films 6 and 11, thereby obtaining a laminated plate 3 having plated front and back conduction holes. Next, a circuit 8 is formed on the front and back surfaces of the obtained laminated board 3 by an etching method or the like to obtain an FPC 9.

【0004】この従来の方法では以下の問題があった。The conventional method has the following problems.

【0005】(1)得られた積層板3の表面に形成され
る金属層が、出発材料の積層板3の金属層1とメッキ皮
膜11の重層したものになり、各々の加工公差が加わっ
て表面粗さが大きくなるため、得られた積層板3の表面
に付着される回路形成用レジストフィルムの密着性が悪
くなり、回路形成歩留まりが低下する。
[0005] (1) The metal layer formed on the surface of the obtained laminated plate 3 is formed by laminating the metal layer 1 of the laminated plate 3 of the starting material and the plating film 11, and each processing tolerance is added. Since the surface roughness is increased, the adhesiveness of the circuit forming resist film adhered to the surface of the obtained laminate 3 is deteriorated, and the circuit forming yield is reduced.

【0006】(2)得られた積層板3の表面に形成され
る金属層が、出発材料の積層板3の金属層1とメッキ皮
膜11の重層したものになるので、厚くなり、また各々
の加工公差が加わって厚みのばらつきが大きくなるた
め、高精細回路形成が難しい。
(2) Since the metal layer formed on the surface of the obtained laminate 3 is formed by superposing the metal layer 1 of the laminate 3 of the starting material and the plating film 11, the metal layer becomes thicker. Since the variation in thickness increases due to the processing tolerance, it is difficult to form a high-definition circuit.

【0007】(3)得られた積層板3の表面に形成され
る金属層が、出発材料の積層板3の金属層1とメッキ皮
膜11の重層したものになるので、厚くなるため、得ら
れたFPC9は屈曲性能が劣る。
(3) Since the metal layer formed on the surface of the obtained laminate 3 is formed by superposing the metal layer 1 of the laminate 3 of the starting material and the plating film 11, the thickness is increased. FPC9 has poor bending performance.

【0008】また、従来の他のFPCの製造方法を、図
5a〜図5dを用いて説明する。すなわち、上記の従来
の製造方法の積層板3に表裏導通穴4を開けたものの表
面に、部分的にフィルム5を貼着けてマスクし、次いで
積層板3に表裏導通のためのメッキを施してメッキ皮膜
6、11を形成し、その後マスク用のフィルムを剥離す
る。次いで、積層板3の表面のメッキ皮膜が形成された
部分と形成されていない部分の段差12を研磨で滑らか
にし、メッキが施された表裏導通穴を有する積層板3を
得る。次いで、得られた積層板3の表裏面にエッチング
法等で回路8を形成してFPC9を得る。
[0008] Another conventional method for manufacturing an FPC will be described with reference to FIGS. 5A to 5D. That is, a film 5 is partially adhered and masked on the surface of the laminate 3 of the above-described conventional manufacturing method in which the front and back conduction holes 4 are opened, and then the laminate 3 is plated for front and back conduction. The plating films 6 and 11 are formed, and then the mask film is peeled off. Next, the step 12 on the surface of the laminate 3 where the plating film is formed and the portion where the plating film is not formed is polished to obtain a laminate 3 having plated front and back conduction holes. Next, a circuit 8 is formed on the front and back surfaces of the obtained laminated board 3 by an etching method or the like to obtain an FPC 9.

【0009】この方法では、得られた積層板3は表面の
金属層が出発材料の積層板3の金属層1のみからなる薄
い部分を有するものの、表面の金属層が出発材料の積層
板3の金属層1とメッキ皮膜11の重層したものになる
厚い部分も有しており、厚さが部分的に異なるため、得
られた積層板3の表面に付着される回路形成用レジスト
フィルムの密着性が悪く回路形成歩留まりが低下する問
題があった。
According to this method, although the obtained laminate 3 has a thin portion in which the surface metal layer is composed of only the metal layer 1 of the laminate 3 of the starting material, the laminate 3 of the laminate having the surface metal of the starting material has a thin portion. It also has a thick portion where the metal layer 1 and the plating film 11 are layered, and since the thickness is partially different, the adhesion of the circuit-forming resist film adhered to the surface of the obtained laminate 3 is obtained. However, there is a problem that the circuit formation yield is deteriorated.

【0010】一般のプリント配線板の場合、表裏導通穴
を有するプリント配線板の製造方法として、表裏導通穴
にメッキを施す際に、出発材料の積層板の表面にもメッ
キ皮膜が形成されて、積層板の表面の金属層が出発材料
の積層板の金属層とメッキ皮膜の重層したものとなる問
題を解決するために、表裏導通穴にメッキを施す際に鋏
み治具を用いて積層板の表裏導通穴以外の表面をマスク
し、表裏導通穴にメッキを施す方法が提案されている
(特開平9−214134号公報)。
[0010] In the case of a general printed wiring board, as a method of manufacturing a printed wiring board having front and back conduction holes, when plating the front and back conduction holes, a plating film is also formed on the surface of the laminate of the starting material, In order to solve the problem that the metal layer on the surface of the laminate is a layer of the metal layer of the starting laminate and the plating film, use a scissors jig when plating the front and back conduction holes. A method has been proposed in which a surface other than the front and back conduction holes is masked and the front and back conduction holes are plated (JP-A-9-214134).

【0011】しかし、この公報に開示されている方法を
FPCの製造方法に適用した場合、鋏み治具とFPC用
の出発材料の積層板の密着性が低く、このため積層板に
メッキを施す際に、鋏み治具と積層板の表面との間にメ
ッキ液がしみ込んで薄いメッキ層ができる。このためメ
ッキ後に鋏み治具を積層板から取り外すことが困難とな
り、しかも取り外しの際に鋏み治具と積層板の間のメッ
キ層がはがれて、バリ(凸部)またはカエリ(凹部)が
発生し、積層板の表面が粗くなるという欠点がある。
However, when the method disclosed in this publication is applied to a method of manufacturing an FPC, the adhesion between the scissors jig and the laminate of the starting material for the FPC is low, and therefore, when plating is performed on the laminate. Then, the plating solution is soaked between the scissors jig and the surface of the laminate to form a thin plating layer. For this reason, it becomes difficult to remove the scissors jig from the laminate after plating, and at the time of removal, the plating layer between the scissors jig and the laminate is peeled off, and burrs (convex portions) or burrs (concave portions) are generated. There is a disadvantage that the surface of the plate becomes rough.

【0012】[0012]

【発明が解決しようとする課題】本発明は、上記の問題
を解決するためになされたものであり、その目的とする
ところは、表裏導通穴を有するFPCの製造方法であっ
て、表裏導通穴を開けた積層板の表裏導通穴以外の表面
にフィルムを貼着けてマスクすることで、積層板の表面
の金属層にメッキ皮膜を重層せず、表裏導通穴に選択的
にメッキを施すことができ、また、積層板の表面とマス
クの間にメッキ液がしみ込むことのないFPCの製造方
法を提供することにある。
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing an FPC having front and back conduction holes. By attaching a film to the surface of the laminated board other than the front and back conduction holes and masking it, it is possible to selectively plating the front and back conduction holes without overlaying the plating film on the metal layer on the surface of the laminate. It is another object of the present invention to provide a method of manufacturing an FPC that can prevent a plating solution from permeating between a surface of a laminate and a mask.

【0013】[0013]

【課題を解決するための手段】本発明の請求項1に係る
FPCの製造方法は、絶縁層の表裏両面に金属層を有す
る積層板に、金属層を貫通する表裏導通穴を形成し、こ
の表裏導通穴の内面にメッキ皮膜を形成するフレキシブ
ルプリント配線板の製造方法において、表裏導通穴以外
の積層板の表面にフィルムを貼着ける工程、積層板の表
裏導通穴にメッキを施してメッキ皮膜を形成する工程、
および、そのメッキ後、フィルムを積層板の表面から剥
離し積層板の表面を研磨する工程を包含しており、その
ことにより上記目的が達成される。
According to a first aspect of the present invention, there is provided a method of manufacturing an FPC, comprising forming a front and back conduction hole penetrating a metal layer in a laminate having a metal layer on both sides of an insulating layer. In the method of manufacturing a flexible printed wiring board in which a plating film is formed on the inner surface of the front and back conduction holes, a step of attaching a film to the surface of the laminate other than the front and back conduction holes, plating the front and back conduction holes of the laminate to form a plating film. Forming,
Further, after the plating, the method includes a step of peeling the film from the surface of the laminate and polishing the surface of the laminate, thereby achieving the above object.

【0014】一実施態様では、フィルムを積層板に貼着
ける前に、積層板に無電解メッキを施す工程を包含す
る。
One embodiment includes the step of applying electroless plating to the laminate before attaching the film to the laminate.

【0015】一実施態様では、積層板の表面が、回路形
成用レジストフィルムが確実に密着するよう平滑であ
る。
In one embodiment, the surface of the laminate is smooth to ensure that the circuit-forming resist film adheres tightly.

【0016】一実施態様では、積層板の表面にメッキ皮
膜が付着していない。
In one embodiment, no plating film adheres to the surface of the laminate.

【0017】本発明の作用は次の通りである。The operation of the present invention is as follows.

【0018】本発明によると、表裏導通穴を開けた積層
板の表裏導通穴以外の表面にフィルムを貼着けてマスク
した状態でメッキを施す。フィルムと積層板の表面は密
着性が良く、フィルムと積層板表面の間に隙間を生じて
メッキ液がしみ込むようなことがない。また、積層板の
表裏導通穴に選択的にメッキ皮膜を形成することがで
き、積層板の表面の金属層にメッキ皮膜を重層すること
がない。
According to the present invention, plating is performed in a state where a film is stuck and masked on the surface other than the front and back conduction holes of the laminated plate having the front and back conduction holes. The film and the surface of the laminate have good adhesion, and there is no gap between the film and the surface of the laminate, so that the plating solution does not soak. Further, a plating film can be selectively formed in the front and back conduction holes of the laminate, and the plating film does not overlap the metal layer on the surface of the laminate.

【0019】[0019]

【発明の実施の形態】本発明に係るFPCの製造方法を
図面に基づいて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing an FPC according to the present invention will be described with reference to the drawings.

【0020】図1、図2および図3は本発明に係るFP
Cの製造方法の第一および第二の実施の形態の工程を示
す断面図である。
FIGS. 1, 2 and 3 show an FP according to the present invention.
It is sectional drawing which shows the process of 1st and 2nd embodiment of the manufacturing method of C.

【0021】本発明に係るFPCの製造方法の第一の実
施の形態は、図1a〜図1dおよび図2e〜図2gに示
すような工程にて製造される。
The first embodiment of the method of manufacturing an FPC according to the present invention is manufactured by steps shown in FIGS. 1A to 1D and FIGS. 2E to 2G.

【0022】図1aに示すように、絶縁層2の表裏両面
に金属層1を有する積層板3を用いる。金属層1として
は、銅、アルミニウム、真鍮、ニッケル等が挙げられ
る。絶縁層2としては、ポリイミドフィルム、ポリエス
テルフィルムが挙げられる。金属層1と絶縁層2を貼り
合わせるために接着剤を使用しても良い。
As shown in FIG. 1A, a laminate 3 having a metal layer 1 on both sides of an insulating layer 2 is used. Examples of the metal layer 1 include copper, aluminum, brass, and nickel. Examples of the insulating layer 2 include a polyimide film and a polyester film. An adhesive may be used to bond the metal layer 1 and the insulating layer 2 together.

【0023】次いで、図1bに示すように、積層板3を
貫通する表裏導通穴4を開ける。表裏導通穴4は、通常
ドリル等で形成する。
Next, as shown in FIG. 1B, front and back conduction holes 4 penetrating through the laminate 3 are formed. The front and back conduction holes 4 are usually formed by a drill or the like.

【0024】次いで、図1cに示すように、積層板3の
表裏導通穴以外の表面にフィルム5を貼着けてマスクす
る。マスク用のフィルム5としては、ドライフィルム等
が挙げられる。
Next, as shown in FIG. 1C, a film 5 is stuck on the surface of the laminate 3 other than the front and back conduction holes, and masked. Examples of the film 5 for a mask include a dry film.

【0025】次いで、図1dに示すように、表裏導通の
ためのメッキを施しメッキ皮膜6を形成する。メッキの
方法は、無電解メッキ、電解メッキが挙げられる。次い
で、図2eに示すように、マスク用のフィルム5を剥離
する。
Next, as shown in FIG. 1D, plating for front-to-back conduction is performed to form a plating film 6. Examples of the plating method include electroless plating and electrolytic plating. Next, as shown in FIG. 2E, the film 5 for a mask is peeled off.

【0026】マスク用のフィルム5と積層板3の表面と
の密着性が良いことから、マスク用のフィルム5と積層
板3との間にメッキ液がしみ込んで薄いメッキ層ができ
ることがなく、このためメッキ後にマスク用のフィルム
5を積層板3の表面から剥離することが容易で、かつ積
層板3の表面が粗くなることがない。
Since the adhesion between the mask film 5 and the surface of the laminate 3 is good, the plating solution does not seep between the mask film 5 and the laminate 3 to form a thin plating layer. Therefore, it is easy to peel off the mask film 5 from the surface of the laminate 3 after plating, and the surface of the laminate 3 does not become rough.

【0027】次いで、図2fに示すように、積層板3の
金属層1の表面より突出した部分13を研磨して、メッ
キを施した表裏導通穴3を有する積層板3を得る。突出
部分を確実に削るため、積層板3の金属層1を1〜2μ
m余分に研磨することがより好ましい。
Next, as shown in FIG. 2F, a portion 13 protruding from the surface of the metal layer 1 of the laminate 3 is polished to obtain a laminate 3 having plated front and back conduction holes 3. The metal layer 1 of the laminated plate 3 should be 1 to 2 μ
It is more preferable to perform extra polishing.

【0028】次いで、図2gに示すように、積層板3の
表裏面に回路8を形成してFPC9を得る。回路8を形
成する方法としては、例えば、以下のエッチング法が挙
げられ、積層板3の表面にレジストフィルムを付着し、
マスクフィルムを貼着け露光し、現像して、レジストフ
ィルムのパターニングを行なった後、エッチングして回
路を形成する。
Next, as shown in FIG. 2g, a circuit 8 is formed on the front and back surfaces of the laminate 3 to obtain an FPC 9. As a method of forming the circuit 8, for example, the following etching method can be mentioned, and a resist film is attached to the surface of the laminate 3;
A mask film is attached and exposed, developed, patterned on a resist film, and then etched to form a circuit.

【0029】積層板3の表面にメッキ皮膜が形成されな
いため、積層板3の金属層1の上にさらにメッキ皮膜を
重層することがなく、得られた積層板3の表面の金属層
は、出発材料の積層板3の金属層1のみからなる。この
ため得られた積層板3の表面は平坦であり、得られた積
層板3の表面に付着される回路形成用レジストフィルム
が確実に密着し、このため回路形成歩留まりに優れる。
また、得られた積層板3の表面の金属層は薄く、また厚
みのばらつきが小さく、このため高精細回路形成が容易
である。さらに、得られた積層板3の表面の金属層が薄
いため、得られたFPC9は屈曲性能に優れる。
Since the plating film is not formed on the surface of the laminate 3, no plating film is further formed on the metal layer 1 of the laminate 3, and the resulting metal layer on the surface of the laminate 3 is It consists only of the metal layer 1 of the laminate 3 of the material. For this reason, the surface of the obtained laminate 3 is flat, and the resist film for circuit formation adhered to the surface of the obtained laminate 3 surely adheres, and therefore, the circuit formation yield is excellent.
In addition, the metal layer on the surface of the obtained laminate 3 is thin and has a small variation in thickness, so that it is easy to form a high-definition circuit. Further, since the metal layer on the surface of the obtained laminate 3 is thin, the obtained FPC 9 has excellent bending performance.

【0030】本発明に係るFPCの製造方法の第二の実
施の形態は、上記の第一の実施の形態の工程の中に図3
hに示すような工程を行なう工程にて製造される。
The second embodiment of the method of manufacturing an FPC according to the present invention includes the steps of FIG.
h.

【0031】上記の第一の実施の形態において、積層板
3に表裏導通穴4を開けたものに、図3hに示すよう
に、無電解メッキを施しメッキ皮膜10を形成する。次
いで、図1c、図1d、図2e〜図2gに示すように、
第一の実施の形態の工程と同様に行う。無電解メッキを
施すことにより、続いて施すメッキを含むメッキ皮膜全
体の積層板3との密着性を高くできる。
In the first embodiment described above, electroless plating is performed on the laminated plate 3 in which the front and back conduction holes 4 are opened, as shown in FIG. Then, as shown in FIGS. 1c, 1d, 2e-2g,
The process is performed in the same manner as the process of the first embodiment. By applying the electroless plating, the adhesion of the entire plating film including the subsequently applied plating to the laminate 3 can be increased.

【0032】[0032]

【実施例】以下に実施例によって本発明をさらに詳細に
説明する。
The present invention will be described in more detail with reference to the following examples.

【0033】(実施例1)図1a〜図1dおよび図2e
〜図2gにより説明する。
(Embodiment 1) FIGS. 1a to 1d and 2e
2g.

【0034】ポリイミドフィルムの絶縁層2の表裏両面
に銅の金属層1(18μm)を有する積層板3を使用し、
これにドリル加工で積層板3を貫通する表裏導通穴4を
開けた。次いで、積層板3の表裏導通穴以外の表面にフ
ィルム5を貼着けてマスクし、次いで、表裏導通のため
の銅の電解メッキを施しメッキ皮膜6を形成した。次い
で、マスク用のフィルム5を剥離した。マスク用のフィ
ルム5の剥離は容易であった。また、メッキは表裏導通
穴およびその周囲のみに付いており、マスクされた積層
板3の表面7にはメッキは付いていなかった。次いで、
積層板3の銅の金属層1の表面より突出した部分13を
研磨して、メッキを施した表裏導通穴を有する積層板3
を得た。得られた積層板3の銅の金属層の部分の厚さは
出発材料の積層板3のものと同じ18μmであった。
Using a laminate 3 having a copper metal layer 1 (18 μm) on both front and back sides of an insulating layer 2 of a polyimide film,
The front and back conduction holes 4 penetrating the laminated plate 3 were formed by drilling. Next, the film 5 was stuck on the surface of the laminated plate 3 other than the front and back conduction holes to mask, and then electrolytic plating of copper for front and back conduction was performed to form a plating film 6. Next, the mask film 5 was peeled off. Peeling of the mask film 5 was easy. Further, plating was provided only on the front and back conduction holes and the periphery thereof, and no plating was provided on the surface 7 of the masked laminate 3. Then
A portion 13 of the laminated plate 3 protruding from the surface of the copper metal layer 1 is polished, and the laminated plate 3 having plated front and back conduction holes is provided.
I got The thickness of the copper metal layer portion of the obtained laminate 3 was 18 μm, which was the same as that of the laminate 3 of the starting material.

【0035】得られた積層板3について、その表裏面に
エッチング法で回路8を形成してFPC9を得た。得ら
れたFPC9の回路間隔は50μmが可能であった。ま
た、IPC法(屈曲半径5mm、ストローク40mm)で屈曲
性能を評価したところ、抵抗上昇は2000万回でも認めら
れなかった。
With respect to the obtained laminated board 3, a circuit 8 was formed on the front and back surfaces thereof by an etching method to obtain an FPC 9. The circuit interval of the obtained FPC 9 could be 50 μm. When the bending performance was evaluated by the IPC method (bending radius: 5 mm, stroke: 40 mm), no increase in resistance was observed even after 20 million times.

【0036】(比較例1)図4a〜図4dにより説明す
る。
(Comparative Example 1) A description will be given with reference to FIGS. 4A to 4D.

【0037】実施例1において、積層板3に表裏導通穴
4を開けたものに、フィルムを貼着けるマスクをせず、
表裏導通のために銅の電解メッキを施し、メッキ皮膜
6、11を形成して、メッキを施した表裏導通穴を有す
る積層板3を得た。得られた積層板3の銅の金属層の厚
さは33μm(出発材料の積層板3の銅の金属層18μm+銅
のメッキ皮膜15μm)であった。次いで、得られた積層
板3の表裏両面に、エッチング法で回路8を形成してF
PC9を得た。得られたFPC9の回路間隔は100μmで
あった。また、実施例1と同様の方法で屈曲性能を評価
したところ、抵抗上昇が150万回で認められた。
In the first embodiment, the laminated plate 3 having the front and back conductive holes 4 formed therein is not provided with a mask for attaching a film.
Electroplating of copper was performed for front-to-back conduction, plating films 6 and 11 were formed, and a laminated board 3 having plated front-back conduction holes was obtained. The thickness of the copper metal layer of the obtained laminate 3 was 33 μm (18 μm of copper metal layer of the laminate 3 as a starting material + 15 μm of copper plating film). Next, a circuit 8 is formed on both the front and back surfaces of the obtained laminate 3 by an etching method,
PC9 was obtained. The circuit interval of the obtained FPC 9 was 100 μm. When the bending performance was evaluated in the same manner as in Example 1, an increase in resistance was observed at 1.5 million times.

【0038】(比較例2)図5a〜図5dにより説明す
る。
(Comparative Example 2) This will be described with reference to FIGS. 5A to 5D.

【0039】実施例1において、積層板3に表裏導通穴
4を開けたものの表面にポリイミドのフィルム5を部分
的に貼り着けてマスクし、次いで、表裏導通のために銅
の電解メッキを施し、メッキ皮膜6、11を形成した。
次いで、マスク用のフィルムを剥離した。次いで、積層
板の表面のメッキが付いた部分と付いていない部分の段
差12を研磨で滑らかにして、メッキを施した表裏導通
穴を有する積層板3を得た。得られた積層板について、
その表裏面にエッチング法で回路8を形成してFPC9
を得た。得られた積層板3は、銅の金属層の厚さが薄い
部分を有するものの、厚さが部分的に異なるため、得ら
れた積層板3の表面に付着される回路形成用レジストフ
ィルムの密着性が悪く回路形成歩留まりに劣った。
In the first embodiment, a polyimide film 5 is partially adhered to the surface of the laminated plate 3 in which the front and back conduction holes 4 are opened and masked, and then, electrolytic plating of copper is performed for front and back conduction. Plating films 6 and 11 were formed.
Next, the mask film was peeled off. Next, the step 12 between the plated portion and the non-plated portion on the surface of the laminate was smoothed by polishing to obtain a laminate 3 having plated front and back conduction holes. About the obtained laminate,
A circuit 8 is formed on the front and back surfaces by an etching method to form an FPC 9
I got Although the obtained laminate 3 has a portion where the thickness of the copper metal layer is thin, the thickness is partially different, so that the adhesion of the circuit-forming resist film adhered to the surface of the obtained laminate 3 is obtained. Poor performance and inferior circuit formation yield.

【0040】[0040]

【発明の効果】本発明のFPCの製造方法によると、出
発材料の積層板の表裏導通穴にメッキを施す際に、該積
層板の表裏導通穴以外の表面にフィルムを貼着けてマス
クする。フィルムと積層板の表面は密着性が良く、フィ
ルムと積層板の表面との間に隙間を生じてメッキ液がし
み込むことがない。さらに、積層板の表面の金属層にメ
ッキ皮膜を重層しないので、得られる積層板は、表面が
平滑で、また、表面の金属層が薄くその厚みのばらつき
が少ない。このため、この積層板は、積層板の表面に付
着される回路形成用レジストフィルムの密着性が高くな
って、回路形成歩留まりが向上し、また、高精細回路の
形成が容易となり、さらに、得られるFPCは屈曲性能
に優れる。
According to the method of manufacturing an FPC of the present invention, when plating the front and back conduction holes of the laminate of the starting material, a film is attached to the surface of the laminate other than the front and back conduction holes and masked. The film and the surface of the laminate have good adhesion, and there is no gap between the film and the surface of the laminate, so that the plating solution does not soak. Further, since the plating film is not overlaid on the metal layer on the surface of the laminate, the resulting laminate has a smooth surface, a thin metal layer on the surface, and little variation in thickness. For this reason, this laminated board has high adhesion of the circuit-forming resist film adhered to the surface of the laminated board, improves the yield of circuit formation, and facilitates the formation of a high-definition circuit. The resulting FPC has excellent bending performance.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のFPCの製造方法の工程を示す断面図
である。
FIG. 1 is a cross-sectional view showing steps of a method for manufacturing an FPC of the present invention.

【図2】本発明のFPCの製造方法の工程を示す断面図
である。
FIG. 2 is a cross-sectional view showing steps of a method for manufacturing an FPC of the present invention.

【図3】本発明のFPCの製造方法の工程を示す断面図
である。
FIG. 3 is a cross-sectional view showing steps of a method for manufacturing an FPC of the present invention.

【図4】従来のFPCの製造方法の工程を示す断面図で
ある。
FIG. 4 is a cross-sectional view showing steps of a conventional method for manufacturing an FPC.

【図5】従来のFPCの製造方法の工程を示す断面図で
ある。
FIG. 5 is a cross-sectional view showing steps of a conventional method for manufacturing an FPC.

【符号の説明】[Explanation of symbols]

1 金属層 2 絶縁層 3 積層板 4 表裏導通穴 5 マスク用のフィルム 6 メッキ皮膜 7 表面 8 回路 9 FPC 10 無電解メッキ皮膜 11 メッキ皮膜 12 段差 13 突出部分 DESCRIPTION OF SYMBOLS 1 Metal layer 2 Insulating layer 3 Laminate board 4 Front and back conduction hole 5 Film for mask 6 Plating film 7 Surface 8 Circuit 9 FPC 10 Electroless plating film 11 Plating film 12 Step 13 Projection

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】絶縁層の表裏両面に金属層を有する積層板
に、金属層を貫通する表裏導通穴を形成し、この表裏導
通穴の内面にメッキ皮膜を形成するフレキシブルプリン
ト配線板の製造方法において、表裏導通穴以外の積層板
の表面にフィルムを貼着ける工程、積層板の表裏導通穴
にメッキを施してメッキ皮膜を形成する工程、および、
そのメッキ後、フィルムを積層板の表面から剥離し積層
板の表面を研磨する工程を包含するフレキシブルプリン
ト配線板の製造方法。
1. A method of manufacturing a flexible printed wiring board, comprising: forming a front and back conduction hole penetrating a metal layer in a laminate having a metal layer on both front and back surfaces of an insulating layer; and forming a plating film on the inner surface of the front and back conduction hole. In, the step of attaching a film to the surface of the laminate other than the front and back conduction holes, the step of plating the front and back conduction holes of the laminate to form a plating film, and
A method of manufacturing a flexible printed wiring board, comprising a step of peeling a film from a surface of a laminate after the plating and polishing the surface of the laminate.
【請求項2】前記フィルムを積層板に貼着ける前に、積
層板に無電解メッキを施す工程をさらに包含する請求項
1記載のフレキシブルプリント配線板の製造方法。
2. The method for manufacturing a flexible printed wiring board according to claim 1, further comprising a step of subjecting the laminate to electroless plating before attaching the film to the laminate.
【請求項3】前記積層板の表面が、回路形成用レジスト
フィルムが確実に密着するよう平滑である請求項1記載
のフレキシブルプリント配線板の製造方法。
3. The method for manufacturing a flexible printed circuit board according to claim 1, wherein the surface of the laminate is smooth so that the circuit-forming resist film is securely adhered.
【請求項4】前記積層板の表面に前記メッキ皮膜が付着
していない請求項1記載のフレキシブルプリント配線板
の製造方法。
4. The method for manufacturing a flexible printed wiring board according to claim 1, wherein said plating film is not adhered to the surface of said laminated board.
JP14484198A 1998-05-26 1998-05-26 Manufacture of flexible printed board Withdrawn JPH11340623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14484198A JPH11340623A (en) 1998-05-26 1998-05-26 Manufacture of flexible printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14484198A JPH11340623A (en) 1998-05-26 1998-05-26 Manufacture of flexible printed board

Publications (1)

Publication Number Publication Date
JPH11340623A true JPH11340623A (en) 1999-12-10

Family

ID=15371685

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14484198A Withdrawn JPH11340623A (en) 1998-05-26 1998-05-26 Manufacture of flexible printed board

Country Status (1)

Country Link
JP (1) JPH11340623A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100351923B1 (en) * 1999-12-29 2002-09-12 앰코 테크놀로지 코리아 주식회사 method for fabricating PCB

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100351923B1 (en) * 1999-12-29 2002-09-12 앰코 테크놀로지 코리아 주식회사 method for fabricating PCB

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