JPH11339500A - Non-volatile semiconductor memory device and checking method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory which has a ferroelectric memory with a high reliability (a small failure rate) with respect to data holding by performing a sufficient check without performing a screening check requiring a long period of time which results in damage to products. SOLUTION: A non-volatile semiconductor memory has a ferroelectric memory cell 3 and a check circuit 2 for supervising a reduction in a power supply voltage Vcc and interrupting the power supply voltage Vcc when the voltage is lower than a predetermined voltage thereby deactivating the memory cell 3. A control means 1 is further provided therein for preventing the power supply voltage Vcc from being interrupted by way of a control input signal, even when the power supply voltage Vcc is lower than the predetermined voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a ferroelectric memory and a test method therefor. In particular, the present invention relates to a nonvolatile semiconductor memory device having a structure capable of reliably performing screening without performing a screening test in which a long-time stress accompanied with deterioration of a ferroelectric substance is applied.

[0002]

2. Description of the Related Art In a semiconductor memory such as a ferroelectric memory or a flash memory as shown in FIG. 8 as an example of a memory cell, the operation becomes abnormal when recording is performed in a state where a power supply voltage is reduced due to consumption of a battery or the like. Incorrect writing (insufficient writing) occurs. To prevent this, a control circuit including a detection circuit for detecting a power supply voltage and stopping the operation of the memory cell when the power supply voltage becomes equal to or lower than a predetermined voltage is provided. The control circuit 50 detects the power supply voltage by monitoring the voltage at a point P obtained by dividing the power supply voltage Vcc by the resistors R1 and R2, as shown in FIG. When the voltage falls below the voltage, the memory cell 51
And the logic circuit 52 and the power supply voltage Vcc are cut off so as not to be supplied. This predetermined voltage is set to a voltage B higher than the actually operable voltage A, as shown in FIG. 9B, in order to ensure the reliability of the semiconductor memory. The voltage between B and C (normal power supply voltage) is the voltage of the actual use area BC actually used. In FIG. 9B, AC is an operable area, OA is an inoperable area, and OB is a lockout area in which power is not supplied to the memory cell 51 or the logic circuit 52.

[0003] In this type of semiconductor memory, a screening test (inspection) is performed under severe conditions in which thermal stress is applied for a long time to reject defective products. In this screening test, a defect is initially generated in a flash memory or the like, and screening is performed.

[0004]

However, in a device using a ferroelectric, not only an initial failure as shown by a dotted line A but also a aging failure as shown by a dotted line B as shown in FIG. As a result, the number of defective products as shown by the curve C is shown. As described above, the ferroelectric film forming the ferroelectric memory is extremely weak against high temperatures, and there is a problem that the ferroelectric films are liable to be deteriorated when exposed to high temperatures. Therefore, a defective product occurs even after a long period of time, and in order to completely screen the defective product, a long screening test must be performed, and the life of the non-defective product is shortened by the screening test. Reliability cannot be sufficiently improved.

On the other hand, in a ferroelectric memory, as shown in FIG. 11 showing the relationship between temperature and polarizability, the higher the temperature, the higher the temperature.
There is a characteristic that the polarizability decreases. Further, as shown in FIGS. 12 and 13 showing the relationship between the applied voltage and the remanent polarization, there is also a characteristic that the remanent polarization is greatly reduced by lowering the operating voltage. Here, Figure 12 shows the rapid annealing (RTA: RAPI
D TEMPERATURE ANNEAL) is a hysteresis curve showing the relationship between the applied voltage and the remanent polarization in a ferroelectric memory in which a ferroelectric thin film was formed by a process. 6 is a curve showing a relationship between applied voltage and remanent polarization in a dielectric memory.
FIGS. 14 and 15 are diagrams showing polarization and voltage saturation characteristics in a ferroelectric memory in which a ferroelectric thin film is formed by RTA processing and furnace processing, respectively. In FIG. 14, the horizontal axis represents the applied voltage and the vertical axis represents the remanent polarization. In FIG. 15, the horizontal axis represents the applied voltage and the vertical axis represents the saturation voltage. Figures 14 and 15
In, black circles are due to RTA treatment and open circles are due to furnace treatment.

[0006] From these results, it has been found that, by lowering the operating voltage, the remanent polarization is greatly reduced, the operating conditions are stricter, and defective products can be remarkable. That is, as shown in FIG.
When a characteristic test is performed at a normal high voltage (for example, 5 V), D
When a characteristic check is performed at a low voltage (for example, 3 V) for a product which can be screened in the state of E, the saturation polarization is reduced to about half as apparent from FIG. The present invention has been made by paying attention to this point, and it has been found that the same effect can be obtained as that of increasing the screening time.

However, in this type of semiconductor memory, a detection circuit is provided so as not to operate at a voltage which can actually operate at a voltage lower than the actual use area in consideration of the operational safety as described above. . Moreover, since the set voltage of the detection circuit is fixed, it cannot be operated at a voltage lower than the actual use area. Therefore, even in the above-described screening test, the voltage can be reduced only to the lowest voltage in the actual use area, and there is a problem that sufficient screening cannot be performed. On the other hand, if the lower limit of the actual use area is lowered, there is a risk that erroneous writing may occur and reliability cannot be sufficiently maintained.

The present invention has been made in order to solve such a problem, and performs a long-term screening test to perform a sufficient test without damaging a product, and has a high reliability in data retention (a small number of defects). It is an object of the present invention to provide a non-volatile semiconductor memory having a ferroelectric memory having a ratio of:

[0009]

SUMMARY OF THE INVENTION A nonvolatile semiconductor memory according to the present invention comprises a ferroelectric memory cell and a power supply voltage cut off when the power supply voltage is lower than a predetermined voltage so that the memory cell is not operated. A non-volatile semiconductor memory having a control circuit, wherein control means is provided for controlling the power supply voltage so as not to be cut off by a control input signal even when the power supply voltage is lower than a predetermined voltage.

That is, in the nonvolatile semiconductor memory device according to the first aspect of the present invention, a ferroelectric memory cell, a detection circuit for detecting a power supply voltage as a monitor voltage, and a detection circuit for detecting the power supply voltage detected by the detection circuit. A shut-off circuit that shuts off the power supply voltage when the power supply voltage is lower than the write-protection voltage and disables the memory cell, and when the power supply voltage becomes lower than the write-protection voltage by a control input signal. Control means for stopping the shut-off operation of the shut-off circuit.

By providing this control means, a lock-out function for stopping the operation of the memory cell when the power supply voltage becomes lower than a predetermined voltage in a normal use state is provided, but the test is performed at a low voltage during the screening test. Can be severely inspected. As a result, even if a screening test in which a severe stress is applied to a semiconductor memory is not performed, a low voltage test is performed, and a situation equivalent to a high temperature test is created. Therefore, by such an inspection, those having a risk of deterioration can be sufficiently eliminated.

According to a second aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the control means invalidates the cutoff circuit by the control input signal without depending on the magnitude of the power supply voltage. It is characterized by including.

According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the control means receives the control input signal so as to be higher than the write inhibit voltage even if the power supply voltage is lowered. And means for increasing the monitor voltage based on the threshold value.

According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the control means boosts the monitor voltage detected by the detection circuit stepwise based on the control input signal. It is characterized by including.

According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory device according to the fourth aspect, the detection circuit includes a dividing resistor connected between a power supply voltage terminal and a ground, and the monitor voltage is connected to the power supply voltage terminal and a ground. It is configured to be detected by the voltage divided by the dividing resistor connected between,
The boosting means is means for adjusting a division ratio of the division resistance.

According to a sixth aspect of the present invention, in the method of testing a nonvolatile memory device, a ferroelectric memory cell, a detecting circuit for detecting a power supply voltage as a monitor voltage, and a detecting circuit for detecting the power supply voltage detected by the detecting circuit are provided. And a shut-off circuit for shutting off the power supply voltage when the power supply voltage is lower than the write-protection voltage so that the memory cell does not operate. An inactivation step of making the shut-off operation of the shut-off circuit inactive even at the voltage of 1, and applying the first voltage to each of the memory cells for a certain period of time. The method includes a low voltage stress applying step of applying a stress, and a detecting step of checking operating characteristics of each of the memory cells and detecting whether or not the memory cells are normal.

According to a seventh aspect of the present invention, in the inspection method of the nonvolatile semiconductor memory device according to the sixth aspect, the deactivating step includes controlling the shutoff circuit by a control input signal without depending on the magnitude of the power supply voltage. And disabling the power supply voltage so as not to cut off the power supply voltage.

According to an eighth aspect of the present invention, in the inspection method of the nonvolatile semiconductor memory device according to the sixth aspect, the deactivating step is performed based on a control input signal even if the power supply voltage is reduced. And increasing the monitor voltage so as to increase the monitor voltage.

According to a ninth aspect of the present invention, in the inspection method of the nonvolatile semiconductor memory device according to the sixth aspect, the deactivating step includes an adjusting step of boosting the monitor voltage by a required amount based on a control input signal. It is characterized by including.

According to a tenth aspect of the present invention, in the inspection method of the nonvolatile semiconductor memory device according to the ninth aspect, the deactivating step includes dividing a divided resistor connected between a power supply voltage terminal and the ground based on a control input signal. By adjusting the ratio,
The method includes an adjusting step of controlling the monitor voltage.

[0021]

Next, a nonvolatile semiconductor memory according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a nonvolatile semiconductor memory according to the present invention. As shown in FIG. 1, a memory block 10 in which a plurality of ferroelectric memory cells are arranged and divided into a plurality of blocks. And a peripheral circuit block 11 such as a sense circuit, a detection circuit 12 for dividing the power supply voltage Vcc by the first and second resistors R1 and R2, and detecting the divided voltage as a voltage at the point P. A low-voltage monitoring block that shuts off the power supply voltage and prevents the memory cell from operating when the power supply voltage is lower than the write inhibit voltage in accordance with the power supply voltage.
And a control block 14 for stopping the low voltage monitoring block 13 even when the power supply voltage Vcc becomes lower than the write inhibit voltage due to the control input signal Cs.

According to such a configuration, in a normal use state, the lock-out function for stopping the operation of the memory cell when the power supply voltage falls below the predetermined voltage (5 V) is provided. By inputting Cs, even if a low voltage of about 3 V is applied, the memory cell can operate without stopping the operation and can be inspected at a low voltage (3 V). It becomes possible. As a result, without performing a screening test in which a severe stress is applied to the semiconductor memory, a test at a low voltage can create a situation equivalent to a test at a high temperature by performing a visual inspection. Therefore, by such an inspection, those having a risk of deterioration can be sufficiently sifted off, and only non-defective products can be provided as non-defective products having undergone the screening test.

Next, a second embodiment of the present invention will be described. As shown in FIG. 2, the nonvolatile memory device according to the second embodiment of the present invention includes a variable resistor R instead of the control block 14 and the first and second resistors R1 and R2 in the first embodiment. Point control block 24 with 'and resistance R2
Is provided. In this device, the control input signal Cs
The variable resistor R1 of the P-point control block 24 is
By stepping up the monitor voltage detected by the detection circuit 12 by adjusting the resistance value of ',
It can be driven substantially at a low voltage.
That is, by increasing the monitor voltage, the monitor voltage detected by the detection circuit 12 is visually increased, so that the interruption operation of the low-voltage monitoring block 13 is stopped even when the voltage becomes lower than the write inhibit voltage. It is characterized by doing.

According to such an apparatus, as in the first embodiment, the power supply voltage becomes a predetermined voltage (5 V) in a normal use state.
In the screening test, the resistance value of the variable resistor R1 ′ is adjusted based on the control input signal Cs and has the lockout function of stopping the operation of the memory cell when the voltage drops further. In practice, by increasing the monitor voltage, 5
Even at a voltage lower than V (3 V), the lockout function of the memory cell does not work, and the memory cell operates, and it is possible to perform a severe inspection at a low voltage. As a result, without performing a screening test in which a severe stress is applied to the semiconductor memory, a test at a low voltage can create a situation equivalent to a test at a high temperature by performing a visual inspection. In addition to this effect, by adjusting the voltage at this time by adjusting the variable resistor R1 ′, the threshold voltage can be easily changed.

Next, a specific example of the circuit configuration of the third embodiment will be described with reference to FIG. It has a memory IC such as a ferroelectric memory cell 3 and a logic circuit 4, and a control circuit 2 for shutting off the power supply voltage Vcc when the power supply voltage Vcc is lower than a predetermined voltage so that the memory cell 3 and the like do not operate. The control input signal V is applied to the nonvolatile semiconductor memory.
A control means 1 is provided for controlling the power supply voltage Vcc so as not to cut off the power supply voltage Vcc even when the power supply voltage Vcc is lower than a predetermined voltage. In the example shown in FIG. 3, the control means 1
This is an example in which the NOR circuit 18 is formed so that the power supply voltage Vcc can be supplied to the memory cell 3 without interrupting the power supply voltage Vcc at all times.

That is, in the example shown in FIG. 3, the control circuit 2 comprises a p-channel transistor 21 and an n-channel transistor 22 connected in series to the power supply voltage Vcc.
The power supply voltage is set to the potential at point P at each gate, and NO
If the output of the NOR circuit 18 is low, the p-channel transistor 21 is turned on and the power supply voltage Vcc is supplied to the memory cell 3. When the monitor voltage is high, the p-channel transistor 21 is turned off, and the supply of the power supply voltage Vcc to the memory cell 3 is cut off. As the monitor voltage, a voltage at a division point (monitor point) P of a voltage dividing resistor in which the first and second resistors R1 and R2 are connected in series between the power supply voltage terminal and the ground is used. In the present invention, on the input side of the control circuit 2, as the control means 1, there is provided a NOR circuit 18 to which the control input signal Vin and the above-mentioned monitor voltage are input.

The control input signal Vin to the NOR circuit 11
In a normal state, a low signal is input, and a high signal is input to perform a screening test by lowering the power supply voltage Vcc during a screening test.

Next, the operation of the semiconductor memory will be described. First, when used as a normal memory, since the control input signal Vin of the control means 1 is low,
Both transistors 2 of the control circuit 2 according to the high and low of the voltage of the monitor point P which is the monitor voltage of the power supply voltage Vcc.
When a low or high signal is input to 1, 2 and the power supply voltage Vcc falls below a predetermined voltage (the monitor voltage is low), the p-channel transistor 21 is turned off, and the power supply voltage Vcc is changed to the memory cell 3 or It is not applied to the logic circuit 4 or the like. When the power supply voltage Vcc is normal and the monitor voltage is high, the p-channel transistor 21 is turned on and the voltage is supplied to the memory cell 3 and the like.

On the other hand, when performing a screening test,
The control input signal Vin of the control means 1 is set high, and the power supply voltage Vcc is reduced to near the lower limit of the operating voltage of the memory cell. At this time, even if the power supply voltage Vcc is too low and the monitor voltage becomes a low signal, the output of the NOR circuit 18 becomes low because the high control input signal is input to one input terminal of the NOR circuit 18, p-channel transistor 2
1 turns on, and a low power supply voltage Vcc is applied to the memory cell 3 and the like. As a result, the inspection can be performed under low-voltage conditions that are more severe than in normal operation.

According to the semiconductor memory of the present invention, since the control means for preventing the power supply voltage from being interrupted even when the power supply voltage is lower than the predetermined voltage is provided at the preceding stage of the control circuit, the screening test is performed at the lower limit of the operation area. It can be performed at a close voltage. Therefore, the same effect as that obtained by performing the screening for a very long time can be obtained, and the reliability can be improved. On the other hand, in the case of normal operation, the control signal is low, and when the power supply voltage decreases due to battery exhaustion or the like, the supply of the power supply voltage to the memory cells and the like is stopped by the detection circuit. Therefore, trouble such as erroneous writing does not occur.

In this example, the power supply voltage Vcc is always supplied without substantially operating the control circuit 2.
Although the NOR circuit is used, other structures such as a simple switching element may be used instead of the NOR circuit.

In the above example, the control circuit is directly controlled to make the original function inactive, and the rescreening test can be performed with a low power supply voltage.
In the following examples shown in FIGS. 4 to 7, even if the power supply voltage Vcc is lowered for the screening test, the monitor voltage input to the detection circuit is apparently increased to supply the power supply voltage to the memory cells and the like. It is controlled so that it can be performed. 4 to 7, the control circuit 5 includes a detection circuit for detecting the power supply voltage Vcc and a circuit for performing control in accordance with the detection voltage. Even if the voltage is low, a signal of a high power supply voltage is applied to the detection circuit.

First, the example shown in FIG.
The transistor Q1 is connected in parallel with the first resistor R1 on the side of the power supply terminal of the divided resistor for obtaining the monitor voltage of, and the control means 1 is formed. Then, in the control circuit 5,
A comparator 19 is provided at a stage preceding the control circuit 2 of FIG. 3 so that the monitor voltage at the point P controlled by the control means 1 is compared with the output of the constant voltage generation circuit 20 so that the monitor voltage at the point P is constant. Is added in order to control according to whether or not the voltage is higher than the voltage. This configuration is similar to that shown in FIG. 3 except that the monitor voltage is compared with a constant voltage. That is, the switching is performed by the control circuit 5 by the monitor voltage, and the application and cutoff of the power supply voltage Vcc to the memory cell 3 and the logic circuit 4 are switched. Next, in the example shown in FIG. 5, in the example shown in FIG. 4, the transistor Q1 and the transistor Q1 are connected in parallel with the first resistor R1 on the power supply terminal side of the divided resistor for obtaining the monitor voltage of the power supply voltage Vcc. The control means 1 is formed by connecting the three resistors R3 connected in series. Just like the other example shown in FIG. 4, the control circuit 5 performs switching by the monitor voltage, and switches between application and cutoff of the power supply voltage Vcc to the memory cell 3 and the logic circuit 4. It has become.

With this configuration, when a high control input signal is input to the gate of the first transistor Q1 during the screening test, the transistor Q1 is turned on, and the resistance between the power supply terminal and the monitor point P is reduced to the second value. 1 resistance R
1 and the value of the third resistor R3 connected in parallel (the resistance of the transistor Q1 is almost 0). As a result, the resistance value between the power supply terminal and the monitor point P decreases, and the potential of the monitor point P increases. Therefore, even if the power supply voltage Vcc decreases, the monitor voltage can be increased, and the control circuit 5 controls the power supply voltage Vcc.
cc is supplied to the memory cell 3, the logic circuit 4, and the like. That is, by lowering the power supply voltage Vcc to the lower limit of the operation area and inputting a high signal as the control input signal Vin at the time of the screening test, the control circuit 5 operates normally and the memory cells 3 and the like can operate. .

The example shown in FIG. 6 is a modification of the example of FIG. 5, in which a fourth resistor R4 and a transistor Q2 are connected in parallel between a monitor point P and the ground, and are connected in series. is there. According to this configuration, in the normal operation state, the control input signal Vin is set high and the transistor Q2 is turned on, so that the fourth resistor R4 is short-circuited. (The power supply voltage is not supplied to the memory cell side). On the other hand, when performing a screening test, the transistor Q
By inputting a low control input signal to the gate of the second transistor, the transistor Q2 is turned off, and the resistance between the monitor point P and the ground is increased by the fourth resistor R4. As a result, even if the potential of the monitor point P rises and the power supply voltage Vcc decreases, the output of the control circuit 5 can be turned on and the power supply voltage Vcc can be supplied to a memory cell or the like. That is, similarly to the above, in the normal operation, the lockout due to the decrease in the power supply voltage is set strictly, while the screening inspection can be performed strictly at a low voltage.

FIG. 7 is a further modification of FIG.
In the example shown in A, a fifth resistor R5 is connected between the first and second resistors R1 and R2, and the extraction point of the monitor point P is set by the p-channel transistor Q3 and the n-channel transistor Q4. Switching is performed between a connection point of the first and fifth resistors (high potential) or a connection point of the fifth and second resistors R5 and R2 (low potential). That is, when a low level is input to the control input signal, the p-channel transistor Q3 is turned on, and a high potential is a monitoring point. When a high level control input signal is input, the n-channel transistor Q4 is turned on and a low voltage is monitored. . Therefore, when performing a screening test, a low signal is input as a control input signal, and the power supply voltage is set to a voltage close to the lower limit of the operation area of the memory cell. Is input and turned on, a low power supply voltage is applied to the memory cell, and the inspection can be performed at a low voltage. Note that the order of connection of the n-channel transistor and the p-channel transistor may be reversed, in which case the high and low of the control input signal are reversed.

To change the monitor voltage by switching these two transistors, as shown in FIG. 7B, a p-channel transistor Q3 is connected between the monitor point P and the second resistor R2. And a fifth resistor connected in series, and an n-channel transistor Q4
Are connected in parallel, and each transistor Q
3. A control signal input terminal having the gates of Q4 connected thereto can be similarly configured. Even with this configuration,
As described above, by inputting high or low to the control input signal to turn on / off the transistors Q3 and Q4, when the transistor Q3 is on, the voltage including the fifth resistor R5 becomes the monitor voltage (high voltage). When the transistor Q4 is on, the voltage of only the second resistor becomes the monitor voltage (low voltage), and the switching between the screening test and the normal operation can be performed as described above. In this case, the resistance of the transistors connected in series can be regarded as almost zero.

[0039]

According to the present invention, the semiconductor memory has a lockout function of stopping its operation in a normal use state due to a decrease in the power supply voltage in a normal use state, but is lower than the normal operation during a screening inspection after manufacturing. Since the inspection can be performed by operating at a voltage, it is possible to select a product that can be sufficiently defective by a short-time screening inspection due to a deterioration in characteristics due to a low voltage of the ferroelectric substance. As a result, the product is not deteriorated by the screening test, the life of the product can be extended, and the product can be sorted without fail, so that the reliability of the product on the market is greatly improved. Further, the time for the screening test can be reduced, which greatly contributes to cost reduction.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a semiconductor memory of the present invention.

FIG. 2 is a diagram showing a configuration of another embodiment of the semiconductor memory of the present invention.

FIG. 3 is a diagram showing a configuration of another embodiment of the semiconductor memory of the present invention.

FIG. 4 is a diagram showing a configuration of another embodiment of the semiconductor memory of the present invention.

FIG. 5 is a diagram showing a configuration of another embodiment of the semiconductor memory of the present invention.

FIG. 6 is a circuit diagram of a control unit showing a modification of the configuration of FIG. 5;

FIG. 7 is a circuit diagram of a control unit showing another modification of the configuration of FIG. 5;

FIG. 8 is a diagram showing a memory cell of a semiconductor memory.

FIG. 9 is a block diagram illustrating an example in which a write-inhibition detection circuit for a decrease in power supply voltage of a conventional semiconductor memory is provided, and a diagram illustrating a relationship between a set voltage and an operation voltage.

FIG. 10 is a diagram showing the relationship between the time for screening a ferroelectric memory and the occurrence of defective products.

FIG. 11 is a diagram showing a relationship between a processing temperature and remanent polarization.

FIG. 12 is a hysteresis curve diagram showing a relationship between applied voltage and residual polarization of a PZT thin film formed by annealing.

FIG. 13 is a diagram showing a relationship between applied voltage and remanent polarization of a PZT thin film formed by furnace annealing.

FIG. 14 is a curve showing the relationship between the applied voltage of the thin film and the saturation remanent polarization.

FIG. 15 is a curve showing the relationship between the applied voltage and the saturation voltage of the thin film.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control means 2 Control circuit 3 Memory cell 5 Control circuit

Claims (10)

[Claims] 1. A ferroelectric memory cell, a detection circuit for detecting a power supply voltage as a monitor voltage, and, when the power supply voltage is lower than a write inhibit voltage, according to the power supply voltage detected by the detection circuit. A shutoff circuit for shutting off a power supply voltage to disable the memory cell, and a control capable of stopping the shutoff operation of the shutoff circuit even when the power supply voltage becomes lower than the write inhibit voltage by a control input signal. And a non-volatile semiconductor memory device. 2. The apparatus according to claim 1, wherein said control means includes means for disabling said cutoff circuit by said control input signal without depending on the magnitude of said power supply voltage.
The nonvolatile semiconductor memory device according to claim 1. 3. The apparatus according to claim 2, wherein said control means includes means for increasing said monitor voltage based on said control input signal such that said monitor voltage is higher than said write inhibit voltage even if said power supply voltage is lowered. Item 2. The nonvolatile semiconductor memory device according to Item 1. 4. The non-volatile memory according to claim 1, wherein said control means includes a step-up means for step-wise raising said monitor voltage detected by said detection circuit based on said control input signal. Semiconductor memory device. 5. The detecting circuit includes a dividing resistor connected between a power supply voltage terminal and a ground, wherein the monitor voltage is detected by voltage division by the dividing resistor. 5. The nonvolatile semiconductor memory device according to claim 4, wherein said means is a means for adjusting a division ratio of said division resistance. 6. A ferroelectric memory cell, a detection circuit for detecting a power supply voltage as a monitor voltage, and the power supply when the power supply voltage is lower than a write inhibit voltage in accordance with the power supply voltage detected by the detection circuit. A non-volatile semiconductor memory device having a shut-off circuit that shuts off a voltage to stop operating the memory cell. The shut-off operation of the shut-off circuit even when the power supply voltage becomes a first voltage lower than a write inhibit voltage. A low-voltage stress applying step of applying a first voltage to each of the memory cells for a certain period of time to apply stress to the memory cells; and Checking the operating characteristics of each memory cell after the stress applying step, and detecting whether or not the memory cell is normal.査方 method. 7. The inactivating step includes a step of disabling the cutoff circuit by a control input signal without depending on the magnitude of the power supply voltage, and providing an output that does not cut off the power supply voltage. 7. The method for testing a nonvolatile semiconductor memory device according to claim 6, wherein 8. The inactivating step, wherein even if the power supply voltage decreases, the power supply voltage becomes higher than the write inhibit voltage.
7. The method according to claim 6, further comprising the step of adjusting the monitor voltage based on a control input signal. 9. The non-volatile semiconductor memory device according to claim 6, wherein said inactivating step includes an adjusting step of boosting said monitor voltage by a required amount based on a control input signal. Inspection method. 10. The inactivating step includes an adjusting step of controlling the monitor voltage by adjusting a dividing ratio of a dividing resistor connected between a power supply voltage terminal and the ground based on a control input signal. 10. The method according to claim 9, wherein the inspection is performed on a nonvolatile semiconductor memory device.