JP2000299000A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable applying lower voltage than power source voltage independently of at the time of testing reliability by switching power source voltage or dropped voltage and supplying it to a memory block voltage by a control input using a dropping part dropping power source voltage. SOLUTION: As a high signal is outputted from a control circuit 23, a NMOS transistor 21 is turned on and a PMOS transistor 22 is turned off, therefore a power source terminal 6 is connected to a dropping part 1 side. In the same way, as a low signal is outputted, a NMOS transistor 21 is turned off and a PMOS transistor 22 is turned on, a power source terminal 6 is connected to a by-pass part 3 side being not dropped. A driving circuit 4 is connected to a word line, a bit line, or a plate line of a memory block 5, and supplies dropped voltage or power source voltage being not dropped to a memory cell having an address decoded by an address decoder 43.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory having memory cells such as a ferroelectric memory.
More specifically, by applying a voltage lower than that of the other element portions to the memory cell to protect the memory cell portion, and without performing a screening test for applying a long-time stress to the deterioration due to the use of the ferroelectric, The present invention relates to a semiconductor memory having a structure capable of performing inspection at a low voltage and performing screening reliably.

[0002]

2. Description of the Related Art In a semiconductor memory such as a ferroelectric memory or a flash memory, when recording is performed in a state where a power supply voltage is reduced due to consumption of a battery or the like, the operation becomes abnormal and erroneous writing (insufficient writing) occurs. . To prevent this, a low-voltage monitoring block is provided that detects the power supply voltage and stops the operation of the memory block when the power supply voltage falls below a predetermined voltage. The low-voltage monitoring block 100 monitors the power supply voltage Vcc with a voltage divided by resistors R1 and R2, for example, as shown in FIG.
Is not supplied with the power supply voltage Vcc. This predetermined voltage is set to a voltage B higher than the actually operable voltage A, as shown in FIG. 10B, in order to ensure the reliability of the semiconductor memory. And
The voltage between B and C (normal power supply voltage) is the voltage of the actual use area BC actually used. Note that FIG.
In (b), AC is an operable area, OA is an inoperable area, and OB is a lockout area where power is not supplied to the memory block 51. In FIG. 10A, reference numeral 102 denotes a peripheral circuit block.

In this type of semiconductor memory, a screening test (inspection) is performed under severe conditions to which thermal stress is applied, and defective products are eliminated. In this screening test, a defect is initially generated in a flash memory or the like and screening is performed. However, in a device using a ferroelectric substance, as shown in FIG. In order to completely screen the defective product, a long screening test must be performed. Since the deteriorated polarization characteristics of the ferroelectric material are not recovered, the life of the non-defective product itself is shortened, and the reliability is reduced. It cannot be improved sufficiently.

When thermal stress is applied by holding the ferroelectric capacitor at a high temperature, FIG. 9 shows the difference between the polarization charge before the thermal stress is applied and the polarization charge after the thermal stress is applied to the temperature of the thermal stress. ΔQ (μC / c
As shown in the change in m ² ), the higher the temperature of the thermal stress, the more remarkable the deterioration of the polarization appears, and the higher the temperature, the same effect as that of performing the screening for a long time appears. Since the degraded polarization characteristics do not recover,
The higher the temperature, the more good products are rejected.

[0005]

On the other hand, in a ferroelectric,
As shown in FIG. 7, the characteristic of the polarization charge Pr (μC / cm ² ) with respect to the applied voltage is such that an almost constant polarization is obtained at a certain voltage (threshold voltage) or higher, whereas a sharp decrease occurs at a voltage lower than the threshold voltage. It has the property of reducing the polarization charge. As a result of the inventor's earnest study, it is clear that the characteristics of the ferroelectric which becomes defective due to the screening of the ferroelectric memory are in a state where the polarization charge is low from the initial state as shown by the broken line in FIG. Became. Therefore, by lowering the operation voltage to a voltage lower than or equal to a voltage near the threshold, the operation condition becomes strict, and the defective product can be remarkable.

That is, as shown in FIG. 7, when a characteristic test is carried out at a normal high voltage (for example, about 5 V), a polarization failure is detected even for a future defective product indicated by a broken line, and a good product is determined. However, by performing a characteristic check at a low voltage (for example, about 3 V), a product that will be defective in the future has clearly less polarization, and it can be immediately predicted that the product is defective. Therefore, when a normal screening is performed, a product which becomes defective between DEs in FIG.
It can be identified in the same manner as when screening was performed in the initial state, and has the same effect as increasing the screening time.

However, in this type of semiconductor memory, a low-voltage monitoring block is provided so that a voltage which can actually operate does not operate at a voltage lower than an actual use area in consideration of safety of operation as described above. ing. Moreover, since the set voltage of the low-voltage monitoring block is fixed, it cannot be operated at a voltage lower than the actual use area. Therefore, in the screening test described above,
There is a problem that the voltage can be reduced only to the lowest voltage in the actual use area, and sufficient screening cannot be performed. On the other hand, if the lower limit of this actual use area is lowered,
There is a risk of erroneous writing and reliability cannot be sufficiently maintained.

SUMMARY OF THE INVENTION The present invention has been made to solve such a problem. A nonvolatile semiconductor memory having a structure in which a reduced power supply voltage can be applied to a memory block in addition to the power supply voltage at the time of reliability inspection. The purpose is to provide.

Another object of the present invention is to provide a long-term screening test, which has a ferroelectric memory, to perform a sufficient test without damaging a product, and to provide a high reliability (less data storage). (Defective rate).

[0010]

A non-volatile semiconductor memory according to the present invention monitors a power supply terminal, a memory block, and a decrease in a voltage applied to the power supply terminal. A low-voltage monitoring block for stopping supply of a voltage, a step-down unit for stepping down a power supply voltage, and a transformer for switching the power supply voltage or the stepped-down voltage to the memory block according to a control input and supplying the memory block; .

With this structure, a low-voltage monitoring block monitors a decrease in the power supply voltage in a normal use state, and prevents the semiconductor memory from operating at a low voltage even in a semiconductor memory formed of a ferroelectric memory having a lockout function. In addition, it is possible to operate at a low voltage at the time of inspection such as screening, so that inspection such as screening can be performed with high accuracy under severe conditions without damaging the semiconductor memory.

The transformer has a structure in which the step-down unit and the power supply voltage bypass unit are connected in parallel via a selection unit, and the voltage of the step-down unit or the bypass unit is output by the control input. With this configuration, it is possible to perform an inspection under a severe condition of a low voltage at the time of inspection while having a lockout function when the power supply voltage is reduced in a normal state with a simple configuration.

The step-down portion is formed, for example, by a transistor or diode connection structure. The transistor may have a structure in which, for example, a gate and a drain of a MOS transistor are connected. Here, the connection structure means connection such as series connection or a combination of series and parallel connection.

The memory block has a ferroelectric capacitor and a MOS transistor connected in series between a plate line and a bit line, and a word line and a plate line to which a gate of the MOS transistor is connected. May be configured so that the voltage of the step-down unit can be selectively applied to at least one of them. Here, the bit line has a pair of symmetric elements in one cell,
When a bit bar line is provided, the bit bar line is also included.

[0015]

Next, a nonvolatile semiconductor memory according to the present invention will be described with reference to the drawings. The nonvolatile semiconductor memory of the present invention includes a power supply terminal 6 and a power supply terminal 6 as shown in FIG.
A memory block 5, a low voltage monitoring block 8 having a command (broken line Q) for monitoring a drop in the voltage applied to the power supply terminal 6 and stopping the supply of the voltage to the memory block 5 when the voltage is equal to or lower than a predetermined voltage; Step-down unit 1 for stepping down voltage Vcc
(See FIG. 1B), and a transformer 7 for switching and supplying the power supply voltage Vcc or the stepped-down voltage to the memory block 5 by a control input.

As shown in FIG. 1B, the transformer 7 includes a step-down unit 1 for lowering the power supply voltage Vcc supplied to the power supply terminal 6, and a bypass unit 3 for transmitting the power supply voltage Vcc without being reduced. Are connected in parallel via the selection unit 2, and either the output of the step-down unit 1 or the power supply voltage Vcc of the bypass unit 3 can be applied to the memory block 5 via the drive unit 4 based on the control input. It has a structure. The selecting section 2 has a control circuit 23 and is formed so that the output of the step-down section 1 and the power supply voltage Vcc of the bypass section 3 can be selected by input of a control signal from the outside.

In the example shown in FIG. 1, the step-down unit 1 includes n-channel (hereinafter, referred to as NMOS) transistors 11, 1
2, 13 are connected in series. This NM
The OS transistors 11, 12, and 13 are each formed in a so-called diode connection structure in which the gate and the drain are connected. This MOS transistor (same for a diode-connected one) requires a threshold voltage Vth determined by a semiconductor material or the like before a voltage is applied and the current starts to flow, and this voltage Vth is M
It can be freely controlled by setting the channel concentration of the OS transistor, and can be lowered by, for example, about 0.6 V. However, Vth varies depending on the semiconductor device.
Also, not only Vth but also the substrate bias effect occurs,
A voltage drop occurs that is equal to or greater than the sum of Vth of the transistors connected in series. Therefore, although some adjustment is required, the voltage drop increases according to the number, and the number is set according to the voltage to be reduced. This connection may be a combination of a parallel connection and a series connection. In the example shown in FIG. 1, the step-down unit 1 and the transistor 21 reduce the voltage by a total of 2.4 V (Vth = 0.6 V).

The selection section 2 is configured such that, for example, an NMOS transistor 21 and a p-channel (hereinafter referred to as PMOS) transistor 22 are connected in series, a power supply terminal 6 is connected to a connection point between the two, and a power supply voltage Vcc is applied. It has become. The other end of each of the transistors 21 and 22 is connected to the step-down unit 1 and the bypass unit 3 which is a power supply voltage not to be stepped down. The drive unit 4 is connected to a connection point between the two. Note that the bypass portion 3 that does not lower the voltage is formed by wiring with a small voltage drop. The gates of the transistors 21 and 22 are connected to each other and connected to a control circuit 23. For example, the control circuit 23 has an external terminal 24 for inputting a control signal. By inputting a low signal, the power supply terminal 6 selects and connects one of the step-down unit 1 and the bypass unit 3 that does not step down.

That is, when a high signal is output from the control circuit 23, the NMOS transistor 21 is turned on, and P
The MOS transistor 22 turns off. As a result, the power supply terminal 6 is connected to the step-down unit 1 side. The control circuit 23
Output a low signal from the NMOS transistor 21
Is turned off, and the PMOS transistor 22 is turned on. As a result, the power supply terminal 6 is connected to the side of the bypass unit 3 that does not step down.

The drive circuit 4 is connected to a word line, a bit line (data line) or a plate line (electrode of a dielectric capacitor) of the memory block 5, and is stepped down to a memory cell of an address decoded by the address decoder 43. Supply voltage or power supply voltage that is not stepped down. The power supply voltage Vcc is directly applied to peripheral circuit blocks and the like.

The memory block 5 has a structure as shown in FIG. 5, for example. In this example, each memory cell 50 includes a first ferroelectric capacitor 51 and a first MOS transistor 52 connected in series between a plate line PL and a bit line BL, a plate line PL and a bit bar line. A second ferroelectric capacitor 53 and a second MOS transistor 54 are connected in series with (−BL). And
One of the first and second ferroelectric capacitors is polarized in the forward direction, and the other capacitor is polarized in the opposite direction to record 1 or 0, and the sense amplifier enable line SE is turned on. The comparator 55 compares which of the bit line BL and the bit bar line (-BL) is larger, and reads out and outputs 1 or 0. However, the structure of the memory cell is not limited to this example, and can be similarly applied to a one-transistor / one-capacitor type, a one-transistor type, and the like.

The operation of the memory cell is performed according to the schedule shown in FIG. That is, as shown in (1), the precharge enable line PE is set high, and the bit line BL and the bit bar line (-B
L) is initialized. Next, when a voltage is applied to the word line WL, a voltage is applied to the plate line PL as shown in (2), and the bit line (BL, -BL) is floated from the ground, thereby discharging the charge of the ferroelectric capacitor. The potential increases according to the amount of charge. Then, when the voltage of the plate line PL is set to 0, the potential of the bit line decreases as follows. In this state, when the sense amplifier line SE is turned high to turn on the sense amplifier, the comparator 55 shown in FIG.
Is determined by detecting the potential difference between the two lines,
Confirm the data. After that, the plate line P
By applying a voltage to L, the bit bar line (−
Writing on the BL) side is performed, and the voltage on the plate line PL is set to 0, thereby writing on the bit line (BL) side. Note that the timing at which the sense amplifier line SE is set to high (enable) may be in the region.

Next, a specific example of applying a voltage stepped down by the step-down unit 1 from the transformer unit 7 or a power supply voltage Vcc via the bypass unit 3 to the memory block 5 will be described with reference to FIGS.
It will be described with reference to FIG.

FIG. 2 shows an example of a structure capable of applying a stepped-down voltage to a plate line PL of a memory block. That is, the voltage selected by the selection unit 2 is applied to the memory cell 50 at a predetermined address via the drive unit 4, but in the example shown in FIG. 2, the voltage is connected to the plate line PL. It has become so. The other word lines WL are wired so that a power supply voltage Vcc that does not drop is applied. As a result, the word line WL
When the voltage applied to the plate line PL is reduced to, for example, 3 V when the voltage is applied to the plate line PL and the bit line BL is 0, only the voltage of 3 V is applied to the ferroelectric capacitor 51. However, as described above, only a small amount of polarization charge is generated, or an insufficient polarization inversion state occurs. Therefore, the polarization of a ferroelectric capacitor having poor polarization characteristics cannot be sufficiently detected. Since the applied electric field is in the same direction as the polarization of the ferroelectric capacitor 53 on the other bit bar line (-BL) side, the inverted charge has no effect.

The example shown in FIG. 3 is an example of a structure capable of applying a stepped-down voltage to a word line WL of a memory block. The configuration of the transformer 7 is the same as that of the above-described example, and a voltage stepped down by the step-down unit 1 at the time of inspection is applied to a predetermined memory cell 50 via the drive unit 4 to the memory block 5. When a stepped-down voltage, for example, 3 V, is applied to word line WL in this manner, MOS transistors 52 and 53 are regulated by their gate voltages.
Only 3 V is applied to 1, 53, and only a small amount of polarization charge is generated as in the above-described case, and the inspection is performed under severe conditions.

With such a configuration, even if the step-down unit 1 is not directly formed on the power line for large current as described above,
What is necessary is just to form a step-down part of the voltage for application to the word line WL. The word line WL is connected to the gate of the MOS transistor as described above, and requires almost no current capacity. Therefore, the step-down portion also requires almost no current capacity and can be formed with a very small area, which is particularly preferable.

The example shown in FIG. 4 is a structure example in which a stepped-down voltage can be applied to both the plate line PL and the word line WL of the memory block 5. The configuration of the transformer 7 is the same as that of the above-described example, and a voltage stepped down by the step-down unit 1 at the time of inspection is applied to a predetermined memory cell 50 via the drive unit 4 to the memory block 5. When a stepped-down voltage, for example, 3 V, is applied to both the plate line PL and the word line WL in this manner, even if the plate line PL is polarized in either the positive voltage or zero direction (either the capacitor 51 or 53). ), The polarization is always caused by the stepped-down voltage, and the reliability is further improved.

Further, with this configuration, the power supply wiring to each of the plate lines PL and the word lines WL of the memory block 5 can be made common, so that the routing of the wiring requiring a current capacity can be reduced. it can.
That is, if the voltage of the step-down unit can be applied to only one of the plate line PL and the word line WL, a power supply line via the transformer 7 is required on one of the lines, and the transformer line is connected to the other line. Although it is necessary to route a power supply line that does not pass through the unit 7, according to this example, both need only be a power supply line that passes through the transformer 7.

Next, the screening operation in the semiconductor memory of the present invention will be described. First, when performing a screening test, a high signal is input from the control signal input terminal 24 to the control circuit 23, and the power supply terminal 6 is connected to the selection unit 2.
To the step-down unit 1 side. In the step-down unit 1, as described above, the voltage drops by more than the sum of the threshold voltages Vth depending on the number of NMOS transistors. for that reason,
For example, if three NMOS transistors are connected, the voltage supplied to the drive circuit 4 via the step-down unit 1 is Vcc
-4Vth. Since the stepped-down voltage is set to a voltage near the lower limit at which the memory cell can operate,
The memory cell operates at that voltage, and a screening test is performed.

In the case of a ferroelectric memory, the characteristics are significantly deteriorated due to the inspection at a low voltage as described above, and the same screening as that performed at a high voltage by performing a long-time screening is performed. be able to. Therefore, by performing the inspection by lowering the power supply voltage Vcc in this way, it is possible to perform an extremely accurate screening inspection.

On the other hand, in a normal use state, by outputting a low control signal to the control circuit 23, the selector 2 turns off the NMOS transistor 21 and turns on the PMOS transistor 22. The terminal 6 is connected to the power supply voltage unit 3 which does not step down. As a result, the power supply voltage Vcc without voltage drop is applied to the memory cell 5 via the drive circuit 4 as it is, and the memory cell 5 is used. Table 1 summarizes the operation table at the time of this test and during normal use.

[0032]

[Table 1] With such a configuration, when performing a screening test, a test can be performed by applying a low voltage, which is a power supply voltage lowered by a control signal of a control circuit, to the memory cell, so that a very high-precision screening is performed. Inspection can be done. In addition, the lockout mechanism for preventing a malfunction such as an erroneous write when the power supply voltage decreases is operated as it is, so that the reliability in the market can be greatly improved. Furthermore, even if a low voltage is applied,
The ferroelectric capacitor and the like are not destroyed at all, and do not shorten the service life to which a thermal stress is applied.

In the above-described example, during screening inspection of a semiconductor memory having a ferroelectric memory, the inspection is performed at a voltage lower than the lockout voltage in a normal operation state, and a normal power supply voltage is applied in a normal use state. In addition, when the power supply voltage is lower than a predetermined voltage, the lockout voltage at which the power supply voltage is not applied to a memory cell or the like is sufficiently increased. However, in order to improve the reliability of the memory cell as in a DRAM or the like. , Other logic I only in the memory cell
When a lower voltage such as C is applied, a similar step-down portion can be formed, and a higher voltage can be applied by a control signal of a control circuit.

[0034]

According to the present invention, a step-down unit for lowering the power supply voltage is incorporated, and any of the power supply voltage and the lowered voltage can be arbitrarily selected and applied to the memory block unit. Therefore, for example, when a ferroelectric memory is provided, while a screening test is performed under a strict condition of a low voltage, monitoring of a drop in a power supply voltage or the like can be performed with a sufficient lockout voltage margin. As a result, the screening test can be performed in a short time, the product is not deteriorated by the screening test, the life of the product can be extended, and the product can be sorted without fail. The reliability is greatly improved. Further, the time for the screening test can be reduced, which greatly contributes to cost reduction.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of one embodiment of a semiconductor memory of the present invention.

FIG. 2 is a configuration explanatory diagram of a specific example of an example of applying a stepped-down voltage of FIG. 1;

FIG. 3 is a configuration explanatory view of another specific example of applying the stepped-down voltage of FIG. 1;

FIG. 4 is a configuration explanatory view of still another specific example of applying the stepped-down voltage of FIG. 1;

FIG. 5 is an explanatory diagram of an example of a memory block in FIG. 1;

FIG. 6 is an explanatory diagram of the operation in FIG. 5;

FIG. 7 is an explanatory diagram of polarization characteristics of a ferroelectric substance with respect to application of a voltage.

FIG. 8 is a diagram showing the relationship between the time for screening a ferroelectric memory and the occurrence of defective products.

FIG. 9 is a diagram showing a change in polarization after a ferroelectric capacitor is held at a high temperature.

FIG. 10 is a block diagram illustrating an example in which a conventional semiconductor memory is provided with a low-voltage monitoring block that inhibits writing when a power supply voltage drops, and illustrates a relationship between a set voltage and an operating voltage.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Step-down part 2 Selection part 3 Bypass part 5 Memory block 6 Power supply terminal 7 Transformation part 8 Low voltage monitoring block

Claims (4)

[Claims] 1. A power supply terminal, a memory block, a low-voltage monitoring block that monitors a decrease in voltage applied to the power supply terminal, and stops supply of a voltage to the memory block when the voltage is lower than a predetermined voltage. A non-volatile semiconductor memory, comprising: a step-down unit that steps down a voltage; and a transformer that switches and supplies the power supply voltage or the stepped-down voltage to the memory block according to a control input. 2. The step-down unit includes a step-down unit and a power supply voltage bypass unit connected in parallel via a selection unit, and outputs a voltage of the step-down unit or the bypass unit according to the control input. The nonvolatile semiconductor memory according to claim 1, wherein the nonvolatile semiconductor memory has a structure. 3. The nonvolatile semiconductor memory according to claim 1, wherein said step-down unit is formed by a connection structure of a transistor or a diode. 4. The memory block has a ferroelectric capacitor and a MOS transistor connected in series between a plate line and a bit line, and a word line connected to a gate of the MOS transistor and the MOS transistor. 4. The nonvolatile semiconductor memory according to claim 1, wherein the voltage of said step-down unit is selectively applied to at least one of said plate lines.