JP2004022067A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of discriminating the abnormality on a high voltage generating circuit side or the abnormality on a non-volatile memory side and of detecting the defective state such as leakage within the non-volatile memory. <P>SOLUTION: The semiconductor device having the non-volatile memory using a high voltage in rewriting of data and the high voltage generating circuit for supplying the high voltage thereto is provided with a voltage discriminating means for deciding the voltage value of the high voltage supplied to the non-volatile memory and discriminates and decides the abnormality of the high voltage generating circuit and the non-volatile memory. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a high voltage generating circuit, and more particularly to a semiconductor device having a high voltage generating circuit and a nonvolatile memory such as an EEPROM to which the generated high voltage is supplied.
[0002]
[Prior art]
2. Description of the Related Art A non-volatile memory such as an electrically programmable EEPROM requires a voltage (for example, 16 V) higher than a power supply voltage (for example, 3 V) of a semiconductor device in which the data is to be rewritten. Usually, this high voltage is obtained by boosting the power supply voltage by a high voltage generation circuit provided in the semiconductor device.
[0003]
Conventionally, the high voltage from this high voltage generating circuit has not been independently tested for its voltage value, but instead has been used for testing whether a memory cell of a nonvolatile memory can be programmed and erased as instructed. For this reason, even if the test result is obtained as good or bad, if the test result is bad, it cannot be determined whether it is due to an abnormality in the high voltage generation circuit or an abnormality in the memory cell.
[0004]
In general, in the inspection of the nonvolatile memory, the inspection is sequentially performed in units of a memory cell group within a predetermined range. At this time, all the memory cell groups are uniformly erased “1” or written “0” ( In the case of 1 word and 16 bits, 0 (H) or F (H) is performed), and the erase / write result is often determined. In addition, the inspection of the memory cell group is not performed uniformly, but may take a long time depending on the combination, but may be performed randomly.
[0005]
[Problems to be solved by the invention]
However, when a predetermined memory cell group is uniformly erased or written, the voltages applied to the memory cells in the memory cell group and the corresponding portions of peripheral circuits such as decoders simultaneously change. . Therefore, even if, for example, a leak location exists between the memory cells or between the corresponding locations, there is a problem that it cannot be detected in this inspection.
[0006]
In addition, when a predetermined memory cell group is randomly erased or written, a leak actually occurs at a leak location existing between memory cells or between corresponding locations. Erasing or writing may be performed as instructed. However, in such a case, even if erasing or writing is performed as instructed, the threshold value Vth of the memory cell often does not change to a predetermined value (for example, 0V → 5V). , Which was the cause of failure after shipment to the market.
[0007]
Therefore, the present invention provides a semiconductor device that can determine whether an abnormality is occurring on the high voltage generation circuit side or an abnormality on the non-volatile memory side and detect a faulty state such as a leak inside the non-volatile memory. The purpose is to do.
[0008]
[Means for Solving the Problems]
2. The semiconductor device according to claim 1, including a memory cell array and a decoder, a nonvolatile memory unit that uses a high voltage when rewriting data, and a power supply voltage boosted to generate the high voltage and supply the generated high voltage to the nonvolatile memory unit. A high voltage generating means and a voltage determining means for comparing a voltage corresponding to the high voltage supplied to the nonvolatile memory means with a predetermined voltage are provided.
[0009]
According to the present invention, since the voltage value of the high voltage supplied to the nonvolatile memory means is determined, the semiconductor device is inspected by separating and inspecting the high voltage generation means side and the nonvolatile memory means side when inspecting the semiconductor device. It is possible to distinguish and determine whether the generated abnormality is an abnormality on the high voltage generation unit side or an abnormality on the nonvolatile memory unit side.
[0010]
Also, by determining the value of the high voltage supplied to the nonvolatile memory means while randomly rewriting a predetermined memory cell group, it is possible to detect the occurrence of a leak on the nonvolatile memory means side regardless of the rewriting result. can do.
[0011]
In addition, since it is not necessary to output the generated high voltage to the outside, an external terminal for the high voltage is not required, and the capability of the high voltage generating means does not need to be increased beyond the originally required amount.
[0012]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an embodiment of a semiconductor device having a high-voltage generation circuit according to the present invention will be described with reference to the drawings.
[0013]
FIG. 1 is an overall configuration diagram of a semiconductor device 100 according to a first embodiment of the present invention, and FIGS. 2 and 3 are diagrams illustrating an operation flow thereof.
[0014]
In FIG. 1, a power supply voltage Vcc (for example, 3 V) is supplied from an external terminal T1 of the semiconductor device 100. The high voltage generation circuit 20 includes a booster circuit such as a charge pump circuit, and boosts a supplied power supply voltage Vcc to generate a predetermined high voltage Vpp (for example, 16 V).
[0015]
The non-volatile memory 10 is an EEPROM, a flash memory, or the like, to which the power supply voltage Vcc and the high voltage Vpp are supplied, and to which various control signals CONT including an inspection signal are supplied. The nonvolatile memory 10 includes a memory cell array 11 in which memory cells are arranged in m rows and n columns, a row decoder 12 for selecting a row, a column decoder 13 for selecting a column, a sense amplifier 14 for detecting data, and input / output of data. It includes an input / output circuit 15, a control circuit 16 for controlling these, and the like.
[0016]
The control of erasing, writing, and reading of the memory cell array 11 is performed for each predetermined memory cell group specified by the row decoder 12 and the column decoder 13. At the time of erasing or writing, that is, rewriting, the high voltage Vpp is applied to the memory cell array 11, the row decoder 12, the column decoder 13, and the like.
[0017]
In the present invention, there is provided a voltage determining means for inspecting (or monitoring) the high voltage Vpp generated by the high voltage generating circuit 20 and supplied to the nonvolatile memory 10 and determining the voltage value.
[0018]
The voltage determining means includes a resistor divider 30 for dividing the voltage between the high voltage Vpp and the ground into the resistance value R1 and the resistance value R2, and a P for preventing the current consumption from being generated by the resistor divider 30 when not operating. A type MOS transistor Q1 is provided. Thus, the subsequent circuits can be operated at the normal power supply voltage Vcc. The divided voltage Vp extracted from the resistor voltage divider 30 is input to one input (+) of the comparator OP1. The reference voltage Vref supplied to the external terminal T2 is input to the other input (-) of the comparator OP1 via the P-type MOS transistor Q2. The test signal Test is applied to the gates of the transistors Q1 and Q2 via the inverting circuits NOT1 and NOT2, respectively. Note that the inverting circuit NOT1 also functions as a level shift circuit. Further, the transistors Q1 and Q2 may be analog switches. Further, the operation of the comparator OP1 may be controlled by the test signal Test.
[0019]
When the test signal Test goes high, the transistors Q1 and Q2 are turned on, and the divided voltage Vp and the reference voltage Vref are input to the comparator OP1. Since the divided voltage Vp is Vpp × R2 / (R1 + R2), if the resistance R1 is 3 MΩ and the resistance R2 is 1 MΩ, the reference voltage Vref is set to 4 V in order to check that the high voltage Vpp is 16 V or more. do it. Of course, since the high voltage Vpp from the high voltage generation circuit 20 slightly decreases due to the driving of the nonvolatile memory 10, the high voltage Vpp is set in consideration of the reduced amount as a margin. As a result, the judgment output of the comparator OP1 goes to the H level when the high voltage Vpp is equal to or higher than 16V, and goes to the L level when the high voltage Vpp is lower than 16V.
[0020]
Next, the inspection operation of the semiconductor device of FIG. 1 configured as described above will be described with reference to the flowcharts of FIGS.
[0021]
First, in FIG. 2, when the test is started (started), in step S101, the inspection signal Test is set to the H level, and Q1 and Q2 are turned on. At this stage, the purpose is only to test the high voltage generation circuit 20, and the nonvolatile memory 10 is not driven.
[0022]
In step S102, the divided voltage Vp and the reference voltage Vref are compared by the comparator OP1. When the comparison result of the comparator OP1 is at the L level, the predetermined high voltage Vpp has not been generated from the high voltage generation circuit 20. Therefore, in step S103, it is determined that the high voltage generation circuit 20 is abnormal, and the process ends abnormally. At the time of the abnormal termination, the test device may generate a required control signal such as an alarm or a display, or perform a repair operation for a defective portion, based on the L level of the determination output from the comparator OP1. On the other hand, when the comparison result of the comparator OP1 is at the H level, since the predetermined high voltage Vpp has been generated from the high voltage generation circuit 20, the operation proceeds to the inspection of the nonvolatile memory 10.
[0023]
In step S104, the data contents of a predetermined memory cell group specified by the decoders 12 and 13 are sequentially erased uniformly.
[0024]
Whether or not each memory cell of the memory cell group has been erased as a result of this erasure is separately monitored. When a memory cell that has not been erased is found by this monitor, the memory cell group is determined to be abnormal, and at least the memory cell group is treated so as not to be used. Note that the memory cell group determined to be abnormal includes the memory cell group itself and peripheral circuits such as a decoder related to the memory cell group (hereinafter the same). This uniform erasure monitoring and processing is similarly applied to uniform writing and random rewriting.
[0025]
If the comparison result of the comparator OP1 is at L level in step S105, it means that the high voltage of the high voltage generation circuit 20 determined to be normal in step S102 has been reduced by driving the memory cell group. In S106, the memory cell group is determined to be abnormal, at least the memory cell group is treated so as not to be used, and the process ends abnormally.
[0026]
Note that when it is determined in step S106 that the memory cell group is abnormal, the inspection flow may not be terminated but the inspection of the next memory cell group may be performed. For this purpose, it is sufficient that the flow proceeds to step S104 after the abnormality is determined in step S106. The processing flow after the abnormality determination can be similarly applied to other abnormality determination steps (including other embodiments).
[0027]
In step S107, the memory cell group uniformly erased in step S104 is uniformly written. When the comparison result of the comparator OP1 is at the L level in step S108, the memory cell group is again determined to be abnormal in step S106, and at least the memory cell group is treated so as not to be used, and abnormal termination is performed. I do.
[0028]
In step S108, when the comparison result of the comparator OP1 is at the H level, the memory cell group is determined to be normal in the uniform rewrite (ie, erase and write) inspection.
[0029]
In step S109, it is determined whether or not the processing in steps S104 to S108 has been performed for all the memory cell groups. When the uniform rewrite inspection has been completed for all the memory cell groups, the flow shifts to the flowchart of FIG.
[0030]
In the flow of FIG. 3, rewriting (that is, erasing / writing) is performed with a required type of random pattern for each memory cell group.
[0031]
In step S110, a certain memory cell group is rewritten with an arbitrary random pattern.
[0032]
In the rewriting with the random pattern, unlike the case of uniform writing and erasing, when a leak or the like occurs between adjacent memory cells or wiring of a corresponding peripheral circuit, the data is supplied to the nonvolatile memory 10. The voltage value of the high voltage Vpp decreases.
[0033]
When the voltage value of the high voltage Vpp decreases, the rewriting operation of the memory cell is not completely performed. As a result, even if the data is rewritten, the threshold voltage Vth of the memory cell at that time should be rewritten from 0 V to 5 V when the memory cell is normal, but the state is changed from 0 V to 3 V, for example.
[0034]
Conventionally, in this case, even if the rewrite result is separately monitored, as a result, it is recognized that each memory cell of the memory cell group has been normally rewritten. It cannot be found.
[0035]
In the present invention, the comparison result of the comparator OP1 is determined in step S111. Then, when the comparison result is at the L level, it is determined in step S112 that the memory cell group is abnormal due to leakage or the like, and at least the memory cell group is treated so as not to be used, and the process ends abnormally.
[0036]
In step S113, it is determined whether or not the memory cell group has been rewritten with a required type of random pattern, and an inspection of rewriting with the required type of random pattern is performed.
[0037]
In step S114, the processes in steps S110 to S113 are performed for all the memory cell groups, and the process ends. In this case, it is determined that both the high voltage generation circuit 20 and the nonvolatile memory 10 are normal.
[0038]
As described above, since the voltage value of the high voltage Vpp supplied to the nonvolatile memory 10 is determined, when the semiconductor device 100 is tested, the high voltage generation circuit 20 and the nonvolatile memory 10 are separated and tested. In addition, it is possible to distinguish and determine whether the abnormality that has occurred in the semiconductor device 100 is an abnormality on the high voltage generation circuit 20 side or an abnormality on the nonvolatile memory 10 side.
[0039]
Further, since the voltage value of the high voltage Vpp supplied to the nonvolatile memory 10 is determined while randomly rewriting a predetermined memory cell group, regardless of the rewriting result of each memory cell, Leak occurrence can be detected.
[0040]
FIG. 4 is an overall configuration diagram of a semiconductor device 200 according to the second embodiment of the present invention, and FIGS. 5 to 7 are diagrams illustrating an operation flow thereof.
[0041]
4, the semiconductor device 200 is different from the semiconductor device of FIG. 1 in that the resistance voltage divider 30 is of a variable type capable of changing its voltage division ratio, and a selector 40 for changing the voltage division ratio is provided. The difference is that the reference voltage generation circuit 50 for generating the reference voltage Vref is provided, and the reference voltage generation circuit 50 and the comparator OP1 are controlled by the test signal Test. Further, the transistor Q2 and the inverting circuit NOT2 are omitted. The other points are the same as those in FIG. 1, and thus different points will be described.
[0042]
The resistance voltage divider 30 is configured to be able to change the voltage division ratio based on the resistance values R1 and R2. For this purpose, for example, a large number of resistors may be connected in series, wires may be drawn out from the many connection points for voltage extraction, and the divided voltage Vp may be obtained from one of the drawn wires.
[0043]
The selector 40 is configured to select one of a number of lead wires from the resistor voltage divider 30 to be connected to the input terminal of the comparator OP1, and to supply the divided voltage Vp. More specifically, the reversible shift register is used to switch between an upward (right) shift and a downward (left) shift according to the output “H level” or “L level” of the comparator OP1 to shift the select position to an arbitrary direction. Can be shifted to Which voltage of the extraction wiring is selected as the divided voltage Vp is determined by changing the selection position of the selector 40 according to the output of the comparator OP1. The selected position selected by the selector 40 indicates the voltage value of the high voltage Vpp in relation to the reference voltage Vref (Vpp ≒ Vref × (R1 + R2) / R2). In such a manner that the voltage value of the high voltage Vpp can be obtained.
[0044]
The reference voltage generation circuit 50 generates the reference voltage Vref inside the semiconductor device 200. For example, by using a bandgap type constant voltage circuit, a reference voltage that is hardly affected by temperature or the like can be obtained. In this case, an external terminal for the reference voltage Vref becomes unnecessary.
[0045]
Next, the inspection operation of the semiconductor device of FIG. 4 configured as described above will be described with reference to the flowcharts of FIGS.
[0046]
First, referring to FIG. 5, when started, in step S201, the inspection signal Test is set to the H level, the transistor Q1 is turned on, and the reference voltage generation circuit 50 is controlled to generate the reference voltage Vref. OP1 is operated. At this stage, the purpose is only to test the high voltage generation circuit 20, and the nonvolatile memory 10 is not driven.
[0047]
In step S202, the selected divided voltage Vp and the reference voltage Vref are compared by the comparator OP1.
[0048]
If the output of the comparator OP1 is at the H level in step S202, the select position of the selector 40 is lowered by one tap in step S203 in order to check the voltage value because the high voltage Vpp is high. Then, in step S204, the output of the comparator OP1 is determined again. When the output is at the H level, the select position of the selector 40 is further lowered by one tap. This process is repeated until the output of the comparator OP1 becomes L level in step S204. When the L level is reached, the select position is raised by one tap in step S205.
[0049]
Then, in step S206, the value of the high voltage Vpp is obtained by calculation based on the select position and the reference voltage Vref. Then, it is determined whether the obtained high voltage Vpp is within an allowable value. If the high voltage Vpp is outside the allowable value range (in this case, it is detected that it is higher than the predetermined value), it is determined in step S207 that the high voltage generation circuit 20 is abnormal, and the process ends abnormally. If the high voltage Vpp is within the allowable value range, the value of the high voltage Vpp is stored in step S208.
[0050]
On the other hand, when the output of the comparator OP1 is at the L level in step S202, the select position of the selector 40 is raised by one tap in step S209 to check the voltage value because the high voltage Vpp is low. Then, in step S210, the output of the comparator OP1 is determined again. When the output is at the L level, the select position of the selector 40 is further lowered by one tap. This processing is repeated until the output of the comparator OP1 becomes H level in step S210.
[0051]
Then, in step S211, the value of the high voltage Vpp is obtained by calculation based on the select position and the reference voltage Vref. It is determined whether the obtained high voltage Vpp is within an allowable value. If the high voltage Vpp is out of the allowable value range (in this case, it is detected that it is lower than the predetermined value), it is determined in step S207 that the high voltage generation circuit 20 is abnormal, and the process ends abnormally. If the high voltage Vpp is within the allowable value range, the value of the high voltage Vpp is stored in step S208.
[0052]
When the selection position of the selector 40 starts from the highest position, steps S209 to S211 can be omitted in the flow of FIG. Conversely, when the selection position of the selector 40 starts from the lowest position, steps S203 to S206 can be omitted in the flow of FIG.
[0053]
When the value of the high voltage Vpp in the high voltage generation circuit 20 alone is obtained, the flow shifts to the flowchart of FIG.
[0054]
In the flow of FIG. 6, uniform rewriting (that is, erasing and writing) is performed for each memory cell group. The flow in FIG. 6 is the same as Steps S104 to S109 in FIG. When the steps correspond to each other, step S220 corresponds to step S104, step S221 corresponds to step S105, step S222 corresponds to step S106, step S223 corresponds to step S107, step S224 corresponds to step S108, and step S225 corresponds to step S109. Accordingly, when the uniform rewrite inspection for all the memory cell groups is completed in step S225, the process proceeds to the flowchart of FIG.
[0055]
In the flow of FIG. 7, rewriting (that is, erasing / writing) is performed with a required type of random pattern for each memory cell group. The flow of FIG. 7 is similar to steps S110 to S114 of FIG. When the steps correspond to each other, step S231 corresponds to step S110, step S232 corresponds to step S111, step S233 corresponds to step S112, step S234 corresponds to step S113, and step S235 corresponds to step S114. In step S235, when the processing is performed for all the memory cell groups and the processing is completed, it is determined that both the high voltage generation circuit 20 and the nonvolatile memory 10 are normal.
[0056]
In the flowcharts of FIGS. 6 and 7, when the comparison result of the comparator OP1 is at the L level in steps S221, S224, and S232, the memory cell group is immediately determined to be abnormal in steps S222 and S233. Has been determined.
[0057]
However, in the second embodiment, since the divided voltage Vp can be changed according to the selected position of the selector 40, it is possible to determine how low the high voltage Vpp is when it is low. As a representative of this determination method, step S233 will be described with reference to the flowchart of FIG.
[0058]
It is assumed that the output of the comparator OP1 becomes L level in step S232. In this case, first, in step S301, the select position of the selector 40 is raised by one tap. As a result, the divided voltage Vp increases by one tap, and in this state, the output of the comparator OP1 is determined again in step S302.
[0059]
If the determination in step S302 is at the H level, it has been found that the voltage drop of the high voltage Vpp is within one tap, and in this case, it can be determined that the memory cell group is not abnormal.
[0060]
If the determination in step S302 is also at the L level, the voltage drop of the high voltage Vpp is large. In this case, the memory cell group is determined to be abnormal (S233), and the process ends abnormally.
[0061]
Regardless of which judgment is made, it is necessary to lower the select position by one tap and return to the original position in step S303 in order to inspect the next memory cell group.
[0062]
The determination method of FIG. 8 is not limited to one tap, and can be adopted over two or more taps. Further, the high voltage Vpp, which is a boosted voltage, may be adjusted based on the result.
[0063]
As described above, in the second embodiment, the voltage divider 30 is of a variable voltage dividing ratio type, and the voltage dividing ratio is changed by the output of the comparator OP1. Further, a selector 40 is provided for changing the voltage dividing ratio of the voltage divider 30 by the output of the comparator OP1 and outputting the changed selected position (that is, the selected position). As a result, the selector 40 changes the voltage dividing ratio of the voltage divider 30 so that the divided voltage Vp matches the reference voltage Vref, so that the high voltage Vpp supplied to the non-volatile memory 10 depends on the selected position of the selector 40. You can know the voltage value. Therefore, the determination of normal or abnormal can be performed with higher accuracy.
[0064]
In each of the embodiments, when the test signal Test is applied, the high voltage Vpp is compared with the reference voltage Vref. However, the comparison of the high voltage Vpp may be performed at all times. You may make it perform it. As described above, by monitoring the high voltage Vpp other than at the time of the inspection, it is possible to detect the deterioration of the nonvolatile memory in actual use.
[0065]
【The invention's effect】
According to the present invention, since the voltage value of the high voltage supplied to the nonvolatile memory means is determined, the semiconductor device is inspected by separating and inspecting the high voltage generating means side and the nonvolatile memory means side when inspecting the semiconductor device. It is possible to distinguish and determine whether the generated abnormality is an abnormality on the high voltage generation unit side or an abnormality on the nonvolatile memory unit side.
[0066]
Also, by determining the value of the high voltage supplied to the nonvolatile memory means while randomly rewriting a predetermined memory cell group, it is possible to detect the occurrence of a leak on the nonvolatile memory means side regardless of the rewriting result. can do.
[0067]
In addition, since it is not necessary to output the generated high voltage to the outside, an external terminal for the high voltage is not required, and it is not necessary to increase the capability of the high voltage generating means beyond the originally required amount.
[Brief description of the drawings]
FIG. 1 is an overall configuration diagram of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a diagram showing an operation flow of FIG. 1;
FIG. 3 is a diagram showing an operation flow of FIG. 1;
FIG. 4 is an overall configuration diagram of a semiconductor device according to a second embodiment of the present invention.
FIG. 5 is a diagram showing an operation flow of FIG. 4;
FIG. 6 is a diagram showing an operation flow of FIG. 4;
FIG. 7 is a view showing the operation flow of FIG. 4;
FIG. 8 is a diagram showing a modification of the operation flow of FIGS. 6 and 7;
[Explanation of symbols]
100, 200 Semiconductor device 10 Nonvolatile memory 11 Memory cell array 12 Row decoder 13 Column decoder 14 Sense amplifier 15 Input / output circuit 16 Control circuit 20 High voltage generation circuit 30 Resistive voltage divider 40 Selector 50 Reference voltage generation circuit OP1 Comparator Q1, Q2 MOS transistor Vpp High voltage Vp Divided voltage Vref Reference voltage Test Test signal

Claims (1)

A nonvolatile memory means including a memory cell array and a decoder, and using a high voltage when rewriting data;
High voltage generating means for raising the power supply voltage to generate the high voltage and supplying the high voltage to the nonvolatile memory means;
A semiconductor device comprising: a voltage determination unit that compares a voltage corresponding to a high voltage supplied to the nonvolatile memory unit with a predetermined voltage.

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