JPH11337600A - Measuring device for time width distribution - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a highly accurate measurement of time width distribution from a short time width to a wide time width with a little memory capacity. SOLUTION: In this measuring device, an analog signal of an object to be measured is converted into a digital signal S' by an A/D converter 21, and time when the digital signal S' is a threshold value X or more is measured by counting a clock signal by a binary counter 23, the counted result of 32 bit of the binary counter 23 is converted into a floating point system data comprising a mantissa portion of 3 bit and an exponent portion of 5 bit by a floating point circuit 30; and an address of a memory 26 is designed bye the floating point system data and a frequency data read out is renewed by one by a frequency renewal circuit 27.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for measuring a pulse width distribution and a pulse interval distribution as one measure for statistically evaluating an electromagnetic environment. About.

[0002]

2. Description of the Related Art When evaluating the influence of electromagnetic interference on communication and broadcasting, amplitude probability distribution (APD), which is a basic characteristic in the amplitude domain, and intersection, which is a basic characteristic in the time domain, are used as statistical parameters of the interference. In addition to the rate distribution (CRD), characteristics of a pulse width distribution (PDD) and a pulse interval distribution (PSD) are important factors.

[0003] The pulse width distribution is defined as a probability distribution of a time when an analog signal to be measured (for example, a short line signal such as an interference wave) exceeds a predetermined threshold value within a predetermined measurement time, and a pulse interval distribution. Is defined as a probability distribution of the time when the analog signal to be measured is lower than a predetermined threshold value within a predetermined measurement time, contrary to the pulse width distribution.

[0004] Since these are both probability distributions of the time width from when a signal crosses a threshold value to when it crosses next, they are collectively referred to as a time width distribution in the following description.

In order to measure such a time width distribution,
Conventionally, a time width distribution measuring device 10 shown in FIG. 10 has been used.

This time width distribution measuring device 10 converts an analog signal S input from an input terminal 10a into an A / D converter 1.
The signal is converted into a digital signal S 'by 1 and input to the digital comparator 12.

The digital comparator 12 compares the input signal S 'with a predetermined threshold value X. When the input signal S' is equal to or higher than the threshold value X, the digital comparator 12 outputs a high level (hereinafter, referred to as H level) signal by two. Output to the binary counter 13, and when the input signal S 'is smaller than the threshold value X,
(Referred to as L level) is output to the binary counter 13.

The binary counter 13 counts the clock signal C output from the clock signal generator 14 while receiving the H level signal from the digital comparator 12, and outputs a reset signal R from the timing controller 15.
Upon receipt, the count value is reset to zero. The cycle of the clock signal C is set to a unit time such as 1 millisecond.

The timing controller 15 outputs a write enable signal W to the memory 16 immediately after the output of the digital comparator 12 changes from the H level to the L level, and immediately thereafter outputs the reset signal R to the binary counter 13. Output.

Therefore, the count result immediately before the binary counter 13 is reset indicates a time when the analog signal S to be measured is equal to or longer than the predetermined threshold value X.

The memory 16 receives the count output of the binary counter 13 as an address signal, outputs data at an address designated by the address signal to the frequency update circuit 17 as frequency data, and outputs a write enable signal from the timing controller 15. When receiving W, the original frequency data is updated with the frequency data from the frequency updating circuit 17.

The frequency update circuit 17 adds 1 to the frequency data from the memory 16 and outputs the frequency data updated and added to the memory 16.

Next, the operation of the time width distribution measuring device 10 will be described. Binary counter 13 and memory 16
Is reset to zero, the analog signal S shown in FIG. 11A is input during the measurement time T, converted into a digital signal S ', and input to the digital comparator 12.

As shown in FIG. 11B, the output of the digital comparator 12 crosses the threshold value X in the negative direction from the time t _{1 at} which the digital signal S ′ crosses the threshold value X in the positive direction. The H level is maintained until time t _2, and the time width T ₁ of the H level period is measured by the binary counter 13.

When the output of the digital comparator 12 changes to L level at time t ₂ , a write enable signal W is output to the memory 16 as shown in FIG.

Therefore, the value of the frequency data D (T ₁ ) at the address specified by the time width data T ₁ (in this case, the initial value is zero) is increased and updated by 1 as shown in FIG. You.

Immediately after the write enable signal W, FIG.
As in the (d), the reset signal R is output to the binary counter 13, and the count in the next H level time width T _2.

In the same manner, the measurement of the time widths T ₁ , T ₂ ,..., T _n of each H level period and the update of the frequency data corresponding to the time widths are continuously performed during the measurement time T. .

For this reason, after the measurement time T is completed, the frequency for each time width is stored in the memory 16, and this frequency data is read out from the memory 16 by a processing device (not shown) and transmitted to the display device. If shown, the time width distribution characteristics (in this case, the pulse width distribution characteristics) of the analog signal S to be measured can be evaluated.

The above measurement and frequency data are updated with respect to the time width T ₁ ′ to T _n−1 ′ of the L level period in which the digital signal S ′ is smaller than the threshold value X, so that the pulse interval is The distribution can also be measured.

[0021]

However, in the above-mentioned conventional time width distribution measuring apparatus, a great problem arises if the range of the time width measured with a small memory capacity is widened.

That is, the maximum address value of the memory 16 is set to 2 ^L
If the measurement resolution (the period of the clock signal C) is Δτ, the time width that can be measured is Δτ to Δτ · (2 ^L −1)
In order to extend the range of the time width without increasing the memory capacity, the minimum measurable time width Δτ must be increased.

However, if the measurable minimum time width Δτ is increased, it becomes impossible to measure a short-width pulse or a pulse interval generated instantaneously.

It is an object of the present invention to solve this problem and to provide a time width distribution measuring apparatus capable of performing measurement from a short time width to a wide time width with high accuracy with a small memory capacity.

[0025]

According to a first aspect of the present invention, there is provided a time width distribution measuring apparatus, comprising: a comparator for comparing an analog signal to be measured with a predetermined threshold; While receiving the comparison output of the comparator, while the comparison output is at one level, the clock signal of a predetermined cycle is counted, and the counting result is expressed as time width data of the analog signal with respect to the threshold by a predetermined number of bits L. A binary counter to be output, and the L-bit counting result output from the binary counter during a predetermined measurement period is converted into a floating-point format having a smaller number of significant digits than the L-bit, and the exponent part of the I-bit is converted. And a J-bit mantissa part, and outputs a (I + J) -bit signal in sequence, and the floating-point conversion circuit outputs (I + J)
A bit signal as an address signal, a memory for reading data stored at an address specified by the address signal, and a data read from the memory,
An update circuit for updating the address of the data to data representing a designated frequency.

According to a second aspect of the present invention, there is provided the time width distribution measuring device according to the first aspect, wherein the floating-point conversion circuit includes: A digit position detection circuit that detects the most significant digit position that has been incremented during counting, and an exponent part conversion circuit that outputs the exponent part of the I bit based on the digit position detected by the digit position detection circuit, Based on the digit position detected by the digit position detection circuit, of the L bit count results, the lower J
A mantissa selection circuit for selectively outputting bit data as the mantissa.

According to a third aspect of the present invention, there is provided the time width distribution measuring device according to the second aspect, wherein the digit position detecting circuit is configured to output the least significant bit of the L-bit count output of the binary counter. The count output of (L-1) bits excluding lower-order bits is received by (L-1) flip-flops for each bit, and 1-bit data is latched for the digit advanced during counting, and The latch data of the (L-1) flip-flops when the counting by the binary counter is completed is
The value corresponding to the highest digit position advanced during the counting (L-
1) The exponent part conversion circuit is configured to output as a bit signal, and the exponent part conversion circuit receives the (L-1) bit signal output from the digit position detection circuit as a selection signal and outputs the I L: 1: 2 signals. The exponent part of the I-bit is output by a branch tree multiplexer, and the mantissa selection circuit receives J (L-1) -bit signals output from the digit position detection circuit as selection signals. The J-bit data is selectively output as a mantissa from the count result of the binary counter by an L: 1 binary tree multiplexer.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a time width distribution measuring device 20 according to an embodiment of the present invention.

The portion for measuring the time width of the time width distribution measuring device 20 has the same configuration as that of the conventional time width distribution measuring device 10 described above.

That is, the analog signal S input from the input terminal 20a is converted into a digital signal S 'by the A / D converter 21 and input to the digital comparator 22.

The digital comparator 22 compares the digital signal S 'with a predetermined threshold value X. When the digital signal S' is equal to or larger than the threshold value X, it outputs an H level signal to the binary counter 23, When the signal S ′ is smaller than the threshold value X, an L level signal is output to the binary counter 23.

Although the analog signal S is converted into a digital signal and compared with the threshold value X here, the analog signal S may be compared with the threshold voltage X by an analog comparator. Good.

The binary counter 23 has a count output of, for example, 32 bits (L = 32), and receives a clock output from the clock signal generator 24 while receiving the H level signal from the digital comparator 22. After counting the signal C and receiving a reset write signal RW from the timing controller 25, the count value is reset to zero. The cycle of the clock signal C is set to a unit time such as 1 millisecond or 1 microsecond.

The timing controller 25 outputs a hold signal H to a floating-point conversion circuit 30 described later immediately after the output of the digital comparator 22 changes from H level to L level, and immediately thereafter, a reset write signal R
W is output to the binary counter 23, the memory 26, and the floating-point conversion circuit 30. The operation of the timing controller 25 is such that the hold signal H is output instead of the reset signal R and the reset write signal RW is output instead of the write enable signal W in the timing chart of FIG.

Accordingly, the count result immediately before the binary counter 23 is reset indicates that the analog signal S to be measured has a time width equal to or larger than the predetermined threshold value X.

The count output of the binary counter 23 is input to the floating point conversion circuit 30. The floating-point conversion circuit 30
The 32-bit fixed-point count output n of the binary counter 23 is converted into a 5-bit (I = 5) exponent part and a 3-bit (J =
The data is converted to the floating-point format of the mantissa of 3), and an 8-bit signal including the exponent and the mantissa is output to the memory 26. The details of the floating-point conversion circuit 30 will be described later.

The memory 26 receives an 8-bit signal output from the floating-point conversion circuit 30 as an address signal,
The frequency data at the address specified by the address signal is output to the frequency update circuit 27,
When receiving the reset write signal RW from No. 5, the frequency data output from the frequency updating circuit 27 is stored at the address of the original frequency data.

The frequency updating circuit 27 adds 1 to the frequency data read from the memory 26 and outputs the result to the memory 26, and updates the frequency data in the memory 26 so as to indicate the designated frequency of the address.

The frequency data stored in the memory 26 during the predetermined measurement time is read out by the frequency data processing means 28. For example, the horizontal axis represents the time width (pulse width), and the vertical axis represents the frequency display device 29. Is displayed on the coordinate screen. From this display, the pulse width distribution of the analog signal S to be measured can be grasped.

In the time width distribution measuring device 20 having the above configuration,
Since the address of the memory 26 is specified by the floating-point conversion circuit 30 using an address signal that changes by 32 octaves (5 bits) with a fineness of 8 points (3 bits) per octave, the capacity is as small as 8 bits. Can measure the time width (pulse width) in the range of 1 · Δτ to (2 ³² −1) · Δτ. For example,
If Δτ is set to 20 nanoseconds, a maximum time width (pulse width) of 85 seconds can be measured.

The digital comparator 22 outputs an L level signal to the binary counter 23 when the digital signal S 'is equal to or larger than the threshold value X, and outputs the digital signal S'
Is output to the binary counter 23 when is smaller than the threshold X, the pulse interval distribution of the analog signal to be measured can be measured.

Next, details of the floating-point conversion circuit 30 will be described. Binary numbers are represented as A × 2 ^{B in} floating point format. Here, A is a mantissa part, and B is an exponent part.

For example, to express a 32-bit binary number n in a fixed-point format in a floating-point format, 5 bits (32 = 2 ⁵ ) are required as an exponent part B. In order to express the data with 8 bits in total, the mantissa part A has 3 bits.

Next, a method of converting a fixed-point L-bit binary number n into a floating-point format will be described.

An L-bit binary number n [QL _-1, QL _-2 ,...
, Q ₂ , Q ₁ , Q ₀ ] is n = (Q ₀ · 2 ⁰ ) + (Q ₁ · 2 ¹ ) +... + (Q _L−1 · 2 ^L−1 ) = Σ ₁ (Q _i · 2 ⁱ ). Here, Σ ₁ represents the sum of i = 0 to L−1, and Q _i is a coefficient of 0 or 1.

Here, the exponent part B is a value satisfying 2 ^B ≦ n <2 ^{B + 1} among the integers in the range of 0 to L−1, and this number B is 1 in bit data. This is one less than the most significant digit value.

For example, when L is 32, the binary number n is [0
0001 *** ... ***], the highest 1 is 28
If in the bit, n is in the range 2 ²⁷ ≦ n <2 ²⁸ and B is 27 (* is any value of 0 or 1).

When the value of the binary number n is represented using this number B, n = 2 ^B + Σ ₂ (Q _i · 2 ⁱ ) = 2 ^B [1 + Σ ₃ (Q
_Bi・ 2 ^-i )]. However, sigma ₂ represents the sum of up to i = 0~B-1, Σ ₃ represents the sum of up to i = 1~∞.

When the binary number n is represented in a floating-point format, the number of significant digits is 4 bits, that is, up to 3 bits of Q _B-1 , Q _B-2 and Q _B-3 following the most significant 1; The binary value m when ignoring the lower order is m = ^2B + QB _- ^1-12B-1 + QB _-2・^2B-1 + QB _-3・^2B-3 = ^2B [ 1 + Q _B-1 · 2 ^-1 + Q _B− ²⁻² + Q _B− 3−2 ^-3 ] = 2 ^B [1+ (Q _B−1 · 2 ² + Q _B− 2 ¹ + Q _B−3. 2 ⁰ ) / 2 ³ ].

[0050] Here, when ^{_{M = Q B-1 · 2}} 2 + Q B-2 · 2 1 + Q B-3 · 2 0, the value m is, m = [1+ (M / 8)] × 2 ^B It is expressed as

When the above expression is compared with the general expression A × 2 ^B in the floating-point format, the mantissa part A is A = 1 + (M / 8). Here, the value M is in the range of 0 to 7. Note that the mantissa part A is uniquely determined for this value M,
This value M is a 3-bit mantissa.

That is, in this floating point conversion circuit 30,
Of the 32-bit fixed-point count result n, a value that is one less than the most significant digit value whose bit data is 1 is output as a 5-bit exponent part B, and the lower three bits as a mantissa part M Selectively output from the counting result n.

In order to realize this, the floating-point conversion circuit 30 is provided with a count value latch circuit 3 as shown in FIG.
A digit position detection circuit 32 for detecting the most significant digit position incremented during counting, that is, the most significant digit position where the bit data is 1, among the 1 and 32-bit count results n; An exponent part conversion circuit 35 that outputs a 5-bit exponent based on the digit position detected by the position detection circuit 32, and a 3-bit mantissa from the count output n based on the digit position detected by the digit position detection circuit 32 Significand part selection circuit 37 for selecting and outputting a part
And

The count latch circuit 31 is a binary counter 2
3 is latched and output each time the hold signal H from the timing controller 25 is received.

[0055] digit position detecting circuit 32, for example as shown in FIG. 2, 31 D-type flip-flop 33 _to 333
_31, is constituted by the hold signal is latched for each receiving an H output as the digit signal 31-bit latch circuit 34 from the timing controller 25 outputs of these flip-flops 33 _to 333 _31.

[0056] each of the flip-flop 33 _to 333 _31, 2
Of the 32-bit count output of the binary counter 23, each of the count outputs from the second bit to the 32nd bit excluding the first bit is received at the clock terminal, and the count output is output while the binary counter 23 is counting. When 1 advances from 0 to 1, data of 1 is latched.

For example, the count output of the binary counter 23 is changed from [0000 ... 0000] to [00 ... 01000101].
In this case, all the outputs of the _{first to fifth} flip-flops 331 to 335 become 1, and the latch circuit 34 outputs a digit signal of [00 ... 0011111]. The reset write signal R from each flip-flop 33 _to 333 ₃₁ the timing controller 25
In response to W, the output is reset to 0.

The exponent part conversion circuit 35 and the mantissa part selection circuit 37 provide a 5-bit exponent part based on the count result n latched by the count latch circuit 31 and the digit signal output from the digit position detection circuit 32. And a 3-bit mantissa part, respectively, using a binary tree multiplexer.

Here, the binary tree multiplexer will be briefly described. FIG. 3 shows an 8: 1 binary tree multiplexer, which is composed of seven switches SW _{1 of} one circuit and two contact points.
Used to SW _7, the first two contacts and a second switch SW _1, the third switch SW _2, SW ₃ connected to the second of the two contacts of the switch SW ₂ fourth, fifth SW ₄ , S
Connect the W _5, 6 to the third two contacts of the switch SW _3, the SW _6, SW ₇ of the seventh connected, by a 7-bit selection signals S1 to S7, 8 input ports Pi (0) ~
A selection circuit for connecting any one of P (7) to the output port Po.

Then, all the switches SW _{1 to} SW _1
7 is connected to the right contact when receiving the selection signal of 0,
When the selection signal of 1 is received, it is connected to the setting on the left side, and
As shown in FIG. 3, the selection signals S1 to S7 of 7 bits are set so as to be sequentially applied from the right to the left switch.

In the binary tree multiplexer configured as described above, as shown in FIG. 4A, a 7-bit selection signal [S7, S6,..., S2, S2
1] is [*** 0 * 00], the data of the rightmost first input port Pi (0) is selectively output. The selection signal [S7, S6,..., S2, S1] is [**
* 0 * 01], the second input port Pi
The data of (1) is selectively output. * Mark is 0
Or any number of ones.

Hereinafter, similarly, when the selection signal is [**** 001
*], The data of the third input port Pi (2) is selectively output, and if the selection signal is [**** 011 *], the data of the fourth input port Pi (3) is selectively output. When the selection signal is [* 001 ***], the data of the fifth input port Pi (4) is selectively output, and when the selection signal is [* 011 ***], the sixth input is performed. The data of the port Pi (5) is selectively output, and the selection signal is [0
1 * 1 ***], the seventh input port Pi
The data of (6) is selectively output and the selection signal is [11 * 1
***], the data of the eighth input port Pi (7) is selectively output.

Here, as described above, the * mark is an arbitrary number of 0 or 1, and therefore, of the selection signals,
Assuming that all * above the most significant digit with bit data being 1 are 0 and all * below the most significant digit with bit data being 1 are 1, FIG. (B).

FIG. 4B shows eight kinds of 7 bits including [000... 000] and changing from the least significant digit so that 1 continues.
This indicates that eight input ports can be selected one by one by a bit selection signal.

FIGS. 3 and 4 show the case of an 8: 1 binary tree multiplexer. In the case of a 32: 1 binary tree multiplexer, 31 switches are used and any of the 32 input ports is used. What is necessary is just a 31-bit selection signal.

Although the circuit is not shown, when a 32: 1 binary tree multiplexer is used, as shown in FIG.
0 ... 000], and 32 input ports Pi (0) to Pi (31) by 32 kinds of 31-bit selection signals S1 to S31 which change so that 1 continues from the least significant digit.
Can be selected one by one.

Therefore, as shown in FIG. 6, the exponent part conversion circuit 35 includes five 32: 1 binary tree multiplexers 3.
6a to 36e, and if 31-bit digit signals output from the digit position detection circuit 32 are input as the selection signals S1 to S31, 32 types of 5-bit signals are output for the 32 types of selection signals. can do.

As shown in FIG. 6, the odd-numbered input ports of the binary tree multiplexer 36a have 0,
1 is preset to the even-numbered input ports. Also,
a is a number from 0 to 7, the binary tree multiplexer 36
b is 0 for the 4a + 1 and 4a + 2 input ports,
1 is preset to the 4a + 3rd and 5ath input ports, 0 is preset to the 8a + 1th to 8a + 4th input ports of the binary tree multiplexer 36c, and 1 is preset to the 8a + 5th to 9ath input ports. 0, 16a + 9th to 17a are input to the 16a + 1th to 8a + 8th input ports of the branch tree multiplexer 36d.
The 1st input port is preset with 1, the 0th is preset for the 1st to 16th input ports of the binary tree multiplexer 36e, and the 1 is preset for the 17th to 32nd input ports.

By presetting the input ports of the respective binary tree multiplexers in this manner, as shown in FIG. 7, the 5-bit signals [B ₄ , B _3] output from the five binary tree multiplexers 36a to 36e are used. , B ₂ , B ₁ , B
₀ ] indicates the exponent part B of the count result n, and the 5-bit exponent part B corresponding to the count result n can be converted and output.

On the other hand, the mantissa selection circuit 37 calculates the count result n
As shown in FIG. 8, a matrix circuit 38 and three 32: 1 binary tree multiplexers 39 as shown in FIG.
a, 39b and 39c.

The matrix circuit 38 is provided with three types of shift signals Fa, Fb, and F in which the bit positions are shifted with respect to the 32-bit count result n latched by the count latch circuit 31.
c is output to the input port of each of the binary tree multiplexers 39a, 39b, and 39c.

That is, from the first bit of the counting result n to the second bit
For data up to the 9th bit

A first shift signal Fa obtained by adding 3 bits of [000] to the lower order is input to the binary tree multiplexer 39a, and the first shift signal Fa is counted from the first bit of the counting result n to the 30th bit.
For data up to the bit

The second shift signal Fb obtained by adding the lower two bits of [00] to the binary tree multiplexer 39
b into the data from the first bit to the 31st bit of the count result n.

The third shift signal Fc obtained by adding one bit of [0] to the lower order is input to the binary tree multiplexer 39b.

The binary tree multiplexers 39a and 39
b and 39c include shift signals Fa to Fc and 31-bit selection signals S1 to S3 from the digit position detection circuit 32.
1 has been entered.

Therefore, as shown in FIG. 9, the selection output M ₂ of the binary tree multiplexer 39c for the counting result n is always one more than the highest digit of the counting result n which has advanced during the counting. become a digit lower of data, select the output M ₁ of the binary tree multiplexer 39b is, the counting result is always as two digits lower data from the most significant digit, which was stepped on during the counting of the n, the binary tree multiplexer 39a selects and outputs M ₀ is always 3 from the most significant digit of the counting result n that has progressed during counting.
This is the lower digit data.

Therefore, three binary tree multiplexers 39
a, 39b, 39c [M]
₂ , M ₁ , M ₀ ] is the mantissa M of the lower 3 bits following the most significant digit of the counting result n which has been incremented during the counting.

As described above, in this embodiment, in order to convert the count output in the fixed-point format to the floating-point format,
Since the conversion of the exponent part and the selection of the mantissa are performed by using a binary tree multiplexer composed of a plurality of switches without performing the arithmetic processing, extremely high-speed format conversion can be performed, and the minimum measurable time width is shortened. Measurement can be performed without missing short pulse or pulse interval generated instantaneously.

The 5-bit exponent B and the 3-bit mantissa M thus obtained specify the address of the memory 26 as an 8-bit address signal. Note that how to combine the 5 bits of the exponent part and the 3 bits of the mantissa part is arbitrary. For example, the exponent part 5 bits may be set to the upper side of the address signal and the mantissa part 3 bits may be set to the lower side. Conversely, the exponent part 5 bits may be set to the lower side of the address signal and the mantissa part 3 bits may be set to the upper side. Alternatively, an 8-bit address signal may be inserted by inserting 3 bits of the mantissa between the 5 bits.

Although the change of the address signal does not become linear with respect to the change of the count result n, since the address signal is uniquely determined for each count result n, the address of the address specified by this address signal is determined. By increasing the data sequentially from 0, the frequency of the measured time width can be detected.

As described above, the frequency data stored in the memory 26 during the predetermined measurement time is read out by the frequency data processing means 28 and read out by the display device 2 as described above.
9 is displayed on the coordinate screen of FIG.
Since the bit read address does not directly represent the count result (pulse width) of the binary counter 23, the frequency data processing means 28 needs to calculate (pulse width) from this read address.

That is, of the 8-bit read address, 5
For the exponent part B of bits and the mantissa part M of 3 bits, the value m when the counting result n is represented by 4 significant bits is m = [1+ (M / 8)] × 2 ^Since it is ^B , the value m obtained by substituting the 5-bit exponent part B and the 3-bit mantissa part M into this equation is the pulse width.
The frequency data processing means 28 calculates the
The pulse width corresponding to the address No. 6 is obtained, and the frequency data is displayed on the time width axis.

When the count output in the fixed-point format is converted to the floating-point format as in the time width distribution measuring device 20 of this embodiment, the resolution is high when the count result (time width) is small, and the count result is low. Since the resolution is reduced as the size increases, there is no substantial decrease in accuracy, and as described above, it is possible to measure a wide time width and a highly accurate measurement with a short time width with a small memory capacity. ing.

In the above embodiment, the binary counter 2
3, the counting result output in fixed-point format is converted to floating-point format using a binary tree multiplexer, but this is not a limitation of the present invention. The unit may be calculated.

As described above, the analog signal S to be measured may be compared with the threshold value by the analog comparator, and the output of the analog comparator may be used to control the count of the binary counter.

Further, the frequency updating circuit 27 of the above embodiment is used.
Has updated the frequency data of the memory 26 by one, but this is not a limitation of the present invention. If the data can determine the designated frequency of the same address, the data stored in the memory 26 is The value may not represent the frequency itself.

In the above embodiment, the 32-bit count result is converted into a 5-bit exponent part and a 3-bit mantissa floating point format. However, this is not limited to the present invention. If the counting result is 32 bits and the address of the memory 26 is 16 bits, the mantissa part is set to 11 bits. When the counting result is 64 bits and the address of the memory 26 is 16 bits, the exponent part may be 6 bits and the mantissa part may be 10 bits.

[0086]

As described above, the time width distribution measuring device of the present invention converts the counting result of the binary counter into a floating point format, and specifies the address of the memory with the converted signal. Therefore, measurement can be performed with a small memory capacity from a short time width to a wide time width without lowering the practical accuracy.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a digit position detection circuit according to the embodiment;

FIG. 3 is a diagram illustrating an example of an 8: 1 binary tree multiplexer;

FIG. 4 is a diagram for explaining the operation of an 8: 1 binary tree multiplexer;

FIG. 5 is a diagram for explaining the operation of a 32: 1 binary tree multiplexer;

FIG. 6 is a block diagram illustrating a configuration of an exponent part conversion circuit according to the embodiment;

FIG. 7 is a view for explaining the operation of the exponent part conversion circuit according to the embodiment;

FIG. 8 is a block diagram illustrating a configuration of a mantissa selection circuit according to the embodiment;

FIG. 9 is a diagram for explaining the operation of the mantissa selection circuit according to the embodiment;

FIG. 10 is a block diagram showing the configuration of a conventional device.

FIG. 11 is a timing chart for explaining the operation of the conventional device.

[Explanation of symbols]

Reference Signs List 20 time distribution measuring device 21 A / D converter 22 digital comparator 23 binary counter 24 clock signal generator 25 timing controller 26 memory 27 frequency updating circuit 28 frequency data processing means 29 display device 30 floating-point conversion circuit 31 count latch Circuit 32 Digit position detection circuit 33 _{1 to} 33 ₃₁ Flip-flop 34 Latch circuit 35 Exponent part conversion circuit 36 a to 36 e Binary tree multiplexer 37 Mantissa part selection circuit 38 Matrix circuit 39 a to 39 c Binary tree multiplexer

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takashi Shinozuka 6-6-6 Minamiyoshinari, Aoba-ku, Sendai, Miyagi Prefecture Inside the Electromagnetic Research Institute, Inc. (72) Masahiro Kuroda 5--10 Minamiazabu, Minato-ku, Tokyo No. 27 Anritsu Corporation

Claims (3)

[Claims] 1. A comparator for comparing an analog signal to be measured with a predetermined threshold value, receiving a comparison output of the comparator, and counting a clock signal of a predetermined cycle while the comparison output is at one level. And outputs the count result as a predetermined bit number L as time width data of the analog signal with respect to the threshold value.
Binary counter, and L output from the binary counter during a predetermined measurement period.
A floating point number which converts the bit counting result into a floating point format having a significant number of digits less than the L bits and sequentially outputs an (I + J) bit signal in which the exponent part of the I bit and the mantissa part of the J bit are combined. A memory for receiving a (I + J) -bit signal output from the floating-point conversion circuit as an address signal and reading data stored at an address specified by the address signal; A time width distribution measuring device, comprising: an updating circuit that updates the data to be updated to data representing the frequency at which the address of the data is specified. 2. The floating-point conversion circuit, comprising: a digit position detection circuit for detecting the most significant digit position of the L-bit count output of the binary counter that has been incremented during counting; and the digit position detection circuit. An exponent part conversion circuit that outputs an exponent part of the I-bit based on the digit position detected by; and the L-bit counting result based on the digit position detected by the digit position detection circuit. 2. The time width distribution measuring device according to claim 1, further comprising: a mantissa selection circuit that selects and outputs, as the mantissa, lower-order J-bit data following the most significant digit advanced during the counting. 3. The digit position detecting circuit outputs (L-1) bits of the count output of the binary counter, excluding the least significant bit, of the L bits of the binary counter to (L-1) bits. The flip-flop receives and latches 1-bit data with respect to the digit incremented during the counting, and latches the latch data of the (L-1) flip-flops when the counting of the binary counter is completed. The exponent conversion circuit is configured to output a signal of (L-1) bits corresponding to the most significant digit position advanced during the counting, and the exponent part conversion circuit outputs (L-1) ) The exponent part of the I bits is output by I L: 1 binary tree multiplexers that receive a bit signal as a selection signal, and the mantissa selection circuit is output from the digit position detection circuit. (L-1) The J-bit data is selected and output as a mantissa from the count result of the binary counter by J L: 1 binary tree multiplexers receiving the bit signal as a selection signal. 3. The time width distribution measuring device according to claim 2, wherein