JPH11331641A - Horizontal synchronizing circuit and image display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the horizontal synchronizing circuit and the image display device that use one PLL circuit and facilitate digital control regardless of a small circuit scale. SOLUTION: The circuit is provided with a pseudo horizontal synchronizing signal output circuit 1 that provides an output of a pseudo horizontal synchronizing signal synchronously with a horizontal synchronizing signal and whose pulse width is variable, a PLL circuit that generates a clock whose frequency is a multiple of the pseudo horizontal synchronizing signal outputted from the pseudo horizontal synchronizing signal output circuit 1, horizontal drive pulse generating circuits 5, 8 that generate a horizontal drive pulse with a prescribed pulse width and delayed from the pseudo horizontal synchronizing signal by a prescribed time based on the clock generated by the PLL circuit 11, voltage signal output circuits 7, 10 that provide an output of a voltage signal in response to a phase difference between the horizontal drive pulse and an FBT pulse generated by the voltage signal output circuits 7, 10, and the pseudo horizontal synchronizing signal output circuit 1 changes a pulse width of the pseudo horizontal synchronizing signal in response to the voltage signal outputted from the voltage signal output circuits 7, 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal scan monitor used in a multi-scan monitor television capable of displaying a video signal screen following various vertical and horizontal synchronizing signals separated from the video signal. The present invention relates to an improvement in a synchronous circuit and a screen display device.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional television which is a multi-scan monitor television capable of displaying a video signal screen following various vertical synchronization signals and horizontal synchronization signals separated from a video signal. FIG. 3 is a block diagram illustrating a configuration example of a horizontal synchronization circuit of the receiver. In this horizontal synchronization circuit, a horizontal synchronization signal (horizontal synchronization pulse) separated from a video signal is supplied to a monostable multivibrator 21. The monostable multivibrator 21 uses the horizontal synchronization signal as a trigger pulse, and outputs a resistor R4 and a capacitor. A delay pulse whose pulse width is determined by the time constant of C3 is output.

The delay pulse output from the monostable multivibrator 21 is given to a monostable multivibrator 22 having a constant time constant by a capacitor C4, and the monostable multivibrator 22 uses the delay pulse as a trigger pulse to generate a pseudo horizontal synchronization signal. Output a signal.

[0004] The pseudo horizontal synchronizing signal output from the monostable multivibrator 22 is an AFC (Automatic Frequency Coupling).
ntrol) circuit 24. The AFC circuit 24 adjusts the phase difference between the applied pseudo-horizontal synchronization signal and an FBT pulse described later, and supplies a horizontal drive pulse for driving a horizontal output transistor to the horizontal deflection circuit 25. A
The FC circuit 24 has a voltage at a predetermined position and a reference voltage (REF).
And an analog comparator 23 for adjusting the pulse width of the horizontal drive pulse by comparing the horizontal drive pulse with the voltage of the horizontal drive pulse. The horizontal deflection circuit 25 outputs the FBT pulse generated by the flyback transformer (FBT) of the high-voltage circuit during the flyback period during which the horizontal output transistor is not driven to the AFC.
To the circuit 24.

In such a horizontal synchronizing circuit, FIG.
The delay pulse output by the monostable multivibrator 21 is changed by the horizontal synchronization signal (horizontal synchronization pulse) shown in FIG.
As a delay signal, a monostable multivibrator 22
Outputs the pseudo-horizontal synchronization signal shown in FIG. 5B, and this pseudo-horizontal synchronization signal is supplied to the AFC circuit 24,
The circuit 24 includes the pseudo horizontal synchronizing signal and the FB shown in FIG.
By adding the phase difference from the T pulse as a DC voltage to a built-in horizontal oscillation circuit, the horizontal synchronization signal is synchronized with the horizontal deflection circuit.

Since the AFC circuit 24 has both a frequency difference detection function and a phase difference detection function, the AFC circuit locks to the horizontal synchronizing signal and the variation generated by the horizontal deflection circuit 25, that is, the accumulation time of the horizontal output transistor, , It is possible to absorb the phase difference between the horizontal drive pulse and the FBT pulse. In addition, the horizontal screen position can be changed by changing the time constant of the monostable multivibrator 21. However, the AFC circuit 24 alone cannot change the pulse width of the horizontal drive pulse in order to optimally drive the horizontal output transistor. For that reason,
An analog comparator 23 is added, and a DC power supply for generating a REF voltage is also required.

FIG. 6 shows a conventional television receiver which is a multi-scan monitor television capable of displaying a screen of a video signal following various vertical synchronization signals and horizontal synchronization signals separated from the video signal. FIG. 2 is a block diagram showing a configuration example of a horizontal synchronization circuit capable of performing more digital processing. In this horizontal synchronization circuit, a horizontal synchronization signal (horizontal synchronization pulse) separated from a video signal is supplied to a digital phase comparator 30, and the phase comparator 30
The horizontal synchronizing signal and 1 / X from the 1 / X divider 33 described later
A phase difference signal from the double clock is applied to the low-pass filter 31.

The phase difference signal smoothed by the low-pass filter 31 is applied to a voltage controlled oscillator (VCO) 32, which outputs a clock having a frequency corresponding to the applied smoothed phase difference signal. . This clock is supplied to a counter 35 and also to a 1 / X frequency divider 33, and the 1 / X frequency divider 33 supplies 1 / X times the supplied clock to the above-described phase comparator 30.
The phase comparator 30, the low-pass filter 31, the voltage-controlled oscillator 32, and the 1 / X frequency divider 33 include a PLL (Phase Locked L).
oop) constitutes the circuit 34 and multiplies the horizontal synchronization signal (X times)
A clock having a frequency is created and given to the counter 35.

The counter 35 outputs a pseudo-horizontal synchronization signal (pseudo-horizontal synchronization signal pulse) of the given X times clock, which is delayed from the horizontal synchronization signal by a predetermined number set in the digital comparator 36, and outputs a digital signal. It is provided to the phase comparator 37. The phase comparator 37 supplies a low-pass filter 38 with a phase difference signal between the pseudo horizontal synchronizing signal and an FBT pulse described later.

The phase difference signal smoothed by the low-pass filter 38 is applied to a voltage controlled oscillator 39. The voltage controlled oscillator 39 outputs a clock having an X-times frequency when the applied smoothed phase difference signal is 0. I do. This clock is provided to the counter 40, and the counter 40
A horizontal drive pulse for driving a horizontal output transistor, which has a pulse width of a predetermined number set in the comparator 36 and is a double clock, is given to the horizontal deflection circuit 42. The horizontal deflection circuit 42 supplies the phase comparator 37 with an FBT pulse generated by a flyback transformer (FBT) of a high-voltage circuit during a flyback period in which the horizontal output transistor is not driven. The phase comparator 37, the low-pass filter 31, the voltage controlled oscillator 32, and the horizontal deflection circuit 42 constitute a PLL circuit 43. The PLL circuit 43 generates a clock having a frequency (X times) the frequency of the pseudo horizontal synchronization signal, and supplies the clock to the counter 40.

In such a horizontal synchronizing circuit, the PLL circuit 34 converts the horizontal synchronizing signal (horizontal synchronizing pulse) shown in FIG. 7A into an X-times period shown in FIG. Is generated and given to the counter 35. The counter 35 outputs a pseudo-horizontal synchronization signal shown in FIG. 7C, which is delayed by a predetermined number of the given X times clock from the horizontal synchronization signal, and supplies the same to the PLL circuit 43. PLL
When the phase difference between the quasi-horizontal synchronization signal and the FBT pulse is 0, the circuit 43 outputs a clock having an X-times frequency shown in FIG. A horizontal drive pulse having a pulse width of a predetermined number of clocks shown in FIG.

The horizontal deflection circuit 42 generates a FB shown in FIG. 7F in a flyback period in which a flyback transformer (FBT) of a high voltage circuit is not driven by a horizontal output transistor.
The T pulse is supplied to the phase comparator 37 as a comparison pulse of the pseudo horizontal synchronization signal. In such a horizontal synchronization circuit, F
By giving the BT pulse to the phase comparator 37 as a comparison pulse of the pseudo-horizontal synchronization signal, it is possible to absorb variations in the horizontal deflection circuit 42.

[0013]

However, two PLL circuits are required, and the circuit scale becomes large. Further, since the number of the voltage controlled oscillators is two, the degree of interference and fluctuation is doubled. The present invention has been made in view of the above-described circumstances, and has as its object to provide a horizontal synchronization circuit and a screen display device that use a single PLL circuit, have a small circuit size, and are easily digitally controlled. And

[0014]

According to a first aspect of the present invention, a horizontal synchronization circuit generates a horizontal drive pulse for driving a horizontal output transistor of a horizontal deflection circuit based on a horizontal synchronization signal. A horizontal synchronizing circuit for stabilizing the period of the horizontal drive pulse by synchronizing with an FBT pulse generated by the flyback transformer outputs a pseudo horizontal synchronizing signal having a variable pulse width in synchronization with the horizontal synchronizing signal. A pseudo-horizontal synchronizing signal output circuit to generate a clock having a frequency multiplied by the pseudo-horizontal synchronizing signal output by the pseudo horizontal synchronizing signal output circuit
An LL circuit, a horizontal drive pulse generation circuit for generating the horizontal drive pulse having a predetermined pulse width and delayed by a predetermined time from the pseudo horizontal synchronization signal based on the clock generated by the PLL circuit, and the horizontal drive pulse generation circuit And a voltage signal output circuit that outputs a voltage signal corresponding to the phase difference between the horizontal drive pulse and the FBT pulse created by the pseudo-horizontal synchronization signal output circuit. The pseudo-horizontal synchronization signal output circuit responds to the voltage signal output by the voltage signal output circuit. The pulse width of the pseudo horizontal synchronizing signal is changed.

In this horizontal synchronizing circuit, a pseudo horizontal synchronizing signal output circuit outputs a pseudo horizontal synchronizing signal having a variable pulse width in synchronization with the horizontal synchronizing signal, and a PLL circuit multiplies the output pseudo horizontal synchronizing signal by a multiple. Create a clock with a frequency. The horizontal drive pulse generation circuit generates a horizontal drive pulse having a predetermined pulse width and delayed by a predetermined time from the pseudo horizontal synchronization signal based on the generated clock, and the voltage signal output circuit outputs the horizontal drive pulse and the FBT pulse. A voltage signal according to the phase difference is output, and the pseudo-horizontal synchronization signal output circuit changes the pulse width of the pseudo-horizontal synchronization signal according to the voltage signal output from the voltage signal output circuit.
As a result, it is possible to realize a horizontal synchronizing circuit having a small circuit size and easy digital control using one PLL circuit.

According to a second aspect of the present invention, in the horizontal synchronization circuit, the voltage signal output circuit includes the horizontal drive pulse and the FB.
It is characterized by including a flip-flop circuit whose output is inverted by a T pulse and an integration circuit for integrating a pulse output from the flip-flop circuit.

In this horizontal synchronizing circuit, the output of the flip-flop circuit is inverted by the horizontal drive pulse and the FBT pulse, and the integration circuit integrates the pulse output by the flip-flop circuit. As a result, the voltage signal output circuit can output a voltage signal corresponding to the phase difference between the horizontal drive pulse and the FBT pulse, the circuit scale is small using one PLL circuit, and the horizontal signal is easy to digitally control. A synchronous circuit can be realized.

According to a third aspect of the present invention, there is provided a screen display device.
Or a horizontal synchronizing circuit according to (2).

Since this screen display device includes the horizontal synchronizing circuit according to the first or second aspect, the circuit scale is reduced and digital control is facilitated.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing the embodiments. FIG. 1 is a block diagram showing a configuration of an embodiment of a horizontal synchronization circuit according to the present invention. In the horizontal synchronization circuit, a horizontal synchronization signal (horizontal synchronization pulse) separated from a video signal is supplied to a monostable multivibrator 1.
With the horizontal synchronization signal as a trigger pulse, a pseudo horizontal synchronization signal (pseudo horizontal synchronization pulse) whose pulse width is determined by the time constant of the resistor R3 and the capacitor C2 is output. One of the resistor R3 and the capacitor C2 is connected in common to the monostable multivibrator 1 and the other is a parallel circuit in which the other is grounded.

The pseudo-horizontal synchronizing signal output from the monostable multivibrator 1 is supplied to a digital phase comparator 2, and the phase comparator 2 generates the pseudo-horizontal synchronizing signal and 1 /
A phase difference signal from the 1 / X clock from the X frequency divider 9 is supplied to the low-pass filter 3. The phase difference signal smoothed by the low-pass filter 3 is applied to a voltage controlled oscillator (VCO) 4. The voltage controlled oscillator 4 has a frequency corresponding to the applied smoothed phase difference signal, as shown in FIG. Output the indicated clock. This clock is applied to a counter 5 and also to a 1 / X divider 9, and the 1 / X divider 9
The 1 / X times clock shown in FIG. 2G of the given clock is applied to the phase comparator 2 described above. Phase comparator 2,
The low-pass filter 3, the voltage-controlled oscillator 4 and the 1 / X frequency divider 9 constitute a PLL (Phase Locked Loop) circuit 11, which generates a clock having a frequency (X times) of the frequency of the pseudo horizontal synchronizing signal and supplies it to the counter 5. .

The counter 5 has a pulse width of a given number set by the digital comparator 8 of the given X times clock, and drives a horizontal output transistor delayed by a given number of times of the X times clock. Is supplied to the horizontal deflection circuit 6 and the flip-flop circuit 7. The horizontal deflection circuit 6 supplies the flip-flop circuit 7 with an FBT pulse generated by a flyback transformer (FBT) of a high-voltage circuit during a flyback period. Phase comparator 2,
The low-pass filter 3, the voltage-controlled oscillator 4 and the 1 / X divider 9 constitute a PLL circuit 11, generate a clock having a frequency (X times) the frequency of the pseudo-horizontal synchronization signal, and supply it to the counter 5.

The flip-flop circuit 7 outputs a phase difference pulse indicating a phase difference between the horizontal drive pulse and the FBT pulse, and supplies the phase difference pulse to the integration circuit 10. The integrating circuit 10 is configured such that a resistor R2, to which one side receives a phase difference pulse, and a capacitor C1, one of which is grounded, are commonly connected to each other. Is connected to the other of the resistor R1 commonly connected to one of the resistor R3 and the capacitor C2.

The operation of the horizontal synchronizing circuit having such a configuration will be described below. In this horizontal synchronization circuit, the monostable multivibrator 1 is inverted in polarity from the horizontal synchronization signal as shown in FIG. 2B by the horizontal synchronization signal (horizontal synchronization pulse) shown in FIG. A pseudo-horizontal synchronization signal (pseudo-horizontal synchronization pulse) whose width is determined by the time constant of the resistor R3 and the capacitor C2 is output, and the pseudo-horizontal synchronization signal is supplied to the PLL circuit 11. The PLL circuit 11
From the pseudo-horizontal synchronization signal, synchronized with the pseudo-horizontal synchronization signal,
A clock having an X-times cycle shown in FIG. The counter 5 has a pulse width which is delayed by a given number of the given X-times clocks from the pseudo-horizontal synchronization signal and has a pulse width of a given number of the X-times clocks, and outputs the horizontal drive pulse shown in FIG. 6 and a flip-flop circuit 7.

In the horizontal deflection circuit 6, a flyback transformer (FBT) of a high voltage circuit is generated during a flyback period, as shown in FIG.
The FBT pulse shown in FIG. The flip-flop circuit 7 outputs a phase difference pulse shown in FIG. 2 (e) indicating the phase difference between the horizontal drive pulse and the FBT pulse, and this phase difference pulse is integrated by the integration circuit 10 and according to the phase difference. Is converted to a voltage value and supplied to one of the resistors R1. As a result, the pulse width of the pseudo horizontal synchronization signal output from the monostable multivibrator 1 changes according to the phase difference.

The rising edge R of the pseudo horizontal synchronizing signal
And the edge S of the phase comparison pulse output by the 1 / X divider 9 of the PLL circuit 11 is compared by the digital phase comparator 2, and a voltage corresponding to the phase difference is output by the voltage controlled oscillator 4.
, The frequency of the clock oscillated by the voltage controlled oscillator 4 changes. The pulse width and position of the horizontal drive pulse can be changed by controlling the rise and fall of the horizontal drive pulse by the digital comparator 8.

The variation in the horizontal deflection circuit 6 is given to the phase comparator 2 as a change in the pulse width of the pseudo horizontal synchronizing signal output from the monostable multivibrator 1. When the pulse width of the pseudo horizontal synchronization signal is large, the frequency of the oscillation clock of the voltage controlled oscillator 4 is controlled to be high, and when the pulse width of the pseudo horizontal synchronization signal is small, the frequency is controlled to be low. As a result, variations in the horizontal deflection circuit 6 can be absorbed.

FIG. 3 is a block diagram showing the configuration of a color television receiver as an embodiment of the screen display device according to the present invention. In the color television receiver, a color television wave received by an antenna 50 is selectively amplified by a tuner 51, converted into an intermediate frequency signal, and sent to a video intermediate frequency amplification / detection circuit 52. The intermediate frequency signal is amplified by a video intermediate frequency amplification / detection circuit 52 and separated into a television signal and an audio intermediate frequency signal. After the audio intermediate frequency signal is amplified by the audio intermediate frequency amplification circuit 65, the audio signal is detected and amplified by the audio detection amplification circuit 66 and output from the speaker 67.

The television signal is amplified by a video amplifier circuit 53 and then separated into a carrier chrominance signal C and a luminance signal Y. The carrier chrominance signal C is sent to a chrominance signal reproducing circuit 54, and the luminance signal Y is a luminance signal. The signal is sent to the amplification circuit 55 and the synchronization circuit 56. The color signal reproducing circuit 54 reproduces and outputs the color difference signals RY, GY and BY from the carrier color signal C. The luminance signals Y amplified by the luminance signal amplifier circuit 55 are added to the color difference signals RY, GY, and BY, respectively, to become color signals R, G, and B, which are input to the color receiving tube 64. Is done.
In the color receiving tube 64, the color signals R, G, B become electron beams corresponding to the respective intensities.

The synchronization circuit 56 includes a synchronization separation circuit 57 for separating the synchronization signal from the luminance signal Y, and a vertical synchronization separation circuit for separating the vertical synchronization signal from the synchronization signal separated by the synchronization separation circuit 57 and outputting the synchronization pulse. 58 and a horizontal synchronizing signal from the synchronizing signal separated by the synchronizing separation circuit 57,
A horizontal deflection circuit 6 for driving the horizontal deflection coil L2 of the color receiving tube 64 and a vertical deflection circuit 59 for driving the vertical deflection coil L1 are provided. The horizontal deflection circuit 6 supplies the horizontal synchronization circuit 60 with an FBT pulse generated during a flyback period in which the flyback transformer (FBT) of the high voltage circuit does not drive the horizontal output transistor. The horizontal synchronization circuit 6 performs control so that the horizontal synchronization signal and the FBT pulse always maintain a predetermined phase difference.

[0031]

According to the horizontal synchronizing circuits according to the first and second aspects of the present invention, it is possible to realize a horizontal synchronizing circuit having a small circuit size and easy digital control using one PLL circuit.

According to the screen display device of the third aspect, the circuit scale is reduced, and digital control is facilitated.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a horizontal synchronization circuit according to the present invention.

FIG. 2 is a timing chart showing an operation of the horizontal synchronization circuit shown in FIG.

FIG. 3 is a block diagram illustrating a configuration of an embodiment of a screen display device according to the present invention.

FIG. 4 is a block diagram illustrating a configuration example of a conventional horizontal synchronization circuit.

5 is a timing chart showing an operation of the horizontal synchronization circuit shown in FIG.

FIG. 6 is a block diagram illustrating a configuration example of a conventional horizontal synchronization circuit.

7 is a timing chart showing an operation of the horizontal synchronization circuit shown in FIG.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 monostable multivibrator (pseudo-horizontal synchronization signal output circuit) 2 phase comparator (PLL circuit) 3 low-pass filter (PLL circuit) 4 voltage-controlled oscillator (PLL circuit) 5 counter (horizontal drive pulse generation circuit) 6 horizontal deflection circuit 7 Flip-flop circuit (voltage signal output circuit) 8 Comparator (horizontal drive pulse generation circuit) 9 1 / X frequency divider (PLL circuit) 10 Integrator circuit (voltage signal output circuit) 60 Horizontal synchronization circuit 64 Color receiving tube C1, C2 Capacitor R1, R2, R3 Resistance 64 Color receiver tube A Vertical synchronization signal (vertical synchronization pulse) B Horizontal synchronization signal (horizontal synchronization pulse) L1 Vertical deflection coil L2 Horizontal deflection coil

Claims (3)

[Claims] 1. A horizontal drive pulse for driving a horizontal output transistor of a horizontal deflection circuit is generated based on a horizontal synchronization signal, and the horizontal synchronization signal is synchronized with an FBT pulse generated by a flyback transformer of the horizontal deflection circuit. Thus, in a horizontal synchronization circuit for stabilizing the cycle of the horizontal drive pulse, a pseudo horizontal synchronization signal output circuit for outputting a pseudo horizontal synchronization signal having a variable pulse width in synchronization with the horizontal synchronization signal; A PLL circuit for generating a clock having a frequency multiplied by the pseudo-horizontal synchronization signal output from the output circuit;
A horizontal drive pulse generation circuit for generating the horizontal drive pulse having a predetermined pulse width and being delayed for a predetermined time from the pseudo horizontal synchronization signal based on the clock generated by the LL circuit; and a horizontal drive pulse generated by the horizontal drive pulse generation circuit. And a voltage signal output circuit that outputs a voltage signal corresponding to the phase difference between the pulse and the FBT pulse. The pseudo-horizontal synchronization signal output circuit outputs the pseudo-horizontal signal in response to the voltage signal output by the voltage signal output circuit. A horizontal synchronizing circuit characterized by changing a pulse width of a synchronizing signal. 2. The voltage signal output circuit includes a flip-flop circuit whose output is inverted by the horizontal drive pulse and the FBT pulse, and an integration circuit that integrates a pulse output from the flip-flop circuit. Horizontal synchronization circuit. 3. A screen display device comprising the horizontal synchronization circuit according to claim 1.