JPH11331134A - Biphase code signal identifying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely provide phase synchronism, even if there is a phase difference between an input biphase signal and a clock signal for identifying this signal. SOLUTION: This signal identifying device is provided with a clock generating part 23 for generating a first clock signal CK1 synchronizing its phase with one symbol block of the biphase signal and a second clock signal CK2, having a prescribed phase different from that of the clock signal, first synchronizing pattern detecting part 21 for detecting a prescribed synchronizing pattern from data sampling the biphase signal with the clock signal CK1, a second synchronizing pattern detecting part 22 for detecting the synchronizing pattern from data sampling the biphase signal with the clock signal CK2, and initialization control part 30 for initializing the clock generation phase of the clock generating part 23 by detecting the synchronizing pattern through the synchronizing pattern detecting part 21 or 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bi-phase code signal discriminating apparatus, which is suitably applied to discrimination and reproduction of a bi-phase (Manchester, CMI, etc.) code signal used in wired / wireless data communication. . Generally, in data communication, block transfer (burst transfer) of data is performed between transmission and reception. On the transmission side, a predetermined frame synchronization signal (synchronization pattern signal) is placed at the beginning of the frame signal in order to match the clock signal phase between transmission and reception. insert. on the other hand,
On the receiving side, it is necessary to correctly identify and reproduce received data in phase synchronization with the frame synchronization signal.

[0002]

2. Description of the Related Art FIG.
(A) is a block diagram of a conventional Manchester / NRZ signal conversion circuit. In the figure, reference numeral 23 denotes a clock signal CK synchronized in phase with the edge of the input Manchester signal.
A clock generation unit (digital PLL circuit) that generates
Reference numeral 21 denotes a synchronization pattern detection unit that detects a predetermined synchronization pattern based on data obtained by sampling the Manchester signal using the clock signal CK. Reference numeral 10 denotes a Manchester / NRZ conversion unit that converts an input Manchester signal into an NRZ signal based on the clock signal CK. It is.

[0003] With this configuration, the synchronous pattern detecting section 2
1 outputs a synchronization detection signal SD when detecting a predetermined synchronization pattern "01010101" with respect to the input Manchester signal. The clock generation unit 23 pulls its own clock phase to a predetermined synchronization state by generating the synchronization detection signal SD, and locks the phase. Therefore, the received data after the synchronization detection can be properly identified and reproduced.

FIG. 5B shows the operation when the clock phase is normal. Generally, the Manchester code is represented such that bit “0” of the NRZ signal has a signal level of “01” and bit “1” of the NRZ signal has a signal level of “10”. In the figure, bit “0” of NRZ is changed to “1”.
0 and the NRZ bit “1” is set to “0”.
Although the signal level is represented by a signal level of "1", it is sufficient to consider here that a Manchester signal whose level is inverted is handled.
Or, even if code conversion is performed as in the latter, generality of signal conversion processing is not lost.

Now, assume that the clock phase relationship in a normal state is as shown in FIG. When the synchronization pattern of the Manchester signal is input, “010101” is output at each falling edge of the clock signal CK.
01 "is sampled, and a synchronization pattern is detected. By the way, when receiving such a frame (burst) signal, the clock phase of the receiving side is not always normal.

FIG. 5C shows the operation when the clock phase has an error (including the jitter of the input signal). For example, if the phase of the input Manchester signal and the phase of the clock signal CK are shifted from each other by 90 degrees from the normal state, the sampling result of the Manchester signal becomes indefinite (or error) as shown in the figure, and the synchronous pattern cannot be detected. FIG. 5D shows the operation when the duty of the input signal changes.

[0007] Even when the duty of the Manchester signal fluctuates, the synchronization result cannot be detected because the sampling result is uncertain (or incorrect).

[0008]

As described above, in the conventional Manchester / NRZ signal conversion circuit, the phase difference (jitter, jitter) between the input Manchester signal and the clock signal CK is obtained.
(Including duty fluctuation), there is a problem that the synchronization pattern cannot be detected. This often resulted in loss of synchronization.

In the above-mentioned conventional circuit, if the received data after the detection of the synchronization pattern includes data (pseudo synchronization pattern) having the same bit configuration as the synchronization pattern, the synchronization pattern detection unit that detects this is detected. There is also a problem that the clock generation unit 23 is re-initialized by 21. Further, the conventional circuit has a problem that a noise signal or the like in a non-transfer section of a burst signal is erroneously recognized as a synchronization pattern, and the circuit is pulled into erroneous phase synchronization.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to determine what kind of phase difference between an input biphase signal and a clock signal for identifying the biphase signal. It is an object of the present invention to provide a bi-phase signal identification device capable of surely obtaining phase synchronization even when (including jitter, duty fluctuation, etc.) is present.

[0011]

The above-mentioned problem is solved, for example, by referring to FIG.
The problem is solved by the configuration of (A). That is, the biphase signal identification device of the present invention (1) includes a first clock signal CK1 that is phase-synchronized with one symbol section of an input biphase code signal, and a second clock signal CK1 having a predetermined phase different from the first clock signal. Clock generator 2 for generating clock signal CK2
3, a first synchronization pattern detection unit 2 for detecting a predetermined synchronization pattern based on data obtained by sampling the bi-phase code signal using the first clock signal CK1.
1, a second synchronization pattern detector 22 for detecting the predetermined synchronization pattern based on data obtained by sampling the biphase code signal with the second clock signal CK2, and detecting the first or second synchronization pattern. Part 21
/ 22 has an initialization control unit 30 for initializing the clock generation phase of the clock generation unit 23 upon detecting the predetermined synchronization pattern.

FIG. 1A shows a biphase / NRZ signal.
9 shows an application example to a signal conversion device. FIG. 1 (B)
Shows an operation timing chart when the phase of the clock signal CK1 is normal. In FIG. 1B, for example, assuming that a clock phase in a normal state is as shown in the figure, a synchronization pattern “01010101” in an input bi-phase (the figure is Manchester) signal is generated by, for example, each falling of the first clock signal CK1. Properly sampled and reliably detected. Therefore, based on this, the initialization control unit 30
Can properly initialize the clock generation phase of the clock generation unit 23.

FIG. 1C is an operation timing chart when the phase of the clock signal CK1 is abnormal. The first clock signal CK1 has, for example, a phase 180 times that of the normal clock signal CK1. ° advanced (−
180 °). In this state, the changing portion of the signal level at the center of one symbol period of the input Manchester signal and each falling edge of the first clock signal CK1 overlap, so that the synchronization pattern cannot be properly detected. However, even in such a case, according to the present invention (1), the synchronization pattern can be properly detected by each falling edge of the second clock signal CK2 shifted by a predetermined phase from the first clock signal CK1. The initialization control unit 30 can properly initialize the clock generation phase of the clock generation unit 23.

Therefore, according to the present invention (1), what kind of phase difference (including jitter, duty fluctuation, etc.) exists between the input biphase signal and the clock signal for identifying the input biphase signal. However, phase synchronization can be reliably obtained. Preferably, in the present invention (2), the present invention (1)
, Both the first and second clock signals have a duty ratio of 、, and the phase difference between the first and second clock signals is 90 °. Accordingly, not only the phase control symmetry can be obtained, but also the phase error covering substantially 360 ° of the input can be always obtained, and the reliable phase synchronization can be obtained.

Preferably, in the present invention (3), in the above present invention (1) or (2), the biphase code signal is a Manchester code signal. Also preferably, in the present invention (4), in the above-mentioned present invention (3), the out-of-synchronization occurs because the edge of the Manchester code signal is not detected in a section where the second clock signal CK2 is at a predetermined level (for example, high level). An out-of-synchronization detecting unit 27 for detecting the out-of-synchronization is detected by the out-of-synchronization detecting unit, so that the initialization function of the initialization control unit 30 is enabled.

That is, in other words, once synchronization is obtained for one frame, the initialization function of the initialization control unit 30 cannot be activated unless an out-of-synchronization is detected thereafter. Therefore, even if the data of the frame includes a pseudo synchronization pattern having the same bit configuration as the synchronization pattern, the initialization control unit 30 does not perform the initialization operation.

Preferably, in the present invention (5), in the present invention (3), a noise detecting section 29 for detecting noise based on the input biphase code signal is further provided, and the noise detecting section 29 detects the noise. Upon detection, the initialization function of the initialization control unit 30 is set to a state in which it can be activated.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Note that the same reference numerals indicate the same or corresponding parts throughout the drawings. FIG. 2 is a diagram showing a Manchester / NRZ signal conversion circuit according to the embodiment. In the figure, reference numeral 10 denotes a Manchester / NRZ conversion unit that converts an input Manchester signal into an NRZ signal; 20, a synchronization control unit of a reception circuit; A first synchronization pattern detection unit that detects a predetermined synchronization pattern based on data obtained by sampling the Manchester signal using the first clock signal CK1, and a predetermined synchronization pattern based on data obtained by sampling the Manchester signal using the second clock signal CK2 A second synchronous pattern detector for detecting a pattern, SR1 and SR2 are shift registers, DC1 and D
C2 is a decoder, and 23 is a clock generation unit (digital PL) that generates a first clock signal CK1 that is phase-synchronized with one symbol section of the Manchester signal and a second clock signal CK2 that is 90 ° out of phase with the clock signal CK1.
L) and 24 are phase comparators, 25 is a variable frequency divider, 26 is a frequency divider, and 27 is a synchronizing state in which an edge of the Manchester signal is not detected in a section where the second clock signal CK2 = 1 (high level). An out-of-synchronization detecting unit for detecting out-of-sync,
8 is an edge detection unit, SS1 is a digital single-shot circuit, FF1 is a D-type flip-flop, 29 is a noise detection unit (shift register SR3) that detects noise based on an input biphase signal, OR
1, OR2 is an OR gate circuit, 30 is an initialization control unit for initializing the clock generation phase of the clock generation unit 23 based on the detection of a synchronization pattern, FF2 is a JK type flip-flop, and SS2 is a digital single shot circuit. is there.

The operation of each section will be described below. In the clock generation unit 23, the variable frequency divider 25 variably divides the master clock signal MCK (for example, 1.8 MHz) of the present apparatus, and the clock signal C detected by the phase comparator 24.
Based on a phase error between K1 and a phase reference signal DTS described later (that is, a signal synchronized with the center edge of one symbol section of the input Manchester signal), its own component is shifted in a direction in which the phase error becomes "0". Fine-tune the circumference ratio. On the other hand, the frequency divider 2
Reference numeral 6 designates a fixed frequency division of the output of the variable frequency divider 25, a first clock signal CK1 (here, duty １ ／) of 9.6 kHz, for example, which is phase-synchronized with one symbol section of the Manchester signal, and the clock signal CK1. And 90 °
The second clock signals CK2 (duty １ ／) having different phases are respectively generated.

In the first synchronous pattern detecting section 21,
The shift register SR1 performs serial-parallel conversion of the input Manchester signal at each falling edge of the clock signal CK1. In this case, when a synchronization pattern (for example, “01010101”) is accumulated in the shift register SR1, the decoder DC1 outputs a synchronization detection signal SD1 = 1.

The same applies to the second synchronous pattern detector 22, except that the shift register SR2 performs serial-parallel conversion of the input Manchester signal at each falling edge of the clock signal CK2. The synchronization detection signals SD1 and SD2 are logically ORed by an OR gate circuit OR1, and when either one is satisfied, the output synchronization set signal SD = 1, whereby the FF2 outputs the clock signal C
Set at the falling edge of K2.

In the out-of-synchronization detecting section 27, the edge detecting section 28 detects a rising edge and a falling edge of the input Manchester signal and outputs a corresponding edge pulse signal EP. When the edge pulse signal EP is generated during the section of the clock signal CK2 = 1 (high level), the single shot circuit SS1 synchronizes with the edge pulse signal EP to obtain a phase reference having a predetermined pulse width (for example, the same pulse width as the clock signal CK2). Generate signal DTS. Then, FF1 is the phase reference signal DTS = 1 (high level)
Is set when the clock signal CK2 falls in the section of (1), but is reset (detection of loss of synchronization) when the clock signal CK2 falls in the section of the phase reference signal DTS = 0 (low level), As a result, the out-of-sync detection signal OSD = 1.

In the noise detecting section 29, the shift register SR3 outputs the clock signal CK1 = 1 (CK2 may be used).
Reset every time depending on the level of. The serial data input terminal DI of SR3 is at a high level. If a noise signal is put on the Manchester signal line during a period other than the above reset, the high level of the input terminal DI is shifted to the output terminals Q1 to Q4. As a result, the noise detection signal ND = 1. Here, the reason why the noise detection condition is set to four pulses of the noise signal is that in the present embodiment, it is possible to generate noise of about two pulses per symbol period when noise occurs, so that there is a margin. It is for four pulses.

The out-of-synchronization detection signal OSD and the noise detection signal ND are logically ORed by an OR gate circuit OR2, and when either one is satisfied, the output synchronous reset signal SR = 1.
FF2 is thereby reset at the falling edge of the clock signal CK2. In the initialization control unit 30,
When FF2 is set, the rising edge of the output signal Q triggers the single-shot circuit SS2 to generate a reset pulse signal RSP, thereby initializing the count phase of the variable frequency divider 25 and the like.

Incidentally, once the FF 2 is set, it is not reset until the above-mentioned loss of synchronization or noise is detected. Therefore, even if a pseudo-synchronous pattern exists in the data, the output Q of FF2 does not rise, and SS2 does not output the reset pulse signal RSP. Therefore, the clock generation unit 23 is not initialized by the pseudo synchronization pattern in the data.

FIGS. 3 and 4 are operation timing charts (1) and (2) of the Manchester / NRZ signal conversion circuit according to the embodiment. FIG. 3 shows that the Manchester signal and the clock signal CK1 are synchronized in phase. Also shows a case where it is normally changing. In this state, each falling edge of the clock signal CK1 substantially coincides with, for example, the boundary of one symbol section of the Manchester signal. On the other hand, the clock signal CK2 has a phase advance of, for example, 90 ° from the clock signal CK1, so that each rising edge of the clock signal CK2 is at a substantially middle point in the first half of the one symbol section of the Manchester signal, and each falling edge of the clock signal CK2. Are respectively located at the approximate intermediate points in the latter half of one symbol section.

Therefore, the respective rising and falling timings of the clock signal CK2 can be used for identifying the Manchester code signal. Although the Manchester / NRZ conversion unit 10 in FIG. 2 does not directly use the clock signal CK2 for code identification, the clock signal C
An identification timing corresponding to the clock signal CK2 can be generated from K1.

According to this, when the Manchester signal level = H (high) is sampled at the rising edge of the clock signal CK2 and the Manchester signal level = L (low) is sampled at the falling edge of the clock signal CK2, the NRZ is sampled. It can be converted to bit "0" of the signal. Further, at the rising edge of the clock signal CK2, the Manchester signal level = L is sampled, and the clock signal CK2 is sampled.
Can be converted to bit "1" of the NRZ signal when the Manchester signal level = H is sampled at the falling edge of the signal. In this way, by sampling the identification result of the bit “1” / “0” obtained in the immediately preceding one symbol section at the rising edge of the clock signal CK1 in the next one symbol section, an NRZ conversion signal as shown in the figure is obtained. Can be

By the way, in the Manchester signal, there is always a level change point at L → H level or H → L level at the center of one symbol section. Accordingly, if the level of the clock signal CK2 = 1 (high) is sampled by the edge pulse signal EP, as long as the phase synchronization of the clock signal CK1 is obtained, the single shot circuit SS1
Always generates the phase reference signal DTS.

Therefore, in the present embodiment, the phase is synchronized while the phase reference signal DTS is generated. That is, as long as the phase is synchronized, the phase reference signal DTS = 1 at the subsequent falling timing of the clock signal CK2, and thus the FF1 remains set. It can be seen from the figure that such a state of phase synchronization is maintained until the phase of the input Manchester signal and the clock signal CK1 deviate by about ± 90 ° from the present. That is, the input Manchester signal can be properly identified within the margin range of the clock phase. Therefore, even if the Manchester signal has some jitter or duty fluctuation, the conversion operation to the appropriate NRZ signal and the state of the phase synchronization are performed. Is obtained.

In this phase synchronization state, each phase reference signal DTS is generated in synchronization with the edge pulse signal EP.
By comparing the phase of, for example, the rising edge of the input signal with the edge of the input Manchester signal, the variable frequency divider 25 is finely adjusted so that the phase error is always "0".

Further, in FIG. 3, a pseudo synchronization pattern "01010101" having the same pattern as the synchronization pattern is included in the middle of the received data block of the Manchester signal. However, according to the present embodiment, FF2 has already been set by prior synchronization detection (not shown), and even if synchronization pattern detection signal SD1 or SD2 is generated again, FF2 is set.
The output Q of 2 does not rise. Therefore, the single shot circuit SS2 is not triggered, and thus the variable frequency divider 25 is not initialized. That is, the pseudo-synchronous pattern signal in the received data block has no effect on the clock
Converted to RZ signal.

FIG. 4 shows a state where the input Manchester signal and the clock signal CK1 are not synchronized in phase. Usually, such a state occurs at the start of reception of the next frame signal. In the figure, generally, a signal such as a normal preamble exists before the synchronization pattern. The clock generation unit 23 can normally perform a certain degree of phase synchronization by using the preamble signal. In this example, the phase of the clock CK1 happens to be, for example, 180 ° ahead of the normal state (−180 °). Equivalent to delay). And this can happen very often in practice. As a result, the phase reference signal DTS in this case is generated in synchronization with the boundary edge of one symbol section, not the middle edge of the one symbol section. Therefore, it cannot be expected that the phase of the clock signal CK1 will be corrected as it is.

However, in the present embodiment, the symbol of the Manchester signal is changed from “0” → “1” (or “1” → “0”).
FF2 is reset (out-of-synchronization state) by utilizing the fact that no edge exists at the boundary of one symbol section and not generating the phase reference signal DTS in this section. That is, an out-of-synchronization state can be effectively detected.

In the preamble signal, "0" →
Even if there is no “1” or “1” → “0” signal pattern,
In this example, a signal pattern of “0” → “1” or “1” → “0” always exists in the synchronization pattern. Therefore, in this case, when the reception of the synchronization pattern starts, FF2
Is surely reset (out of synchronization). Alternatively, the FF 2 may be reset in advance by detecting a noise signal in a frame non-transfer section before receiving this frame.

In any case, the circuit in this case is F
The synchronization pattern is received when F2 = 0 (out of synchronization state). Now, comparing the falling phase of the input Manchester signal with the falling phase of the clock signal CK1, since the falling phase is located at approximately the middle point of one symbol section, each level of the synchronization pattern “LHLHLHLH” cannot be sampled properly. The first synchronization pattern detection unit 21 cannot detect a synchronization pattern.

On the other hand, since the phase of the clock signal CK2 is shifted from the phase of the clock signal CK1 by 90 °, each level of the synchronization pattern "LHLHLHLH" can be properly sampled with a margin, and the second synchronization pattern detecting unit 21 is not shown. The synchronous pattern detection signal SD2
Is output. As a result, the FF2 is set, and a synchronous reset pulse signal RSP is output in synchronization with the rise thereof, whereby the count phase of the variable frequency divider 25 is instantaneously initialized (locked in). This instantaneous pull-in operation is performed by, for example, using the edge pulse signal a that appears first after the generation of the synchronous reset pulse signal RSP as a reference so that the rising edge of the clock signal CK1 occurs at this time. Can be easily performed by adjusting the count phase of

Thereafter, the phase reference signal DTS is generated by generating the edge pulse signal EP at the center of one symbol section in the section of the clock signal CK2 = 1. As a result, FF1 (out-of-synchronization detection signal OSD) is set at the falling edge of the clock CK2 of a new phase, and accordingly, FF2 is set (synchronous state). Subsequent operations may be the same as those described with reference to FIG.

Thus, according to the present embodiment, when the phase between the Manchester signal and the clock signal CK1 fluctuates within a range of ± 90 ° from the normal state, the input synchronization pattern is adjusted by the clock signal CK1. Can be detected. When the phase fluctuates within the range of ± 90 ° to ± 180 °, the input synchronization pattern can be properly detected by the clock signal CK2.

Therefore, no matter how the clock phase fluctuates in advance from the normal state (maximum ± 180 °), the synchronization pattern can be properly detected, and as a result, the clock signal CK can be detected.
1 and CK2 are properly pulled in, and the input Manchester signal is properly adjusted to NRZ based on the clock signal CK1.
Converted to a signal. In the above embodiment, an example of application to a Manchester / NRZ signal conversion circuit has been described. However, the present invention can also be applied to a CMI / NRZ signal conversion circuit that is another biphase code. However, in the CMI code, NR
Bit “0” of Z is a signal level of “01” and NRZ
Is represented by an alternate level of "00" and "11", the edge pulse signal EP is not always obtained at the middle point of one symbol section. Therefore, the out-of-synchronization detection unit 27 cannot be used as it is,
It is possible to detect out-of-sync in other ways.

Further, by applying the present invention (1) to the CMI / NRZ signal conversion circuit, the input CMI / NRZ signal
It goes without saying that the synchronization pattern can be properly detected regardless of how the phase of the signal and the clock signal CK1 fluctuates from the normal state. Although the preferred embodiment of the present invention has been described, it goes without saying that various changes in the configuration, control, and combination of these components can be made without departing from the spirit of the present invention.

[0042]

As described above, according to the present invention, what kind of phase difference (including jitter, duty fluctuation, etc.) exists between an input biphase signal and a clock signal for identifying the input biphase signal. However, since the synchronization pattern can be appropriately detected even when the communication method is used, it greatly contributes to improving the quality of data communication.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating a Manchester / NRZ signal conversion circuit according to an embodiment.

FIG. 3 is an operation timing chart (1) of the Manchester / NRZ signal conversion circuit according to the embodiment.

FIG. 4 is an operation timing chart (2) of the Manchester / NRZ signal conversion circuit according to the embodiment;

FIG. 5 is a diagram illustrating a conventional technique.

[Explanation of symbols]

 DC decoder FF flip-flop OR OR gate circuit SR shift register SS single shot circuit

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akihisa Nakamura 2-2-6 Jomi, Chuo-ku, Osaka-shi, Osaka Fujitsu Kansai Digital Technology Co., Ltd.

Claims (5)

[Claims] A clock generation unit that generates a first clock signal phase-synchronized with one symbol section of an input bi-phase code signal and a second clock signal having a predetermined phase different from the first clock signal; A first synchronization pattern detection unit that detects a predetermined synchronization pattern based on data obtained by sampling a biphase code signal using the first clock signal; and converting the biphase code signal into data sampled using the second clock signal. A second synchronization pattern detection unit for detecting the predetermined synchronization pattern based on the first synchronization pattern; and a first or second synchronization pattern detection unit detecting the predetermined synchronization pattern to initialize a clock generation phase of the clock generation unit. A bi-phase code signal identification device, comprising: 2. The method according to claim 1, wherein both the first and second clock signals have a duty ratio of １ ／, and the phase difference between the first and second clock signals is 90 °. 1
2. The bi-phase code signal identification device according to claim 1. 3. The bi-phase code signal identification device according to claim 1, wherein the bi-phase code signal is a Manchester code signal. 4. An out-of-synchronization detecting section for detecting out-of-synchronization by detecting no edge of the Manchester code signal in a section where the second clock signal is at a predetermined level, and detecting the out-of-synchronization by the out-of-synchronization detecting section. 4. The bi-phase code signal identification device according to claim 3, wherein the initialization function of the initialization control unit is enabled. 5. A noise detection unit for detecting noise based on an input bi-phase code signal, wherein the noise detection unit detects the noise to enable the initialization function of the initialization control unit. 4. The method according to claim 3, wherein
2. The bi-phase code signal identification device according to claim 1.