JPH11331120A - Carrier frequency synchronizing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately synchronize a carrier frequency, even on a phasing transmission line as a carrier frequency synchronizing circuit for orthogonal frequency division multiplex(OFDM) demodulator. SOLUTION: For a carrier frequency synchronizing circuit 10, phase change amounts are respectively detected by phase shift detecting circuits 111 -11L1 , based on plural pilot signals P1-PL1 outputted from a fast Fourier transform(FFT) processor 97, and in the case of finding a frequency correcting amount for synchronism establishment from this detected result, the reception levels of the respective pilot signals P1-PL1 are detected. Based on the detected reception levels, the frequency correcting amount is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a carrier frequency synchronizing circuit, and more particularly to a carrier frequency synchronizing circuit applied to a demodulator for receiving and demodulating a multicarrier signal transmitted by orthogonal frequency division multiplexing. Things.

[0002]

2. Description of the Related Art When transmitting high-speed data having a short bit width in digital wireless communication, a delayed wave that is reflected on a building or the like and arrives at a receiver is received with a delay of several to several tens of symbols. For this reason, interference occurs between symbols and frequency selective fading occurs. Frequency selective fading significantly distorts the received waveform and significantly degrades transmission characteristics. One method of countermeasures against this fading is a method called multicarrier transmission.

[0003] In multicarrier transmission, a transmission mode is adopted in which high-speed data is serial-parallel-converted on the transmitting side to be converted into a plurality of low-speed data having a long bit width, and then a plurality of carrier waves (subcarriers) are modulated and transmitted. On the receiving side, a process of demodulating the received signal of each subcarrier and then performing parallel-to-serial conversion to obtain demodulated data is performed. This prevents the occurrence of intersymbol interference. Here, "Orthogonal Frequency Division Multiplexing (OFDM)"
A method called “ltiplexing” is one method for realizing this multicarrier transmission.

[0004] Regarding the OFDM transmission system, refer to Reference 1 “O
FDM digital transmission system ", Shunji Nakahara, ITU Journal, Vol. 27, No. 1. FIG.
A general configuration showing a relationship between an OFDM modulator and an OFDM demodulator disclosed in the above-mentioned Document 1 is shown. FIG.
, 8 is an OFDM modulator, and 9 is an OFDM demodulator. The OFDM modulator 8 includes a serial-parallel converter 81,
IFFT (Inverse Fast Fourier Transform) processor 82, D /
A converters 83a and 83b, LPF (low-pass filter)
84a, 84b, mixers 85a, 85b, a π / 2 phase shifter 86, a carrier oscillator 87, and an adder 88. The OFDM demodulator 9 includes a BPF (bandpass filter) 91, mixers 92a and 92b, a π / 2 phase shifter 93, a carrier oscillator 94, LPFs 95a and 95b,
Each of the D converters 96a, 96b, and 17 includes an FFT (fast Fourier transform) processor 97 and a parallel-serial converter 98.

[0005] Next, an outline of the OFDM transmission system will be described. FIG. 10 shows a format of a transmission symbol. First, a description will be given using the configuration of the OFDM modulator 8 shown in FIG. In the OFDM modulator 8, FIG.
As shown in (a), N arranged in series (N is a natural number)
The transmission symbols C _{0 to} C _N−1 are rearranged in parallel by the serial / parallel converter 81.

At this time, assuming that the width of the transmission symbols arranged in series is T, the width Ts of the symbols arranged in parallel output from the serial-parallel converter 81 is N ×, as shown in FIG. At T, the symbol width is increased N times. Here, the transmission symbol C _K (k = 0 to N−1) is generally a _k
+ Jb _K , and its phase and amplitude change according to the data to be transmitted. The values of a _K and b _K are different depending on the modulation method to be adopted. For example, in the case of QPSK, the value takes one of ± 1 according to transmission data, and the phase is
/ 4, 3π / 4, -3π / 4, and -π / 4.

The N symbols C _{0 to} C _N−1 output from the serial-to-parallel converter 81 are subjected to inverse Fourier transform processing by an IFFT processor 82, and as a result, the in-phase component I of the transmission baseband signal and An orthogonal component Q is generated. The in-phase component signal I and the quadrature component signal Q output from the IFFT processor 82 are respectively supplied to a D / A converter 83
a, after being converted to an analog signal by 83b, LP
Unnecessary harmonic components are removed by F84a and 84b. L
Output signals from the PFs 84a and 84b are input to mixers 85a and 85b, respectively, and are respectively IF (Intermediate).
te Frequency (intermediate frequency) signal.

The output signal of the LPF 84a is a mixer 85a
Is multiplied by the output signal of the carrier oscillator 87 input to the other input terminal of the mixer 85a. L
The output signal of the PF 84b is, at the mixer 85b, π / 2 input to the other input terminal of the mixer 85b.
The output signal of the phase shifter 86 is multiplied. π / 2 phase shifter 86
Receives the output signal of the carrier oscillator 87 and outputs a signal obtained by shifting the phase of the output signal by π / 2. The signals output from the mixers 85a and 85b are added by an adder 88. The transmission IF signal output from the adder 88 is converted into a desired RF (Radio Frequency) signal by a subsequent-stage frequency conversion circuit (not shown) in the same manner as a general transmitter, and then an antenna (not shown) Sent from.

In the configuration of the OFDM modulator 8 described above,
D / A converters 83a and 83b, LPFs 84a and 84b,
A portion including the mixers 85a and 85b, the π / 2 phase shifter 86, the carrier oscillator 87, and the adder 88 has the same configuration as the quadrature modulator of a general modulator. Therefore,
The characteristic part of the OFDM modulator 8 is that the serial-parallel converter 81
And the IFFT processor 82. Where IFF
The inverse Fourier transform process performed by the T processor 82 is a process of converting a signal on the frequency axis into a signal on the time axis.

Therefore, the N transmission symbol symbols C _{0 to} C _N−1 input to the IFFT processor 82 are
It can be regarded as N signals arranged on the frequency axis.
That is, the modulation processing in the multicarrier transmission that modulates each of N carriers (subcarriers) by the N transmit symbols C ₀ -C _N-1, is realized by IFFT processor 82 by the OFDM method.

FIG. 11 is a diagram showing a spectrum of a transmission IF signal output from the OFDM modulator 8. 11, the modulated N subcarriers W ₀ to _W-N-1 is shown to arranged on the frequency axis by each of N transmit symbols C ₀ ~C _N-1. Here, since the interval between subcarriers becomes as small as 1 / Ts, a feature of the OFDM system is that adjacent subcarriers overlap each other.

Next, the demodulation operation in the OFDM system will be described using the configuration of a general OFDM demodulator 9 shown in FIG. R received by antenna (not shown)
The F signal is converted into a reception IF signal by a frequency conversion circuit (not shown), like a general receiver. The reception IF signal is first input to the BPF 91. This BPF 91 removes unnecessary frequency components included in the received IF signal.

The output signal of the BPF 91 is split into two and input to mixers 92a and 92b, respectively. BPF91
One of the two signals after output from the mixer 92a
Is multiplied by the output signal of the carrier oscillator 94 input to the other input terminal of the mixer 92a. The output signal of the mixer 92a is input to the LPF 15a, where unnecessary harmonic components are removed to become in-phase components of the baseband signal.

The other signal which is branched into two after the output of the BPF 91 is supplied to a mixer 92b.
The product is multiplied by the output signal of the π / 2 phase shifter 93 which is input to the other input terminal of b. The π / 2 phase shifter 93 receives the output signal of the carrier oscillator 94 and outputs a signal obtained by shifting the phase of the output signal by π / 2. Mixer 92
The output signal b is input to the LPF 95b, where unnecessary harmonic components are removed to become orthogonal components of the baseband signal. The output signals of LPFs 95a and 95b are A /
After being input to the D converters 96a and 96b and converted into digital signals, the input is input to the FFT processor 97.

The FFT processor 97 performs a Fourier transform process on the input in-phase component signal I and quadrature component signal Q, and outputs _N demodulated symbols C _{0 to} C _{N -1} . The signal output from the FFT processor 97, that is, the N demodulated symbols arranged in parallel are converted into N demodulated symbols arranged in series by the parallel-serial converter 98, and output from the OFDM demodulator 9.

In the configuration of the OFDM demodulator 9 described above,
BPF 91, mixers 92a and 92b, π / 2 phase shifter 9
3. Carrier oscillator 94, LPFs 95a and 95b and A
The portion composed of the / D converters 96a and 96b is the same as the configuration often employed as a quasi-synchronous detector of a general demodulator. Therefore, the characteristic parts of the OFDM demodulator 9 are the FFT processor 97 and the parallel / serial converter 98.
It is. These two parts allow the OFDM modulator 8
-To-parallel converter 81 and IFFT processor 8 in
The processing reverse to the processing performed in step 2 is performed to reproduce the transmission symbol.

That is, FFT is applied to the IFFT signal.
If the FT processing is performed, the original signal before the IFFT is obtained from the signal after the FFT processing. Therefore, the N demodulated symbols C _{0 to} C _N−1 output from the FFT processor 97 are the transmission symbols C ₀ to It matches C _N-1 . That is, the demodulation process in multicarrier transmission of demodulating N modulated waves is realized by the FFT processor 97 in the OFDM system.

As described above, in the OFDM system, the frequency interval of each subcarrier is 1 / Ts, but this subcarrier interval 1 / Ts is generally as small as about several kHz.
Then, a difference (frequency offset) between the oscillation frequencies of the carrier oscillators 87 and 94 becomes a problem. If an offset exists in the carrier frequency, interference occurs between subcarriers in the OFDM demodulator 9.

[0019] That is, the symbol C _K transmitted in subcarrier k on the transmission side, the carrier frequency offset,
On the receiving side,... K-1, k, k + 1,.
Since the mixed signal also mixes with subcarriers around the original subcarrier k, a plurality of transmission symbols interfere with each other and transmission characteristics are significantly deteriorated. Therefore, OFD
The M demodulator 9 requires a carrier frequency synchronization circuit for matching the oscillation frequency of the carrier oscillator 94 with the oscillation frequency of the carrier oscillator 87, that is, the carrier frequency of the received IF signal.

Therefore, a conventional carrier frequency synchronization circuit will be described. Fig. 12 is a document 2 "Study of a new frequency synchronization method using guard period in OFDM", Takashi Seki, Noboru Taga, Tatsuya Ishikawa, Technical Report of the Institute of Television Engineers of Japan, Vol.19, No.38, pp.13-18 (1995),
FIG. 3 is a configuration diagram of an OFDM demodulator including a conventional carrier frequency synchronization circuit. General OFDM demodulator 9 shown in FIG.
The same parts as those described above are denoted by the same reference numerals and description thereof is omitted.

The OFDM demodulator shown in FIG. 12 is provided with a carrier oscillator 99 for changing the oscillation frequency in place of the above-mentioned carrier oscillator 94, and the oscillation frequency of the carrier oscillator 99 is changed according to the control voltage. A carrier frequency synchronizing circuit 100 is added. The carrier frequency synchronizing circuit 100 delays an input signal by one symbol time (= Ts) and outputs the delayed signal.
Output signals of / D converters 96a and 96b and delay circuit 101
And a phase detection circuit 103 that receives the output signal of the correlator 102 and obtains the correlation value of these signals, and outputs the result, and detects the phase of the signal. A latch 104 for sampling an output signal of the circuit 103 at a symbol period, and a latch 10
L that removes unnecessary noise components from the output signal of No. 4 and outputs
An F (loop filter) 105 is provided. Where L
The output signal of F105 is a voltage for controlling the oscillation frequency of the voltage controlled carrier oscillator 99.

The correlator 102 includes a conjugate circuit 102b for outputting a complex conjugate of the input signal, and A / D converters 96a and 96.
6b and a complex multiplier 102a that outputs a result of complex multiplication of the output signal of the conjugate circuit 102b, and a moving average circuit that obtains a moving average of the output signal of the complex multiplier 102a and outputs the result. 102c.

Next, the carrier frequency synchronization circuit 100
Will be described. In the carrier frequency synchronizing circuit 100 shown in FIG. 12, the output signals (digitized reception baseband signals) of the A / D converters 96a and 96b are each branched into two, and one output signal is input to the correlator 102. The other is input to the delay circuit 101 and is delayed by one symbol time (= Ts). In the correlator 102,
The correlation of the input signal is obtained by the conjugate circuit 102b, the complex multiplier 102a, and the moving average circuit 102c. That is, the currently received baseband signal and Ts
The correlation of the baseband signal received before the time is determined.

Since the carrier frequency synchronization circuit 100 is a circuit utilizing the fact that a repetitive component is inserted into a transmitted baseband signal, the repetitive component inserted into the transmitted baseband signal is used here. The explanation is supplemented. FIG. 13 shows the in-phase component of the transmission baseband signal waveform, and FIG. 14 shows the relationship between the delay of the reception baseband signal and the correlation value. This in-phase component is the output signal waveform of the D / A converter 83a of the OFDM modulator 8 shown in FIG.
This is a signal obtained by converting the output of the A / D converter 16a in the FDM demodulator.

As shown in FIG. 13, the leading portion of the transmission baseband signal has a period called a guard interval having a width of Tg. In this period, the same waveform as the waveform having the width Tg of the trailing portion of the transmission baseband signal is provided. Has been copied and inserted. The portion excluding the guard interval is called an effective symbol. The guard interval is inserted for the purpose of reducing the effect of the delayed wave. The conventional carrier frequency synchronization circuit 100 shown in FIG. 12 is a circuit that synchronizes the carrier frequency by using the point that the waveform of the guard interval is the same as the waveform of the end portion of the effective symbol.

That is, since the waveform of the received guard interval portion and the waveform of the end portion of the effective symbol are the same and show a strong correlation, the received baseband signal is branched into two, and one of them is divided by the time Ts. If the correlation is obtained with a delay, a large correlation output can be obtained every time Ts as shown in FIG. This correlation output includes a carrier frequency offset component as described below. Conventional systems detect this component and synchronize the carrier frequency.

In FIG. 14, the signal rA1 (t) of the guard interval portion A1 of the received baseband signal can be expressed by the following equation (1) when expressed by a complex number.

[0028]

(Equation 1)

Here, ρ (t) is an envelope, and θ (t) is a phase. On the other hand, the signal rA2 (t) of the portion A2 received after the time Ts is a signal obtained by rotating the phase of the same waveform as that of the portion A1 by the carrier frequency offset, and can be expressed by the following equation (2).

[0030]

(Equation 2)

Here, Δf is a carrier frequency offset. The signal represented by the above equation (1) corresponds to the output signal of the delay circuit 101 in the configuration of the carrier frequency synchronization circuit 100, and the signal represented by the above equation (2) is an A / D converter 96.
a, 96b. Conjugate circuit 102
Since the output of b is a complex conjugate signal of the signal of the above equation (1), it becomes the following equation (3).

[0032]

(Equation 3)

Here, * in the above equation (3) represents complex conjugate. Since the output signal of the complex multiplier 102a is a product of the above equations (2) and (3), the following equation (4) is obtained.

[0034]

(Equation 4)

In the above equation (4), the carrier frequency offset Δ
f, the carrier frequency offset Δ
f is detected by a subsequent circuit. Moving average circuit 102c
Takes the average of the input signals for the guard interval period Tg, and the output signal of the moving average circuit 102c is expressed by the following equation (5).

[0036]

(Equation 5)

Here, Y is a value obtained by averaging ρ (t) ² over time Tg, and is substantially constant. The phase detection circuit 103 detects the phase of the signal represented by the above equation (5). Therefore, the output signal of the phase detection circuit 24 is 2π
Since ΔfTs, a signal proportional to the carrier frequency offset Δf is obtained. This 2πΔfTs is used as an error signal for carrier frequency synchronization. This error signal is sampled at the symbol period by the latch 104 because the correlation value is obtained at the time of the peak as shown in FIG.

The output signal of the latch 104 is used as a control voltage of the voltage controlled carrier oscillator 99 after an unnecessary noise component is removed by the LF 105. The voltage control carrier oscillator 99 reduces the output frequency when the control voltage is a positive voltage, and increases the output frequency when the control voltage is a negative voltage. Therefore, Δf
If> 0, the oscillation frequency is corrected to be small, and if Δf <0, the correction is made to be large. Therefore, the error signal indicates the correction amount. In this way, control is performed such that the carrier frequency offset Δf becomes 0, and synchronization of the carrier frequency is established.

[0039]

In the above-described carrier frequency circuit, when fading occurs, the level of the received signal, that is, the received level fluctuates, so that the level of the received level differs for each frequency. This will be described with reference to FIG. FIG. 15 shows the frequency characteristics of a transmission path in which fading has occurred, and the spectrum of a received OFDM signal. In OFDM, the reception level of each subcarrier differs due to fading. That is, in FIG. 15, a signal transmitted on a subcarrier whose frequency characteristic of a transmission path is degraded (in the figure,
(positions a1 and a2), the reception level is reduced, and the reliability is reduced. Conversely, a signal having a large frequency characteristic has a high reception level, so the reliability is high (in the figure,
position of b1, b2, b3).

If it is attempted to synchronize the carrier frequency without considering such a difference, a signal having a small reception level adversely affects the synchronization characteristics. That is, in the conventional carrier frequency synchronization circuit, the carrier frequency is synchronized using the same waveform that is repeatedly transmitted. At this time, since the magnitude of the received signal level due to fading is not taken into account, the synchronization performance is reduced by fading. However, there is a problem in that the metal is deteriorated.

The present invention has been made in order to solve the above problems, and as a carrier frequency synchronizing circuit for an OFDM demodulator, it is possible to accurately synchronize a carrier frequency even in a fading transmission line. It is an object to obtain a simple carrier frequency synchronization circuit.

[0042]

Means for Solving the Problems The above-mentioned problems are solved,
In order to achieve the object, a carrier frequency synchronization circuit according to the present invention performs orthogonal frequency division multiplexing on a transmission side of a signal including L1 (L1 is a natural number) signals serving as a reference for establishing synchronization of a carrier frequency. The receiving side generates a carrier signal, and on the receiving side, in order to establish synchronization of the carrier frequency, a system for correcting the carrier frequency according to the state of the reference L1 signals in the carrier signal generated on the transmitting side is provided. In the carrier frequency synchronization circuit applied and used on the receiving side of the system, a detection for detecting each reception level of the reference L1 signals received at the frequency used by the reference L1 signals. Means and the reference L1
L2 (L2 is a natural number, L2
≦ L1) selecting means for selecting the reference signals; and correcting means for correcting a carrier frequency based on the reference signals selected by the selecting means.

According to the present invention, each reception level of the reference L1 signals received at the frequency used by the reference L1 signals for establishing the synchronization of the carrier frequency is detected, and the detection is performed. L2 (L2 is a natural number, L2 ≦ L1) signals are selected in descending order from the magnitude relation of the received levels, and the carrier frequency is corrected based on the selected signals. Small received signals are excluded from the synchronization process,
High-accuracy frequency synchronization can be achieved even in a fading wireless transmission path.

The carrier frequency synchronizing circuit according to the next invention is characterized in that, on the transmitting side, a plurality of transmission signals are orthogonally frequency-division multiplexed to generate a carrier signal. Applied to a system that corrects the carrier frequency according to the state of a plurality of signals in the carrier signal generated in the above, in the carrier frequency synchronization circuit used on the receiving side of the system, the plurality transmitted from the transmitting side Modulation removing means for removing the modulation of the signals, detecting means for detecting the respective reception levels of the plurality of signals which have been modulated by the modulation removing means, and the detecting means between the plurality of modulated signals. Selecting means for selecting L2 (L2 is a natural number) signals in ascending order from the magnitude relationship of the reception levels detected in step (a), and And correcting means for correcting the carrier frequency based on the selected signal-option means, characterized by comprising a.

According to the present invention, a plurality of signals sent from the transmitting side are subjected to modulation removal, and the respective reception levels of the plurality of modulation-removed signals are detected. Since L2 (L2 is a natural number) signals are selected in descending order and the carrier frequency is corrected based on the selected signals, a received signal having a small reception level under fading is excluded from synchronization processing, and fading is performed. It is possible to achieve high-precision frequency synchronization even in a wireless transmission path with a channel, and since all received signals that are unmodulated signals are used, all received power can be used without waste. This is effective when the desired frequency synchronization accuracy cannot be obtained at least.

In a carrier frequency synchronizing circuit according to the next invention, the correction means includes an adder for adding the signal selected by the selection means, and a carrier wave frequency detecting means for detecting a phase of a signal based on an addition result of the adder. And a phase detection circuit for obtaining a correction amount for correcting

According to the present invention, when correcting the carrier frequency, the adder adds up the signals obtained by the selection, and the phase detection circuit detects the phase of the signal based on the addition result of the adder to change the carrier frequency. Since the correction amount for the correction is obtained, the carrier frequency can be corrected using only the selected signal.

In the carrier frequency synchronizing circuit according to the next invention, the transmitting side performs orthogonal frequency division multiplexing on a signal including L1 (L1 is a natural number) signals, which is used as a reference for establishing synchronization of the carrier frequency. The present invention is applied to a system that generates a signal and corrects a carrier frequency according to a state of the reference L1 signals in the carrier signal generated on the transmitting side for establishing synchronization of the carrier frequency on the receiving side. Detecting means for detecting each reception level of the reference L1 signals received at a frequency used by the reference L1 signals in a carrier frequency synchronization circuit used on the receiving side of the system; , The reference L1
Extracting means for extracting a signal whose reception level detected by the detecting means is equal to or higher than a certain level, and correcting means for correcting a carrier frequency based on the reference signal extracted by the extracting means And characterized in that:

According to the present invention, each reception level of the reference L1 signals received at the frequency used by the reference L1 signals for establishing the synchronization of the carrier frequency is detected, and the reception level is determined. By extracting signals above a certain level,
Since the carrier frequency is corrected based on the extracted signal, a reception signal having a reception level equal to or lower than a certain level under the fading is eliminated from the synchronization processing, and thus, even in a radio transmission path with fading, the accuracy is improved. High frequency synchronization can be achieved.

In the carrier frequency synchronizing circuit according to the next invention, the transmitting side generates a carrier signal by orthogonal frequency division multiplexing of a plurality of transmission signals, and the receiving side performs synchronization of the carrier frequency by the transmitting side. Applied to a system that corrects the carrier frequency according to the state of a plurality of signals in the carrier signal generated in the above, in the carrier frequency synchronization circuit used on the receiving side of the system, the plurality transmitted from the transmitting side Modulation removing means for removing the modulation of the signal, detecting means for detecting each reception level of the plurality of signals which have been modulated by the modulation removing means, and detecting the signal among the plurality of modulated signals. Extracting means for extracting a signal whose reception level detected by the means is equal to or higher than a predetermined level, and extracting the signal based on the signal extracted by the extracting means from among the plurality of modulation-removed signals. Characterized by comprising a correction means for correcting the carrier frequency, the.

According to the present invention, a plurality of signals sent from the transmitting side are subjected to modulation removal, the respective reception levels of the plurality of signals subjected to the modulation removal are detected, and the reception level is equal to or higher than a certain level. , And the carrier frequency is corrected based on the extracted signal, so that the received signal having the reception level below a certain level under the fading is excluded from the synchronization processing, and the fading radio transmission path is used. It is possible not only to achieve high-precision frequency synchronization in, but also to use all received signals that are unmodulated signals, so that all received power can be used without waste.
This is effective when a desired frequency synchronization accuracy cannot be obtained due to a small number of pilot signals.

In the carrier frequency synchronizing circuit according to the next invention, the correction means includes an adder for adding the signal extracted by the extraction means, and a carrier wave frequency detecting means for detecting the phase of the signal based on the addition result of the adder. And a phase detection circuit for obtaining a correction amount for correcting

According to the present invention, when correcting the carrier frequency, the adder adds the signals obtained by the extraction, and
The phase detection circuit detects the phase of the signal based on the addition result of the adder and obtains a correction amount for correcting the carrier frequency, so that the carrier frequency can be corrected using only the extracted signal. is there.

In the carrier frequency synchronizing circuit according to the next invention, the extraction means turns on the output when the reception level detected by the detection means is above a certain level, and turns off the output when the reception level is below the certain level. It is characterized by having.

According to the present invention, at the time of extraction, the signal output is turned on when the level is equal to or higher than a certain level by the switch,
Since the signal output is turned off when the signal level does not reach the certain level, a signal having a required reception level can be easily extracted by on / off control.

The carrier frequency synchronizing circuit according to the next invention is characterized in that the transmitting side performs orthogonal frequency division multiplexing on a signal including L1 (L1 is a natural number) signals to be used as a reference for establishing synchronization of the carrier frequency. The present invention is applied to a system that generates a signal and corrects a carrier frequency according to a state of the reference L1 signals in the carrier signal generated on the transmitting side for establishing synchronization of the carrier frequency on the receiving side. Detecting means for detecting each reception level of the reference L1 signals received at a frequency used by the reference L1 signals in a carrier frequency synchronization circuit used on the receiving side of the system; , The reference L1
Weighting means for adding a weight corresponding to the level of the reception level detected by the detection means to each of the signals, and correction for correcting the carrier frequency based on a reference signal weighted by the weighting means Means.

According to the present invention, each reception level of the reference L1 signals received at the frequency used by the reference L1 signals is detected, and the reception level of each of the reference L1 signals is detected. A weight corresponding to the magnitude of the detected reception level is added, and the carrier frequency is corrected based on the weighted reference signal, so that the influence of a pilot signal having a small reception level during synchronization processing is reduced. Accordingly, highly accurate frequency synchronization can be achieved even in a fading wireless transmission path.

The carrier frequency synchronizing circuit according to the next invention is characterized in that a transmitting side generates a carrier signal by orthogonal frequency division multiplexing of a plurality of transmission signals, and a receiving side for establishing the synchronization of the carrier frequency. Applied to a system that corrects the carrier frequency according to the state of a plurality of signals in the carrier signal generated in the above, in the carrier frequency synchronization circuit used on the receiving side of the system, the plurality transmitted from the transmitting side Modulation removing means for removing the modulation of the signal, detecting means for detecting each reception level of the plurality of signals which have been modulated by the modulation removing means, and each of the plurality of signals which have been modulated by the modulation removing means Weighting means for adding a weight corresponding to the magnitude of the reception level detected by the detection means, and carrying the signal based on the signal weighted by the weighting means. And correcting means for correcting the wave frequency,
It is characterized by having.

According to the present invention, a plurality of signals sent from the transmitting side are subjected to modulation removal, the respective reception levels of the plurality of signals subjected to the modulation removal are detected, and the reception level is reduced. Since a corresponding weight is added and the carrier frequency is corrected based on the weighted signal,
It is possible to reduce the influence of the pilot signal having a small reception level at the time of the synchronization process, and it is possible to achieve high-accuracy frequency synchronization even in a fading radio transmission path. Since all received power can be used without waste because it is used, it is effective when the number of pilot signals is small and desired frequency synchronization accuracy cannot be obtained.

In the carrier frequency synchronizing circuit according to the next invention, the correction means includes an adder for adding the signals weighted by the weighting means, and a carrier wave frequency detecting means for detecting the phase of the signal based on the addition result of the adder. And a phase detection circuit for obtaining a correction amount for correcting

According to the present invention, when correcting the carrier frequency, the adder adds the signals obtained by the weighting, and the phase detection circuit detects the phase of the signal based on the addition result of the adder to change the carrier frequency. Since the correction amount for the correction is obtained, the carrier frequency can be corrected according to the weight of each signal.

[0062]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a carrier frequency synchronization circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 First, the configuration will be described. FIG. 1 is a block diagram showing a configuration example of an OFDM demodulator according to Embodiment 1 of the present invention.
Indicates an OFDM demodulator according to the first embodiment. FIG.
In the figure, the same parts as those in the conventional example are denoted by the same reference numerals, and description thereof will be omitted. The OFDM demodulator 1 shown in FIG.
The overall configuration of the FDM demodulator includes a carrier frequency synchronization circuit 10 in place of the carrier frequency synchronization circuit 100. The carrier frequency synchronization circuit 10 controls the voltage of the carrier oscillator 99 to establish the synchronization of the carrier frequency, similarly to the above-described carrier frequency synchronization circuit 100 (see FIG. 9). The connection relationship of the carrier frequency synchronization circuit 10 is different from that of the above-described carrier frequency synchronization circuit 100 in that the carrier frequency synchronization circuit 10 is connected to the output of the FFT processor 97.

Specifically, in the OFDM system,
A pilot signal (generally, an unmodulated pilot symbol) may be transmitted using a specific plurality of subcarriers. Unmodulated pilot symbols are all “0”
Alternatively, it means a symbol composed of data that does not change with time, such as all “1”. Carrier frequency synchronization circuit 1
Numeral 0 denotes a circuit for synchronizing the carrier frequency using a plurality of pilot signals sent from the transmitting side. In FIG. 1, among the N outputs of the FFT processor 97, L1 outputs up to P1, P2,..., PL1 indicated by bold lines represent received pilot signals. The number L1 of pilot signals differs depending on the system, but is usually several to several tens.

As shown in FIG. 1, for example, as shown in FIG. 1, the carrier frequency synchronizing circuit 10 is provided for each of the L1 pilot signals, and detects each phase shift amount from the L1 received pilot signals. Phase shift detection circuits 11 _{1 to} 11 _L1 , a selector 12 for selecting a predetermined number of phase shifts having a large reception level, a selection control circuit for instructing the output of the phase shift detection circuit to be selected by the selector 12 from the received pilot signal 13, an adder 14 for adding the selected phase shift amount, a phase detection circuit 15 for detecting a phase from the added phase shift amount, and an LF 16 for removing noise from the detected phase. Each phase shift detector circuit 11 ₁ to 11 _L1 is configured with a delay detection circuit 11a for detecting a phase shift amount of the corresponding received pilot signal by a level detecting circuit 11b for detecting the reception level from the reception pilot signal corresponding Is done.

Here, the transmission format of the OFDM system will be described. FIG. 2 is a diagram illustrating a format example of a transmission frame used in the OFDM scheme. As shown in FIG. 2, the format of the transmission frame includes null symbols, data, pilot symbols, and data. An unmodulated null symbol is inserted as the first symbol. This position corresponds to the position of the demodulated symbol C _0. After that, data is inserted. Embodiment 1
Since the data sequence of the pilot signal is known, the position of the pilot symbol is known. Therefore, the positions of the pilot symbols are the demodulated symbols C ₁ , C ₄ .
It corresponds to the position of _N-2 . Demodulated symbols C ₁ , C ₄ ... C _N-2
., PL1 at the positions
Is applicable.

Next, the operation will be described. In the carrier frequency synchronization circuit shown in FIG. 1, each phase-shifting circuits 11 ₁ to 11 _L1, each pilot signal output is inputted from the FFT processor 97, together with the phase shift of the pilot signal is detected, respectively, The level of each pilot signal is detected. That is, the delay detection circuit 11a detects the phase shift amount from the corresponding received pilot signal, and the level detection circuit 11b detects the reception level from the corresponding received pilot signal.

The L1 phase shift amounts thus detected are input to the selector 12. Also, L1 amino reception level detected by the level detecting circuit 11b of the phase-shift detector circuit 11 ₁ to 11 _L1 is input to the selection control circuit 13. The selection control circuit 13 selects a selection signal for selecting the upper L2 signals (phase shift amounts) having a higher detection level from the L1 input signals (reception levels).
Output to 2. Here, L2 ≦ L1 is set.

The selector 12 selects L2 phase shift amounts in accordance with the selection signal output from the selection control circuit 13, and outputs the selected L2 phase shift amounts to the adder 14 at the subsequent stage. The adder 14 adds the input L2 signals (phase shift amounts), and outputs the addition result to the phase detection circuit 15. In the phase detection circuit 15, a phase is detected from the output signal of the adder 14, and the phase is used as a control voltage of the voltage-controlled carrier wave oscillator 99 after an unnecessary noise component is removed by the LF 16.

Subsequently, the phase shift detection circuits 11 ₁ to 11 ₁
1 _L1 will be specifically described. Represented as the following equation (6) representing each pilot signal P1, P2 ... PL1 is input to the delay detection circuit 11a of each phase-shift detector circuit 11 ₁ to 11 _L1 by a complex number. However, for the sake of simplicity, noise superimposed on the transmission path is excluded.

[0071]

(Equation 6)

Here, ρi and θi are the envelope and the phase of the received pilot signal, respectively. ρi represents the reception level of each pilot signal, and becomes different in each pilot signal under the influence of fading as shown in FIG.

Since the delay detection circuit 11a delay-detects the input signal for each symbol (every Ts time) and outputs the result, if the phase fluctuation due to fading is sufficiently small, the output of the delay detection circuit 11a is assumed. The signal is represented by the following equation (7).

[0074]

(Equation 7)

As can be seen from the above equation (7), the output signal of each delay detection circuit 11a includes a carrier frequency offset component Δf. What is necessary is just to detect this Δf and correct the carrier frequency offset, but as described above, the magnitude of ρi differs for each pilot signal. Then, since the S / N ratio (signal-to-noise power ratio) differs for each pilot, the accuracy of detected Δf differs for each pilot. That is, if a received pilot signal having a small value of ρi and a poor SN ratio is used, the detection accuracy of Δf decreases. In the circuit configuration of the first embodiment, the difference in the reception level due to the fading is considered, and the frequency is corrected using only the pilot signal having the highest reception level as much as possible. Synchronize with high accuracy.

For this purpose, each phase shift detection circuit 11 ₁
-11 _L1 has a level ρi ² (i = 1, 2, ²⁾ of the output signal of the pair of differential detection circuits 11a.
.., PL1) are detected. Therefore, the selection control circuit 13 selects the upper L2 having a higher level from ρi ² (i = 1, 2,..., PL1) and outputs the selection result to the selector 12. The selector 12 selects and outputs only the delay detection result for the upper L2 pilot signals having the higher reception level based on the selection result. Where L2 and L
1 is set to L2 ≦ L1, a received pilot signal having a small reception level and a poor SN ratio is selected by the selector 1
2 can be eliminated. The output signal of the adder 14 is given by the following equation (8).

[0077]

(Equation 8)

Here, R is a value obtained by summing the magnitudes ρi ² of the selected L2 differential detection results. The phase detection circuit 15 after the adder 14 detects and outputs the phase 2πΔfTs from the input signal represented by the above equation (8).
Does not include a pilot signal whose reception level has dropped due to fading, the S / N ratio of the output signal of the phase detection circuit 15 is large, and the accuracy of frequency offset correction is high.

As described above, according to the first embodiment, when detecting the phase shift of each received pilot signal, each level is detected by the level detection circuit.
Based on this detection result, only the received signal (pilot signal) having a large SN ratio is selected to establish synchronization. Therefore, a received signal having a small reception level under fading is excluded from the synchronization processing. High-accuracy frequency synchronization can be achieved even in a fading wireless transmission path.

When correcting the carrier frequency, the adder 14 adds the pilot signal obtained by the selection of the selector 12, and the phase detection circuit 15 detects the phase of the pilot signal based on the addition result of the adder 14. Thus, a correction amount for correcting the carrier frequency is obtained, so that the carrier frequency can be corrected using only the selected pilot signal.

Embodiment 2 By the way, in Embodiment 1 described above, the number of pilot signals selected for phase detection is fixed at L2, but the present invention is not limited to this, and as in Embodiment 2 described below. The number of pilot signals used may be changed according to the reception level.

First, the configuration will be described. FIG. 3 is a block diagram showing a configuration example of the OFDM demodulator according to the second embodiment of the present invention. In FIG. 3, reference numeral 2 denotes an OFDM demodulator according to the second embodiment. This OFDM demodulator 2 has the same overall configuration as the OFDM demodulator 1 according to the above-described first embodiment, and the OFDM demodulator 1 is transmitted from the carrier frequency synchronization circuit 10 to the carrier frequency synchronization circuit 20. The difference is in the replaced part. Therefore, in the OFDM demodulator 2, the same components as those of the OFDM demodulator 1 are denoted by the same reference numerals, and description thereof will be omitted.

The carrier frequency synchronizing circuit 20 differs from the above-described carrier frequency synchronizing circuit 10 in the configuration of the preceding stage of the adder 14 including the phase shift detecting circuit. That is, the carrier frequency synchronization circuit 20, the adder from the preceding 14 eliminating the selector 12 and the selection control circuit 13, a phase shift detector circuit 21 in place of the phase shift detector circuit 11 ₁ to 11 _L1
Only _{1 to} 21 _L1 are provided.

[0084] phase-shift detector circuit 21 ₁ through 21 _L1 is connected to the demodulator output or the pilot signal output corresponding to the same manner as the phase shift detector circuit 11 ₁ to 11 _L1 described above. Each of the phase shift detection circuits 21 _{1 to} 21 _L1 is, for example, as shown in FIG. 3, a delay detection circuit 21a for detecting a phase shift amount of a corresponding reception pilot signal, and a level for detecting a reception level from the corresponding reception pilot signal. Detection circuit 21b, control circuit 21 for determining validity / invalidity of the pilot signal according to the reception level of the pilot signal
c and a switch 21d for switching the output / non-output of the pilot signal according to the control of the control circuit 21c. Here, the control circuit 21c outputs a control signal for turning on the switch 21d when the level detected by the level detection circuit 21b is equal to or higher than a predetermined value. 21d off
A control signal is output for setting

Next, only operations different from those of the first embodiment will be described. FIG. 4 is a diagram for explaining a method of removing a received signal having a small reception level in a fading transmission path. FIG. 4 shows the same state as FIG. 15 described above. In the carrier frequency synchronizing circuit 20, the operations of the delay detection circuit 21a and the level detection circuit 21b are the same as the operations described in the above-described first embodiment, and a description thereof will be omitted. The control circuit 21c is connected to the output of the level detection circuit 102 and the input of the switch 21d.
And outputs a control signal for switching ON / OFF of the switch 21d based on the output signal.

In FIG. 4, a signal transmitted on a subcarrier whose frequency characteristic of the transmission path is degraded (a
1, (a2)), the reception level becomes smaller. This a
In the case of establishing synchronization including the portions at the positions 1 and a2,
Although the reliability is reduced, T
If H is determined, the control circuit 21c switches the switch 21d based on the predetermined value TH to eliminate pilot signals (reception signals C ₁ and c2 in FIG. 4) whose reception level does not reach the predetermined value. Can be. Switch 21d
Is input to the adder 14. Subsequent processing is the same as in the first embodiment, and a description thereof will not be repeated.

As described above, according to the second embodiment, only pilot signals having a reception level equal to or higher than a predetermined value are extracted under fading, and pilot signals having reception levels equal to or lower than a predetermined value are synchronized. Since the processing is excluded from the processing, the above-described first embodiment is also used in this case.
Similarly to the above, it is possible to achieve highly accurate frequency synchronization even in a fading wireless transmission path.

The second embodiment is effective in a case where the transmission path characteristics change greatly and the value of the number L2 of pilot signals to be selected cannot be fixed.

In addition, when correcting the carrier frequency, the adder 14 adds the signals obtained by extracting the phase shift detection circuits 21 _{1 to} 21 _L1 , and the phase detection circuit 15 adds the signal based on the addition result of the adder 14. Is detected to obtain a correction amount for correcting the carrier frequency, so that the carrier frequency can be corrected using only the extracted pilot signal.

Further, each of the phase shift detecting circuits 21 _{1 to} 21 _{1
In L1} , at the time of extraction, the switch 21d turns on the signal output when the value is equal to or more than a predetermined value, and turns off the signal output when the value is less than the predetermined value. It is possible to extract a signal having a required reception level.

Embodiment 3 In the first embodiment, the number of pilot signals selected for phase detection is fixed at L2. However, the present invention is not limited to this. Instead of using all the pilot signals, weights may be added to the pilot signals according to the reception level.

First, the configuration will be described. FIG. 5 is a block diagram showing a configuration example of the OFDM demodulator according to the third embodiment of the present invention. In FIG. 5, reference numeral 3 denotes an OFDM demodulator according to the third embodiment. The OFDM demodulator 3 has the same overall configuration as the OFDM demodulator 1 according to the above-described first embodiment, and the OFDM demodulator 1 is connected to the carrier frequency synchronization circuit 30 from the carrier frequency synchronization circuit 10. The difference is in the replaced part. Therefore, in the OFDM demodulator 3, the same components as those of the OFDM demodulator 1 are denoted by the same reference numerals, and description thereof will be omitted.

The carrier frequency synchronizing circuit 30 differs from the above-described carrier frequency synchronizing circuit 10 in the configuration of the preceding stage of the adder 14 including the phase shift detecting circuit. That is, the carrier frequency synchronization circuit 30, the adder from the preceding 14 eliminating the selector 12 and the selection control circuit 13, a phase shift detector circuit 31 in place of the phase shift detector circuit 11 ₁ to 11 _L1
It is provided only ₁ to 31 _L1.

[0094] phase-shift detector circuit 31 ₁ to 31 _L1 is connected to the demodulator output or the pilot signal output corresponding to the same manner as the phase shift detector circuit 11 ₁ to 11 _L1 described above. Each of the phase shift detection circuits 31 _{1 to} 31 _L1 is, for example, as shown in FIG. 5, a delay detection circuit 31a for detecting a phase shift amount of a corresponding received pilot signal, and a level for detecting a reception level from the corresponding received pilot signal. A coefficient setting circuit 31c connected to the outputs of the detection circuit 31b and the level detection circuit 31b for setting a weight coefficient for the pilot signal in accordance with the reception level with respect to the pilot signal; and a weighting coefficient set by the coefficient setting circuit 31c for the pilot signal. And a multiplier 21d for multiplying by.

Next, only operations different from those of the first embodiment will be described. Carrier frequency synchronization circuit 30
In the description, the operations of the delay detection circuit 31a and the level detection circuit 31b are the same as the operations described in the first embodiment, and the description is omitted. The coefficient setting circuit 31c sets a weight coefficient for multiplying the output signal of the delay detection circuit 31a by the multiplier 31d based on the output signal of the level detection circuit 31b. Specifically, the coefficient setting circuit 31c sets a weight coefficient proportional to the reception level detected by the level detection circuit 31b. That is, if the detected reception level is high, a large weighting factor is set, and if the detected reception level is low, a small weighting factor is set. Therefore, a large weighting factor is multiplied by the output of the delay detection circuit 31a for a pilot signal having a high reception level, but a small weighting factor is multiplied when the reception level is low. As a result, in the adder 14, the contribution of the pilot signal having a low reception level is reduced.

As described above, the multiplier 31d multiplies the output signal of the delay detection circuit 31a by the weight coefficient set by the coefficient setting circuit 31c. The output of the multiplier 31d is input to the adder 14. Subsequent processing is the same as in the first embodiment, and a description thereof will not be repeated.

As described above, according to the third embodiment, a large weight is added to a pilot signal having a high reception level under fading, while a small weight is added to a small pilot signal. Therefore, the influence of the pilot signal having a small reception level during the synchronization processing is reduced. In this case as well, as in the first embodiment,
High-accuracy frequency synchronization can be achieved even in a fading wireless transmission path.

[0098] The third embodiment is effective when the transmission path characteristics greatly change and the value of the number L2 of pilot signals to be selected cannot be fixed.

At the time of correcting the carrier frequency, the adder 14 adds the pilot signals obtained by weighting the phase shift detection circuits 31 _{1 to} 31 _L1 and adds the pilot signals.
Since the correction amount for correcting the carrier frequency is obtained by detecting the phase of the signal based on the addition result of the adder 14, the carrier frequency can be corrected according to the weighting of each signal.

Embodiment 4 By the way, in Embodiment 1 described above, synchronization is established from a plurality of known pilot signals. However, the present invention is not limited to this.
As in the fourth embodiment described below, synchronization may be established using all outputs (received signals) of the FFT processor 97.

First, the configuration will be described. FIG. 6 is a block diagram showing one configuration example of the carrier frequency synchronization circuit according to the fourth embodiment of the present invention. In FIG. 6, reference numeral 4 denotes an OFDM demodulator according to the fourth embodiment. This OFDM
The demodulator 4 has the same overall configuration as the OFDM demodulator 1 according to the first embodiment described above.
The difference from the demodulator 1 is that the carrier frequency synchronization circuit 10 is replaced with a carrier frequency synchronization circuit 40. Therefore, in the OFDM demodulator 4, the same components as those of the OFDM demodulator 1 are denoted by the same reference numerals, and description thereof will be omitted.

In the carrier frequency synchronizing circuit 40, the above-mentioned carrier frequency synchronizing circuit 10 is different from the FFT processor 97.
Are used, and the phase shift detection circuits 11 ₁ to 11 ₁ are used.
The difference is that modulation elimination circuits 41 _{1 to} 41 _N are provided at the preceding stage of 1 _N respectively. Other parts are the same as those of the first embodiment.
Since it is the same as that of FIG. In the fourth embodiment, not the subject of only a synchronization pilot signal, since it is intended for all received signals, the phase shift detector circuit is the N available until 11 ₁ to 11 _N . However, with respect to the phase shift detector circuit 11 ₁ to 11 _N, for its internal structure and function is similar to the phase shift detector circuit of the first embodiment described above.

The modulation removal circuits 41 _{1 to} 41 _N remove the modulation components of the input signal from the FFT processor 97. There are various methods for removing the modulation component, for example,
If the modulation scheme of each subcarrier is BPSK, the input signal may be squared, and if QPSK, the input signal may be squared.
Alternatively, after performing data determination, a method of removing a change in a received signal point due to data based on the determination data may be used. By employing such a method, each output signal of the modulation removal circuits 41 _{1 to} 41 _N does not include a modulation component,
Input signal of the phase shift detector circuit 11 ₁ to 11 _N are the same processing as in the first embodiment described above in a non-modulation signal becomes possible.

As described above, according to the fourth embodiment, it is possible to achieve high-precision frequency synchronization even in a fading radio transmission path from the same configuration as in the first embodiment. Modulation removal circuit 41 ₁
By adding the configuration of to 41 _N, the total received power because it uses all the received signals from the ability to use without waste, it is effective when the number of pilot signals is less desired frequency synchronization accuracy is not obtained.

Embodiment 5 FIG. In the second embodiment described above, synchronization is established from a plurality of known pilot signals. However, the present invention is not limited to this.
As in the fifth embodiment described below, synchronization may be established using all outputs (received signals) of the FFT processor 97.

First, the configuration will be described. FIG. 7 is a block diagram showing a configuration example of the carrier frequency synchronization circuit according to the fifth embodiment of the present invention. In FIG. 7, reference numeral 5 denotes an OFDM demodulator according to the fifth embodiment. This OFDM
The demodulator 5 has the same overall configuration as the OFDM demodulator 2 according to the second embodiment described above.
The demodulator 2 is different from the demodulator 2 in that the carrier frequency synchronization circuit 20 is replaced with a carrier frequency synchronization circuit 50. Therefore, in the OFDM demodulator 5, the same components as those of the OFDM demodulator 2 are denoted by the same reference numerals, and description thereof will be omitted.

In the carrier frequency synchronizing circuit 50, the above-described carrier frequency synchronizing circuit 20 is different from the FFT processor 97.
Are used, and the phase shift detection circuits 21 ₁ to 21 2 are used.
The difference is that modulation elimination circuits 51 _{1 to} 51 _N are provided at the preceding stage of 1 _N , respectively. Other parts are the same as those of the second embodiment.
Since it is the same as that of FIG. In the fifth embodiment, since only the pilot signal is not subjected to the synchronization processing and all the received signals are targeted, _N phase shift detection circuits 21 _{1 to} 21 N are prepared. . However, with respect to the phase shift detector circuit 21 ₁ through 21 _N, for its internal structure and function is similar to the phase shift detector circuit of the second embodiment described above.

The modulation removal circuits 51 _{1 to} 51 _N remove the modulation components of the input signal from the FFT processor 97. There are various methods for removing the modulation component, for example,
If the modulation scheme of each subcarrier is BPSK, the input signal may be squared, and if QPSK, the input signal may be squared.
Alternatively, after performing data determination, a method of removing a change in a received signal point due to data based on the determination data may be used. By adopting such a method, each output signal of the modulation removal circuits 51 _{1 to} 51 _N does not include a modulation component,
The input signals of the phase shift detection circuits 21 _{1 to} 21 _N are non-modulated signals, so that the same processing as in the second embodiment can be performed.

As described above, according to the fifth embodiment, it is possible to achieve high-precision frequency synchronization even in a fading radio transmission path from a configuration similar to that of the second embodiment. Modulation removal circuit 51 ₁
By adding the configuration of to 51 _N, the total received power because it uses all the received signals from the ability to use without waste, it is effective when the number of pilot signals is less desired frequency synchronization accuracy is not obtained.

Embodiment 6 FIG. By the way, in Embodiment 3 described above, synchronization is established from a plurality of known pilot signals, but the present invention is not limited to this.
As in Embodiment 6 described below, synchronization may be established using all outputs (received signals) of the FFT processor 97.

First, the configuration will be described. FIG. 8 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to Embodiment 6 of the present invention. In FIG. 8, reference numeral 6 denotes an OFDM demodulator according to the sixth embodiment. This OFDM
The demodulator 6 has the same overall configuration as the OFDM demodulator 3 according to the third embodiment described above.
The difference from the demodulator 3 is that the carrier frequency synchronization circuit 30 is replaced by a carrier frequency synchronization circuit 60. Therefore, in the OFDM demodulator 6, the same components as those of the OFDM demodulator 3 are denoted by the same reference numerals, and description thereof will be omitted.

In the carrier frequency synchronizing circuit 60, the above-mentioned carrier frequency synchronizing circuit 30 is different from the FFT processor 97.
Are used, and the phase shift detection circuits 31 _{1 to} 3 ₁
The difference is that modulation elimination circuits 61 _{1 to} 61 _N are provided at the preceding stage of 1 _N , respectively. Other parts are the same as those of the third embodiment.
Since it is the same as that of FIG. In the sixth embodiment, since only pilot signals are not subjected to synchronization processing but all received signals are targeted, _N phase shift detection circuits 31 _{1 to} 31 N are prepared. . However, the internal configurations and functions of the phase shift detection circuits 31 _{1 to} 31 _N are the same as those of the above-described phase shift detection circuit of the third embodiment.

The modulation removing circuits 61 _{1 to} 61 _N remove the modulated components of the input signal from the FFT processor 97. There are various methods for removing the modulation component, for example,
If the modulation scheme of each subcarrier is BPSK, the input signal may be squared, and if QPSK, the input signal may be squared.
Alternatively, after performing data determination, a method of removing a change in a received signal point due to data based on the determination data may be used. By adopting such a method, each output signal of the modulation removal circuit 61 ₁ to 61 _N does not include the modulation component,
The input signals of the phase shift detection circuits 31 _{1 to} 31 _N are non-modulated signals, and the same processing as in the third embodiment can be performed.

As described above, according to the sixth embodiment, it is possible to achieve high-accuracy frequency synchronization even in a fading radio transmission path from a configuration similar to that of the third embodiment. Modulation removal circuit 61 ₁
By adding the configuration of to 61 _N, the total received power because it uses all the received signals from the ability to use without waste, it is effective when the number of pilot signals is less desired frequency synchronization accuracy is not obtained.

Although the present invention has been described with reference to the first to sixth embodiments, various modifications are possible within the scope of the gist of the present invention, and these are not excluded from the scope of the present invention.

[0116]

As described above, according to the present invention,
Detecting each reception level of the reference L1 signals received at the frequency used by the reference L1 signals for establishing the synchronization of the carrier frequency, and increasing the detected reception levels based on the magnitude relation of the detected reception levels. Since L2 (L2 is a natural number) signals are selected in order and the carrier frequency is corrected based on the selected signals, a received signal having a small reception level under the fading is excluded from the synchronization processing. In addition, there is an effect that a carrier frequency synchronization circuit capable of achieving high-accuracy frequency synchronization even in a fading wireless transmission path is obtained.

According to the next invention, a plurality of signals sent from the transmitting side are subjected to modulation removal, the respective reception levels of the plurality of modulated signals are detected, and the magnitude relation of the reception levels is detected. L2 (L2 is a natural number, L2
.Ltoreq.L1) signals are selected and the carrier frequency is corrected based on the selected signals. Therefore, a received signal having a low reception level under fading is excluded from the synchronization processing, and a fading radio transmission path is used. In addition, it is possible to achieve high-precision frequency synchronization, as well as use all received signals that are unmodulated signals, so that all received power can be used without waste. When the synchronization accuracy cannot be obtained, an effective carrier frequency synchronization circuit can be obtained.

According to the next invention, when correcting the carrier wave frequency, the adder adds up the signals obtained by the selection, and the phase detection circuit detects the phase of the signal based on the addition result of the adder to obtain the carrier wave frequency. Is obtained, so that a carrier frequency synchronizing circuit capable of correcting the carrier frequency using only the selected signal is obtained.

According to the next invention, each reception level of the reference L1 signals received at the frequency used by the reference L1 signals for establishing the synchronization of the carrier frequency is detected, and the reception level is detected. Extracted a signal of a certain level or higher and corrected the carrier frequency based on the extracted signal, so that a received signal having a reception level of a certain level or less under fading is excluded from the synchronization processing,
As a result, there is an effect that a carrier frequency synchronization circuit capable of achieving high-accuracy frequency synchronization even in a fading wireless transmission path is obtained.

According to the next invention, a plurality of signals sent from the transmitting side are subjected to modulation removal, and the reception levels of the plurality of signals subjected to the modulation removal are detected so that the reception level becomes a fixed level. Since the above signal was extracted and the carrier frequency was corrected based on the extracted signal,
Reception signals with a reception level below a certain level under fading are excluded from the synchronization processing, and it is possible to achieve high-precision frequency synchronization even in a radio transmission path with fading, as well as all unmodulated signals. Since the received signal is used, the entire received power can be used without waste. Therefore, when the number of pilot signals is small and a desired frequency synchronization accuracy cannot be obtained, an effective carrier frequency synchronization circuit can be obtained.

According to the next invention, when correcting the carrier wave frequency, the adder adds the signals obtained by the extraction, and the phase detection circuit detects the phase of the signal based on the addition result of the adder to detect the carrier wave frequency. Is obtained, so that a carrier frequency synchronizing circuit capable of correcting the carrier frequency using only the extracted signal is obtained.

According to the next invention, at the time of extraction, a switch is used to turn on the signal output when the level is equal to or higher than a certain level, and to turn off the signal output when the level is lower than the certain level. There is an effect that a carrier frequency synchronizing circuit capable of easily extracting a signal having a required reception level by on / off control is obtained.

According to the next invention, each reception level of the reference L1 signals received at the frequency used by the reference L1 signals is detected, and the reception level of each of the reference L1 signals is detected. Weight is added according to the magnitude of the detected reception level, and the carrier frequency is corrected based on the weighted reference signal. This makes it possible to obtain a carrier frequency synchronization circuit capable of achieving high-accuracy frequency synchronization even in a fading wireless transmission path.

According to the next invention, the modulation removal is performed on a plurality of signals sent from the transmitting side, and the reception levels of the plurality of modulation-removed signals are detected to determine the magnitude of the reception level. Is added, and the carrier frequency is corrected based on the weighted signal, so that the effect of a pilot signal having a small reception level during synchronization processing is reduced, and even in a radio transmission path with fading. Not only is it possible to achieve high-precision frequency synchronization, but also because all received signals that are unmodulated signals are used, all received power can be used without waste. Is obtained, an effective carrier frequency synchronization circuit can be obtained.

According to the next invention, when correcting the carrier frequency, the adder adds the signals obtained by weighting, and
The phase detection circuit detects the phase of the signal based on the addition result of the adder and obtains a correction amount for correcting the carrier frequency, so that the carrier frequency can be corrected according to the weight of each signal. There is an effect that a frequency synchronization circuit can be obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of an OFDM demodulator according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a format example of a transmission frame used in the OFDM scheme.

FIG. 3 is a block diagram illustrating a configuration example of an OFDM demodulator according to a second embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of removing a received signal having a small reception level in a fading transmission path according to the second embodiment.

FIG. 5 is a block diagram illustrating a configuration example of an OFDM demodulator according to a third embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration example of an OFDM demodulator according to a fourth embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration example of an OFDM demodulator according to a fifth embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration example of an OFDM demodulator according to a sixth embodiment of the present invention.

FIG. 9 is a general configuration diagram showing a relationship between an OFDM modulator and an OFDM demodulator according to a conventional example.

FIGS. 10A and 10B are diagrams for explaining transmission symbols. FIG. 10A shows a format of transmission symbols before serial-parallel conversion, and FIG. 10B shows a format of transmission symbols after serial-parallel conversion. .

FIG. 11 is a diagram illustrating a spectrum of a transmission IF signal output from the OFDM modulator.

FIG. 12 is a block diagram showing an OFDM demodulator according to a conventional example.

FIG. 13 is a diagram illustrating an in-phase component of a transmission baseband signal waveform.

FIG. 14 is a diagram illustrating a relationship between a delay of a received baseband signal and a correlation value.

FIG. 15 is a diagram illustrating the relationship between the frequency characteristics of a fading transmission path and the spectrum of a received signal.

[Explanation of symbols]

1,2,3,4,5,6 OFDM demodulator, 10,2
0, 30, 40, 50, 60 carrier frequency synchronization circuit,
11a, 21a, 31a Differential detection circuit, 11b, 21
b, 31b level detection circuit, 11 _{1 to} 11 _N , 21 ₁
To 21 _N , 31 _{1 to} 31 _N phase shift detection circuit, 12
Selector, 13 selection control circuit, 14 adder, 15
Phase detection circuit, 16 LF, 21c control circuit, 21d
Switch, coefficient setting circuit, 31d multiplier, 41 ₁ to
_{41 N, 51 1 ~51 N,} 61 1 ~61 N modulation removal circuit.

Claims (10)

[Claims] 1. A transmitting side generates a carrier signal by orthogonal frequency division multiplexing a signal including L1 (L1 is a natural number) signals serving as a reference for establishing synchronization of a carrier frequency.
On the receiving side, in order to establish the synchronization of the carrier frequency, the present invention is applied to a system for correcting the carrier frequency according to the state of the reference L1 signals in the carrier signal generated on the transmitting side. A carrier frequency synchronizing circuit used on the side, detecting means for detecting each reception level of the reference L1 signals received at the frequency used by the reference L1 signals; and the reference The L2 signals are compared in order of magnitude from the magnitude of the reception level detected by the detection means.
(L2 is a natural number, L2 ≦ L1) selecting means for selecting the reference signal; and correcting means for correcting a carrier frequency based on the reference signal selected by the selecting means. A carrier frequency synchronization circuit, characterized in that: 2. A transmitting side generates a carrier signal by orthogonal frequency division multiplexing a plurality of transmission signals, and a receiving side generates a carrier signal by establishing a plurality of carriers in the carrier signal generated by the transmitting side in order to establish synchronization of the carrier frequency. Applied to a system that corrects the carrier frequency according to the state of the signal, and performs modulation removal on a plurality of signals sent from the transmission side in a carrier frequency synchronization circuit used on the reception side of the system. Modulation removing means, detecting means for detecting each reception level of the plurality of signals which have been modulated and removed by the modulation removing means, and magnitude relationship between the reception levels detected by the detecting means among the plurality of modulated and removed signals. L2 in ascending order
Selecting means for selecting (L2 is a natural number) signals; and correcting means for correcting a carrier frequency based on a signal selected by the selecting means among the plurality of modulation-removed signals. A carrier frequency synchronization circuit. 3. The adder for adding a signal selected by the selector, and a correction amount for correcting a carrier frequency by detecting a phase of a signal based on an addition result of the adder. The carrier frequency synchronization circuit according to claim 1 or 2, further comprising a phase detection circuit. 4. A transmitting side generates a carrier signal by orthogonal frequency division multiplexing a signal including L1 (L1 is a natural number) signals serving as a reference for establishing synchronization of a carrier frequency.
On the receiving side, in order to establish the synchronization of the carrier frequency, the present invention is applied to a system for correcting the carrier frequency according to the state of the reference L1 signals in the carrier signal generated on the transmitting side. A carrier frequency synchronizing circuit used on the side, detecting means for detecting each reception level of the reference L1 signals received at the frequency used by the reference L1 signals; and the reference Extracting means for extracting a signal whose reception level detected by the detecting means is equal to or higher than a certain level among the L1 signals; and correcting for correcting a carrier frequency based on the reference signal extracted by the extracting means. Means; and a carrier frequency synchronization circuit. 5. A transmitting side generates a carrier signal by orthogonal frequency division multiplexing a plurality of transmission signals, and a receiving side generates a carrier signal by establishing a plurality of transmission signals in the carrier signal generated by the transmitting side to establish synchronization of the carrier frequency. Applied to a system that corrects the carrier frequency according to the state of the signal, and performs modulation removal on a plurality of signals sent from the transmission side in a carrier frequency synchronization circuit used on the reception side of the system. A modulation removal unit; a detection unit that detects each reception level of the plurality of signals that have undergone modulation removal by the modulation removal unit; and a reception level that is detected by the detection unit among the plurality of modulation-removed signals is constant. Extracting means for extracting a signal of a level or higher, and correcting means for correcting a carrier frequency based on a signal extracted by the extracting means among the plurality of signals subjected to modulation removal, Carrier frequency synchronization circuit, characterized in that it includes. 6. The adder for adding the signal extracted by the extractor, and a correction amount for correcting a carrier frequency by detecting a phase of a signal based on an addition result of the adder. The carrier frequency synchronization circuit according to claim 4, further comprising a phase detection circuit. 7. The apparatus according to claim 1, wherein the extraction unit has a switch that turns on an output when the reception level detected by the detection unit is equal to or higher than a predetermined level, and turns off an output when the reception level is lower than the predetermined level. Item 7. The carrier frequency synchronization circuit according to item 4, 5 or 6. 8. A transmitting side generates a carrier signal by orthogonal frequency division multiplexing a signal including L1 (L1 is a natural number) signals serving as a reference for establishing carrier frequency synchronization,
On the receiving side, in order to establish the synchronization of the carrier frequency, the present invention is applied to a system for correcting the carrier frequency according to the state of the reference L1 signals in the carrier signal generated on the transmitting side. A carrier frequency synchronizing circuit used on the side, detecting means for detecting each reception level of the reference L1 signals received at the frequency used by the reference L1 signals; and the reference Weighting means for weighting each of the L1 signals in accordance with the magnitude of the reception level detected by the detection means; and correcting the carrier frequency based on a reference signal weighted by the weighting means. A carrier frequency synchronization circuit, comprising: a correction unit. 9. A transmission side generates a carrier signal by orthogonal frequency division multiplexing of a plurality of transmission signals, and a reception side generates a carrier signal by establishing a plurality of carrier signals in the transmission side signal for establishing synchronization of the carrier frequency. Applied to a system that corrects the carrier frequency according to the state of the signal, and performs modulation removal on a plurality of signals sent from the transmission side in a carrier frequency synchronization circuit used on the reception side of the system. Modulation removing means, detecting means for detecting respective reception levels of the plurality of signals modulated by the modulation removing means, and detecting each of the plurality of signals modulated by the modulation removing means by the detecting means. Weighting means for adding a weight corresponding to the magnitude of the received level, and correction means for correcting the carrier frequency based on the signal weighted by the weighting means. Carrier frequency synchronization circuit, characterized in that the. 10. The correction means obtains a correction amount for correcting a carrier frequency by detecting an adder for adding the signals weighted by the weighting means and detecting a phase of a signal based on an addition result of the adder. 10. The carrier frequency synchronization circuit according to claim 8, further comprising a phase detection circuit.