JP3943228B2 - Carrier frequency synchronization circuit - Google Patents

Description

【００２９】
ここで、ρ（ｔ）は包絡線、θ（ｔ）は位相である。一方、Ｔｓ時間後に受信されるＡ２の部分の信号ｒＡ２（ｔ）は、Ａ１の部分と同一波形が搬送波周波数オフセットによって位相回転したものになり、次式（２）のように表すことができる。
【００３０】
【数２】

【００３１】
ここで、Δｆは搬送波周波数オフセットである。上式（１）で表される信号は搬送波周波数同期回路１００の構成における遅延回路１０１の出力信号に対応し、上式（２）で表される信号はＡ／Ｄ変換器９６ａ，９６ｂの出力信号に対応している。共役回路１０２ｂの出力は、上式（１）の信号の複素共役信号となるので次式（３）となる。
【００３２】
【数３】

【００３３】
ここで、上式（３）中の＊は複素共役を表す。複素乗算器１０２ａの出力信号は、上式（２）および（３）の積であるから、次式（４）となる。
【００３４】
【数４】

【００３５】
上式（４）には搬送波周波数オフセットΔｆが含まれているので、この搬送波周波数オフセットΔｆが後段の回路で検出される。移動平均回路１０２ｃは、ガードインターバル期間Ｔｇ分の入力信号の平均をとるので、その移動平均回路１０２ｃの出力信号は次式（５）で表される。
【００３６】
【数５】

【００３７】
ここで、Ｙはρ（ｔ）² がＴｇ時間に渡って平均された値であり、ほぼ一定値となる。位相検出回路１０３では上式（５）で表される信号の位相が検出される。したがって、位相検出回路２４の出力信号は２πΔｆＴｓとなるので、搬送波周波数オフセットΔｆに比例した信号が得られる。この２πΔｆＴｓが搬送波周波数同期のための誤差信号として用いられる。この誤差信号は、図１７に示したように、相関値がピークの時点で得られるので、ラッチ１０４によりシンボル周期でサンプリングされる。
【００３８】
ラッチ１０４の出力信号はＬＦ１０５によって不要な雑音成分が除去されて電圧制御搬送波発振器９９の制御電圧として使われる。電圧制御搬送波発振器９９は、制御電圧が正電圧の場合には出力周波数を小さくし、逆に負電圧の場合には大きくする。よって、Δｆ＞０の場合には発振周波数を小さく補正し、Δｆ＜０の場合には大きく補正することから、上記誤差信号は補正量を表すことになる。
このようにして、搬送波周波数オフセットΔｆが０になるように制御が行われ、搬送波周波数の同期が確立される。
【００３９】
【発明が解決しようとする課題】
従来の搬送波周波数同期回路は前述したように繰り返し送信される同一波形を用いて搬送波周波数の同期をとる構成としたので、搬送波周波数同期のための誤差信号は前述のとおり２πΔｆＴｓであった。この値は、搬送波周波数オフセットΔｆによってＴｓ時間内に変化する位相角（単位はラジアン）に等しい。
【００４０】
したがって、この値のとり得る値の範囲は式（６）のとおり−π〜πに制限される。この関係を次式で表すとことができる。すなわち、
−π＜２πΔｆＴｓ＜π … （６）
である。
【００４１】
したがって、前述したような搬送波周波数同期回路１００で同期できる搬送波周波数オフセットΔｆの範囲は、次式（７）で表されるように、±１／（２Ｔｓ）の範囲に限られる。すなわち、
−１／（２Ｔｓ）＜Δｆ＜１／（２Ｔｓ） … （７）
である。
【００４２】
隣接するサブキャリア間の関係をみると、図１４に示したように、１／Ｔｓはサブキャリア周波数間隔であるから、同期範囲はサブキャリア周波数間隔の半分となる。もしΔｆがこの範囲外であると同期できない。一般に、サブキャリア周波数間隔は数ｋＨｚ程度と小さい。具体例を１つ挙げると、欧州のディジタル音声放送システムのサブキャリア周波数間隔は４ｋＨｚである。搬送波周波数オフセットは、図１２において、送信側の搬送波発振器８７と受信側の搬送波発振器９４の発振周波数の違いにより生じていた。
【００４３】
そこで、一例として、上記搬送波発振器８７，９４の精度が±１ｐｐｍ（＝±１×１０^-6）、ＲＦ（Radio Frequency ）周波数が１．９ＧＨｚを仮定した場合には、最大の搬送波周波数オフセットΔｆの値は、Δｆ_max ＝±３．８ｋＨｚとなる。この場合、サブキャリア周波数間隔が４ｋＨｚのシステムを想定すると、従来の方式では±２ｋＨｚまでの周波数オフセットまでしか同期できないので、±３．８ｋＨｚという大きな周波数オフセットには同期できなかった。
【００４４】
以上のように、前述した搬送波周波数同期回路１００のような構成では、サブキャリア周波数間隔の１／２以上の搬送波周波数オフセットが存在する場合には、同期できないという問題点があった。
【００４５】
この発明は、上記のような問題点を解消するためになされたもので、ＯＦＤＭ復調器用の搬送波周波数同期回路として、大きな搬送波周波数オフセットが存在する場合であっても確実に搬送波周波数の同期を確立することが可能な搬送波周波数同期回路を得ることを目的とする。
【００４６】
【課題を解決するための手段】
上述した課題を解決し、目的を達成するため、この発明に係る搬送波周波数同期回路は、送信側では、搬送波周波数の同期確立のために基準となる信号を含んだ複数の信号を直交周波数分割多重して搬送波信号を生成し、受信側では、搬送波周波数の同期確立のため、前記送信側で生成された搬送波信号内の前記基準となる信号の状態に応じて搬送波周波数を補正するシステムに適用され、当該システムの受信側で使用される搬送波周波数同期回路において、前記基準となる信号が使用する周波数周辺の周波数で受信された前記基準となる信号の信号レベルに基づいて搬送波周波数の補正量を求める第１発生手段と、前記基準となる信号の位相変化量に基づいて搬送波周波数の補正量を求める第２発生手段と、前記第１発生手段で求めた補正量、前記第２発生手段で求めた補正量の順で搬送波周波数の補正制御を行う制御手段と、を備えたことを特徴とする。
【００４７】
この発明によれば、同期確立の基準となる信号が使用する周波数周辺の周波数で受信された同期確立の基準となる信号の信号レベルに基づいて求めた搬送波周波数の補正量に従って搬送波周波数の補正制御を行い、その後で、同期確立の基準となる信号の位相変化量に基づいて求めた搬送波周波数の補正量に従って搬送波周波数の補正制御を行うようにしたので、初期の大きな搬送波周波数オフセットに対しても正しく補正量が得られることになり、この補正量に従って補正して搬送波周波数オフセットがある程度小さくなってから同期確立が行われ、これにより、大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能である。
【００４８】
つぎの発明に係る搬送波周波数同期回路は、前記基準となる信号は前記送信側で位相変化をもたないように無変調信号として生成された信号であり、前記第１発生手段は、前記基準となる信号が使用する周波数１つずつの上下の周波数で受信された前記搬送波信号をそれぞれ遅延検波する一対の遅延検波回路と、前記一対の遅延検波回路によりそれぞれ遅延検波された信号を平均化する一対の平均回路と、前記一対の平均回路によりそれぞれ平均化された信号の包絡線に基づいて信号レベルを検出する一対の包絡線検出回路と、前記一対の包絡線検出回路によりそれぞれ検出された信号レベルの差分をとって前記補正量を得る演算回路と、を含み、前記第２発生手段は、前記基準となる信号を遅延検波する遅延検波回路と、前記遅延検波回路により遅延検波された信号の位相変化量を検出して前記補正量を得る位相検出回路と、を含んだことを特徴とする。
【００４９】
この発明によれば、同期確立の基準となる信号が送信側で位相変化をもたないように無変調信号として生成された場合には、搬送波信号の位相が時間的に変化しないことから、同期確立のために、基準となる信号が使用する周波数の上下１つずつの周波数で検出される基準となる信号の信号レベルの差分をとって補正量を得る構成と、基準となる信号の位相変化量を補正量として求める構成とを用意すればよく、このような構成により、同期確立の基準となる信号が送信側で位相変化をもたなくても、初期の大きな搬送波周波数オフセットに対しても正しく補正量が得られることになり、この補正量に従って補正して搬送波周波数オフセットがある程度小さくなってから同期確立が行われるため、大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能である。
【００５０】
つぎの発明に係る搬送波周波数同期回路は、前記基準となる信号は前記送信側で位相変化をもつように変調信号として生成された信号であり、前記第１発生手段は、前記基準となる信号が使用する周波数の上下１つずつの周波数で受信された前記搬送波信号の位相変化を除去する一対の第１位相回転回路と、前記一対の第１位相回転回路によりそれぞれ位相変化を除去された前記搬送波信号をそれぞれ遅延検波する一対の遅延検波回路と、前記一対の遅延検波回路によりそれぞれ遅延検波された信号を平均化する一対の平均回路と、前記一対の平均回路によりそれぞれ平均化された信号の包絡線に基づいて信号レベルを検出する一対の包絡線検出回路と、前記一対の包絡線検出回路によりそれぞれ検出された信号レベルの差分をとって前記補正量を得る演算回路と、を含み、前記第２発生手段は、前記基準となる信号の位相変化を除去する第２位相回転回路と、前記第２位相回転回路により位相変化を除去された前記基準となる信号を遅延検波する遅延検波回路と、前記遅延検波回路により遅延検波された信号の位相変化量を検出して前記補正量を得る位相検出回路と、を含んだことを特徴とする。
【００５１】
この発明によれば、同期確立の基準となる信号が送信側で位相変化をもつように変調信号として生成された場合には、搬送波信号の位相が時間的に変化することから、同期確立のために、まず位相変化を打ち消してから基準となる信号が使用する周波数の上下１つずつの周波数で検出される基準となる信号の信号レベルの差分をとって補正量を得る構成と、まず位相変化を打ち消してから基準となる信号の位相変化量を補正量として求める構成とを用意すればよく、このような構成により、同期確立の基準となる信号が送信側で位相変化をもっていても、初期の大きな搬送波周波数オフセットに対しても正しく補正量が得られることになり、この補正量に従って補正して搬送波周波数オフセットがある程度小さくなってから同期確立が行われるため、大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能である。
【００５２】
つぎの発明に係る搬送波周波数同期回路は、前記基準となる信号は前記送信側で位相変化をもたないように無変調信号として生成された信号であり、前記第１発生手段は、前記基準となる信号が使用する周波数よりも大きい周辺の複数の周波数および小さい周辺の複数の周波数でそれぞれ受信された前記搬送波信号をそれぞれ遅延検波する複数の遅延検波回路と、前記複数の遅延検波回路によりそれぞれ遅延検波された信号を平均化する複数の平均回路と、前記複数の平均回路によりそれぞれ平均化された信号の包絡線に基づいて信号レベルを検出する複数の包絡線検出回路と、前記複数の包絡線検出回路によりそれぞれ検出された信号レベルの内で、前記基準となる信号が使用する周波数よりも大きい周波数で検出された前記信号レベルの和と前記基準となる信号が使用する周波数よりも小さい周波数で受信された前記信号レベルの和との差分をとって前記補正量を得る演算回路と、を含み、前記第２発生手段は、前記基準となる信号を遅延検波する遅延検波回路と、前記遅延検波回路により遅延検波された信号の位相変化量を検出して前記補正量を得る位相検出回路と、を含んだことを特徴とする。
【００５３】
この発明によれば、同期確立の基準となる信号が送信側で位相変化をもたないように無変調信号として生成された場合には、搬送波信号の位相が時間的に変化しないことから、同期確立のために、基準となる信号が使用する周波数よりも大きい周辺の複数の周波数および小さい周辺の複数の周波数でそれぞれ検出された基準となる信号の信号レベルの差分をとって補正量を得る構成と、基準となる信号の位相変化量を補正量として求める構成とを用意すればよく、このような構成により、同期確立の基準となる信号が送信側で位相変化をもたなくても、基準となる信号が使用する周波数の上下１つずつの周波数で受信される搬送波信号から補正量を得る場合よりも幅広い搬送波周波数オフセットに対して補正量が得られ、搬送波周波数オフセットがある程度小さくなってから同期確立が行われるため、より大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能である。
【００５４】
つぎの発明に係る搬送波周波数同期回路は、前記基準となる信号は前記送信側で位相変化をもつように変調信号として生成された信号であり、前記第１発生手段は、前記基準となる信号が使用する周波数よりも大きい周辺の複数の周波数および小さい周辺の複数の周波数でそれぞれ受信された前記搬送波信号の位相変化を除去する複数の第１位相回転回路と、前記複数の第１位相回転回路によりそれぞれ位相変化を除去された前記搬送波信号をそれぞれ遅延検波する複数の遅延検波回路と、前記複数の遅延検波回路によりそれぞれ遅延検波された信号を平均化する複数の平均回路と、前記複数の平均回路によりそれぞれ平均化された信号の包絡線に基づいて信号レベルを検出する複数の包絡線検出回路と、前記複数の包絡線検出回路によりそれぞれ検出された信号レベルの内で、前記基準となる信号が使用する周波数よりも大きい周波数で検出された前記信号レベルの和と前記基準となる信号が使用する周波数よりも小さい周波数で受信された前記信号レベルの和との差分をとって前記補正量を得る演算回路と、を含み、前記第２発生手段は、前記基準となる信号の位相変化を除去する第２位相回転回路と、前記第２位相回転回路により位相変化を除去された前記基準となる信号を遅延検波する遅延検波回路と、前記遅延検波回路により遅延検波された信号の位相変化量を検出して前記補正量を得る位相検出回路と、を含んだことを特徴とする。
【００５５】
この発明によれば、同期確立の基準となる信号が送信側で位相変化をもつように変調信号として生成された場合には、搬送波信号の位相が時間的に変化することから、同期確立のために、まず位相変化を打ち消してから基準となる信号が使用する周波数よりも大きい周辺の複数の周波数および小さい周辺の複数の周波数でそれぞれ受信された搬送波信号について信号レベルの差分をとって補正量を得る構成と、まず位相変化を打ち消してから基準となる信号の位相変化量を補正量として求める構成とを用意すればよく、このような構成により、同期確立の基準となる信号が送信側で位相変化をもっていても、基準となる信号が使用する周波数の上下１つずつの周波数で受信された搬送波信号から補正量を得る場合よりも広い搬送波周波数オフセットに対して補正量が得られ、搬送波周波数オフセットがある程度小さくなってから同期確立が行われるため、より大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能である。
【００５６】
つぎの発明に係る搬送波周波数同期回路は、前記制御手段は、搬送波周波数のオフセット量が一定量よりも小さくなった時のタイミングで使用補正量を前記第１発生手段で求めた補正量から前記第２発生手段で求めた補正量へ切り換えるスイッチであることを特徴とする。
【００５７】
この発明によれば、スイッチにより搬送波周波数のオフセット量が一定量よりも小さくなった時のタイミングで使用補正量を切り換えるようにしたので、搬送波周波数オフセットの状況に応じて適切な補正を与えることができ、これにより、搬送波周波数の同期確立をスムーズに行うことが可能である。
【００５８】
つぎの発明に係る搬送波周波数同期回路は、前記タイミングは、同期確立開始後の一定時間の経過により前記スイッチへ供給されることを特徴とする。
【００５９】
この発明によれば、同期確立開始後の一定時間の経過でスイッチの切り換えタイミングを図るようにしたので、同期確立の際には、常に一定のタイミングで搬送波周波数の同期動作を実現することが可能である。
【００６０】
つぎの発明に係る搬送波周波数同期回路は、前記一定時間を記憶したメモリと、前記メモリに記憶された前記一定時間を参照して前記スイッチの切り換えを制御する切換制御回路とをさらに有したことを特徴とする。
【００６１】
この発明によれば、メモリに一定時間を記憶しておき、切換制御回路によりその一定時間を参照してスイッチの切り換えを制御するようにしたので、外部から切り換えタイミングを与えなくても、簡単な構成でスイッチを切り換えることが可能である。
【００６２】
つぎの発明に係る搬送波周波数同期回路は、あらかじめ設定された前記一定時間をカウントするカウント回路をさらに有したことを特徴とする。
【００６３】
この発明によれば、カウント回路によりあらかじめ設定された一定時間をカウントして、スイッチの切り換えタイミングを得るようにしたので、外部から切り換えタイミングを与えなくても、簡単な構成でスイッチを切り換えることが可能である。
【００６４】
つぎの発明に係る搬送波周波数同期回路は、前記制御手段は、前記基準となる信号が使用する周波数で受信された前記基準となる信号の信号レベルが前記基準となる信号が使用する周波数に隣接する少なくとも２つの周波数で検出された前記基準となる信号の信号レベルよりも所定値以上大きくなった時のタイミングで使用補正量を前記第１発生手段で求めた補正量から前記第２発生手段で求めた補正量へ切り換えるスイッチであることを特徴とする。
【００６５】
この発明によれば、基準となる信号の信号レベルが基準となる信号が使用する周波数に隣接する少なくとも２つの周波数で検出された基準となる信号の信号レベルよりも大きくなった時のタイミングで使用補正量を切り換えるようにしたので、あらかじめ切り換えタイミングを用意しておく必要がなく、装置の製造過程を単純化することが可能である。
【００６６】
【発明の実施の形態】
以下に添付図面を参照して、この発明に係る搬送波周波数同期回路の好適な実施の形態を詳細に説明する。
【００６７】
実施の形態１．
本実施の形態１は、ＯＦＤＭ方式により、特定のサブキャリアを用いてパイロット信号（一般には無変調のパイロットシンボル）を伝送する一例である。ここで、無変調のパイロットシンボルとは、全て「０」もしくは全て「１」のように時間的に変化しないデータから成るシンボルを言う。
【００６８】
まず、構成について説明する。図１は本発明の実施の形態１による搬送波周波数同期回路の一構成例を示すブロック図であり、同図において、１は本実施の形態１のＯＦＤＭ復調器を示している。図１において、従来例と同一部分には同一符号を付し説明を省略する。ＦＦＴプロセッサ９７の出力信号のうち、サブキャリアｍがパイロットシンボルを伝送するためのサブキャリアの番号を表し、Ｃ_m-1 ，Ｃ_m ，Ｃ_m+1 はそれぞれサブキャリアｍ−１，ｍ，ｍ＋１での復調シンボルを表している。
【００６９】
図１に示したＯＦＤＭ復調器１は、図１５のＯＦＤＭ復調器の全体構成において、搬送波周波数同期回路１００に替わる搬送波周波数同期回路１０を有している。この搬送波周波数同期回路１０は、前述した搬送波周波数同期回路１００（図１５参照）と同様に、搬送波発振器９９の電圧制御を行って搬送波周波数の同期を確立する。この搬送波周波数同期回路１０は、ＦＦＴプロセッサ９７の出力に接続される点で前述した搬送波周波数同期回路１００とは接続関係が異なる。
具体的には、ＦＦＴプロセッサ９７からの並列（復調信号Ｃ₀ 〜Ｃ_N-1 ）の内で、パイロットシンボルが伝送されるサブキャリア周波数とその周辺（上下１つずつ）のサブキャリア周波数での出力が接続される。
【００７０】
搬送波周波数同期回路１０は、図１に示したように、パイロットシンボルレベル検出回路１３ａ，１３ｂ、加算器１７およびＬＦ１８ａよりなる第１発生回路、遅延検波回路１１、位相検出回路１２およびＬＦ１８ｂよりなる第２発生回路、および、補正制御回路１９を備えている。
【００７１】
上記第１発生回路において、パイロットシンボルレベル検出回路１３ａは、パイロットシンボルが伝送されるサブキャリアｍよりも番号が１つ小さいサブキャリアｍ−１、すなわちパイロットシンボルが伝送されるサブキャリア周波数よりも周波数がサブキャリア間隔だけ低いサブキャリアにおける復調出力Ｃ_m-1 を入力して、Ｃ_m-1 に含まれるパイロットシンボル成分のレベルを検出して検出結果を出力する回路である。
【００７２】
同様に、パイロットシンボルレベル検出回路１３ｂは、パイロットシンボルの伝送されるサブキャリアｍよりも番号が１つ大きいサブキャリアｍ＋１、すなわちパイロットシンボルが伝送されるサブキャリア周波数よりも周波数がサブキャリア間隔だけ高いサブキャリアにおける復調出力Ｃ_m+1 を入力して、Ｃ_m+1 に含まれるパイロットシンボル成分のレベルを検出して検出結果を出力する回路である。
【００７３】
パイロットシンボルレベル検出回路１３ａは、遅延検波回路１４ａ、平均回路１５ａおよび包絡線検出回路１６ａを備え、パイロットシンボルレベル検出回路１３ｂは、遅延検波回路１４ｂ、平均回路１５ｂおよび包絡線検出回路１６ｂを備えている。遅延検波回路１４ａ，１４ｂは、それぞれ入力された信号（復調出力Ｃ_m-1 ，Ｃ_m+1 ）に対して遅延検波を行いその結果を出力する。平均回路１５ａ，１５ｂは、それぞれ遅延検波回路１４ａ，１４ｂの出力信号を入力して、その入力信号を一定時間平均してその結果を出力する。
【００７４】
包絡線検出回路１６ａ，１６ｂはそれぞれ平均回路１５ａ，１５ｂの出力信号を入力して、その入力信号の包絡線の大きさを検出してその結果を出力する。加算器１７は、パイロットシンボルレベル検出回路１３ｂの出力からパイロットシンボルレベル検出回路１３ａの出力を減算してその結果を出力する。ここで、減算器１７の出力信号が搬送波周波数同期のための第１誤差信号ＥＲＲ１となる。
ＬＦ１８ａは、減算器１７の出力信号である第１誤差信号ＥＲＲ１から不要な雑音成分を除去して出力する。
【００７５】
前記第２発生回路において、遅延検波回路１１は、ＦＦＴプロセッサ９７の復調信号Ｃ_m 出力に接続され、パイロットシンボルの伝送されるサブキャリアｍにおける復調出力Ｃ_m を入力して遅延検波を行う。位相検出回路１２は遅延検波回路１１の出力信号の位相を求めてその結果を出力する。ここで、位相検出回路１２の出力信号が第２誤差信号ＥＲＲ２となる。ＬＦ１８ｂは、位相検出回路１２の出力信号である第２誤差信号ＥＲＲ２から不要な雑音成分を除去して出力する。
【００７６】
また、補正制御回路１９は、ＬＦ１８ａ，ＬＦ１８ｂおよび搬送波発振器９９に接続され、所定のタイミングで第１誤差信号ＥＲＲ１，ＥＲＲ２のいずれか一方を搬送波発振器９９の制御電圧として供給する。ここで、所定のタイミングとは、搬送波周波数のオフセット量が一定量よりも小さくなった時のタイミングで使用補正量を第１誤差信号ＥＲＲ１（前記第１発生回路で求めた電圧制御の補正量）から第２誤差信号ＥＲＲ２（前記第２発生回路で求めた補正量）へ切り換えるタイミングを指す。この所定のタイミングの取り方については、時間計測など各種の方法が考えられる。
【００７７】
図２には、ＯＦＤＭ方式に使用される伝送フレームのフォーマット例が示されている。伝送フレームのフォーマットは、図２に示したように、ヌルシンボル、データ、パイロットシンボル、データで構成されている。先頭シンボルとして無変調のヌルシンボルが挿入される。この位置は、復調シンボルＣ₀ の位置にあたる。それ以降はデータが挿入される。本実施の形態１では、パイロット信号のデータ系列は既知のため、パイロットシンボルの位置は既知であり、復調シンボルＣ_m の位置にあたる。
【００７８】
つぎに、誤差信号について説明する。まず、第１誤差信号ＥＲＲ１の生成方法について説明する。搬送波周波数オフセットΔｆが０Ｈｚであれば、受信されたパイロットシンボルはサブキャリアｍのみに現れるが、搬送波周波数オフセットΔｆが存在すると、受信されたパイロットシンボルの電力の一部が隣接するサブキャリア（サブキャリアｍ−１もしくはサブキャリアｍ＋１）に漏れる。搬送波周波数オフセットΔｆが負の場合には受信されたパイロットシンボルの電力の一部はサブキャリアｍ−１に漏れ、搬送波周波数オフセットΔｆが正の場合には受信されたパイロットシンボルの電力の一部はサブキャリアｍ＋１に漏れる。
【００７９】
隣接するサブキャリアに漏れるパイロットシンボルのレベルは搬送波周波数オフセットΔｆの大きさによって変化する。そこで、パイロットシンボルが伝送されるサブキャリアｍの隣接する２つのサブキャリアの復調信号に含まれるパイロットシンボルのレベルを検出することで、搬送波周波数オフセットΔｆの方向とその大きさを知ることができる。搬送波周波数オフセットΔｆの方向およびその大きさを表す情報を搬送波周波数同期用の誤差信号として使用することで、搬送波周波数同期をとることができる。
【００８０】
続いて、パイロットシンボルレベルの検出方法について説明する。図３は遅延回路出力を説明する図であり、同図（ａ）は無変調パイロットシンボル成分に対する遅延検波回路１４ａ，１４ｂの出力を示し、同図（ｂ）はパイロットシンボル以外の信号成分に対する遅延検波回路１４ａ，１４ｂの出力を示している。図４は誤差信号を説明する図であり、同図（ａ）は搬送波周波数オフセットΔｆによるパイロットシンボルレベル検出回路１３ａ，１３ｂの変化を示し、同図（ｂ）は搬送波周波数オフセットΔｆによる第１誤差信号ＥＲＲ１の変化を示している。
【００８１】
ここで、搬送波周波数オフセットΔｆが負の場合を想定すると、復調出力Ｃ_{m- 1} には無変調のパイロットシンボル成分と、パイロットシンボル以外のシンボル成分が混在している。パイロットシンボル以外のシンボルは、送信するデータによりその振幅や位相が変化する。パイロットシンボルレベル検出回路１３ａはパイロットシンボルのみのレベルを抽出してそのレベルを出力する。遅延検波回路１４ａの出力信号には、パイロットシンボルに対する遅延検波出力と、パイロットシンボル以外のシンボルに対する遅延検波出力が混在する。
【００８２】
ここで、図３（ａ）に示すように、パイロットシンボルに対する遅延検波出力は、その位相が時間的に変化しない信号となる。これに対して、図３（ｂ）に示すように、パイロットシンボル以外のシンボルに対する遅延検波出力は、その位相がランダムに変化する信号となる。
【００８３】
ここで、図３（ｂ）は変調方式がＱＰＳＫの場合の例であり、遅延検波回路出力信号の位相は０、π／２、π、−π／２の内のいずれかをランダムにとる。このような遅延検波回路１４ａの出力信号を平均回路１５ａで平均すると、パイロットシンボル成分に対する平均包絡線は大きいのに対して、パイロットシンボル以外のシンボル成分に対する平均包絡線はほぼ０（ゼロ）となる。
【００８４】
したがって、包絡線検出器１６ａにより平均回路１５ａの出力信号の包絡線を検出すると、その結果は、パイロットシンボル以外のシンボルに対しては０（ゼロ）となって、パイロットシンボル成分のみに対するレベルが得られる。このように、パイロットシンボルレベル検出回路１３ａは、サブキャリア番号ｍ−１に含まれる信号成分の内、パイロットシンボル成分のみのレベルを出力する。
【００８５】
サブキャリア番号ｍ−１に含まれるパイロットシンボルレベルは、図４（ａ）に示すように、搬送波周波数オフセットΔｆがサブキャリア周波数間隔だけ負の方向である場合、すなわち、Δｆ＝−１／Ｔｓ（ΔｆＴｓ＝−１）の場合に最大となって、Δｆが−１／Ｔｓから離れるにしたがって（ΔｆＴｓが−１から離れるにしたがって）小さくなるような信号の波形３０１ａとなる。
【００８６】
また、パイロットシンボルレベル検出回路１３ｂについても同様であって、サブキャリアｍ＋１に含まれる信号成分の内、パイロットシンボル成分のみのレベルを出力する。図４（ａ）に示すように、サブキャリアｍ＋１に含まれるパイロットシンボルレベルは、搬送波周波数オフセットΔｆがサブキャリア周波数間隔だけ正の方向である場合、すなわち、Δｆ＝１／Ｔｓ（ΔｆＴｓ＝１）の場合に最大となって、Δｆが１／Ｔｓから離れるにしたがって（ΔｆＴｓが１から離れるにしたがって）小さくなるような信号の波形３０１ｂとなる。
【００８７】
減算器１７は、パイロットシンボルレベル検出回路１３ｂの出力からパイロットシンボルレベル検出回路１３ａの出力を減算する。その結果、減算器１７の出力信号は図４（ｂ）に示す波形３０２のようになる。したがって、搬送波周波数同期用の第１誤差信号ＥＲＲ１は搬送波周波数オフセットΔｆが−２／Ｔｓから２／Ｔｓの範囲で得られる。この第１誤差信号ＥＲＲ１は、ＬＦ１８ａで雑音成分が除去された後に電圧制御搬送波発振器９９の制御電圧として機能する。
【００８８】
続いて第２誤差信号ＥＲＲ２の生成方法について説明する。第１誤差信号ＥＲＲ１により搬送波周波数オフセットΔｆが十分に小さくなった後では、遅延検波回路１１に入力されるシンボル成分はほとんどパイロット信号成分のみとなる。
遅延検波回路１１に入力されるパイロットシンボルを複素数で表すと次式（８）のように表される。
【００８９】
【数６】

【００９０】
ここで、ρ、θはそれぞれ包絡線と位相であり、無変調パイロットシンボルの場合は変化しない一定値となる。遅延検波回路２８ｃは１シンボル毎（Ｔｓ時間毎）に入力信号の遅延検波を行いその結果を出力するのでその出力信号は次式（９）のように表される。
【００９１】
【数７】

【００９２】
位相検出回路１２は上式（８）で表される遅延検波回路１１による出力信号の位相２πΔｆＴｓを検出して出力する。位相検出回路１１による出力信号が第２誤差信号ＥＲＲ２となる。よって、第２誤差信号ＥＲＲ２は搬送波周波数オフセットΔｆに比例した信号（＝２πΔｆＴｓ）となる。この第２誤差信号ＥＲＲ２は、ＬＦ１８ｂで雑音成分が除去された後に搬送波発振器９９の制御電圧となる。
【００９３】
以上説明したように、本実施の形態１によれば、まず広い周波数範囲で誤差信号を発生することのできる第１誤差信号ＥＲＲ１を使って搬送波周波数の同期を行い、Δｆが十分に小さくなった後に第２誤差信号ＥＲＲ２に切り換えて搬送波周波数の同期を行うことから、Δｆが−２／Ｔｓ〜２／Ｔｓの範囲であれば、搬送波周波数の同期を確立することが可能である。その結果、搬送波周波数の同期範囲が−２／Ｔｓ〜２／Ｔｓであって、従来例の４倍となり、大きな搬送波周波数オフセットΔｆが存在しても搬送波周波数の同期をとることが可能である。
【００９４】
また、サブキャリア周波数の間隔１／Ｔｓを４ｋＨｚ、ＲＦ（Radio Frequency ）周波数が１．９ＧＨｚ、発振器の精度が±１ｐｐｍ（＝±１×１０^-6）であるとすると、最大のΔｆの値は、Δｆ_max ＝±３．８ｋＨｚである。この場合、従来の方式では±２ｋＨｚまでの周波数オフセットまでしか対応できないので、搬送波周波数同期がとれなかったが、本実施の形態１によれば、４倍の±８ｋＨｚまでの周波数オフセットまで対応できるので、このように大きな搬送波周波数オフセットΔｆが存在する場合においても搬送波周波数の同期をとることが可能である。
【００９５】
実施の形態２．
さて、前述した実施の形態１では、パイロットシンボルが時間的に変化しない信号（無変調信号）である場合について説明したが、本発明は、これに限定されず、以下に説明する実施の形態２のように、パイロットシンボルが時間的に変化する信号（変調信号）である場合にも適用可能である。
【００９６】
まず、構成について説明する。図５は本発明の実施の形態２による搬送波周波数同期回路の一構成例を示すブロック図であり、同図において、２は本実施の形態２のＯＦＤＭ復調器を示している。このＯＦＤＭ復調器２は、前述した実施の形態１によるＯＦＤＭ復調器１と全体的には同様の構成を採用しており、ＯＦＤＭ復調器１とは搬送波周波数同期回路１０から搬送波周波数同期回路２０に置き換えた部分で相違する。したがって、このＯＦＤＭ復調器２においては、ＯＦＤＭ復調器１と同様の構成には同様の番号を付してその説明を省略する。
【００９７】
搬送波周波数同期回路２０は、前述した搬送波周波数同期回路１０とは、パイロットシンボルの時間的な変化を相殺するための回路を追加した部分で相違する。すなわち、搬送波周波数同期回路２０は、遅延検波回路１１、パイロットシンボルレベル検出回路１３ａ，１３ｂの前段にそれぞれ位相回転回路２１，２２ａ，２２ｂを設けている。これら位相回転回路２１，２２ａ，２２ｂは、いずれも入力信号（復調出力Ｃ_m ，Ｃ_m-1 ，Ｃ_m+1 ）に対してパイロットシンボルの位相回転と逆の回転を与えてパイロットシンボルの時間的な変化をうち消すものである。
【００９８】
前述した搬送波周波数同期回路１０はパイロットシンボルが時間的に変化しない信号（無変調信号）である場合に適用可能な構成であるため、無変調信号ではない場合すなわち変調信号の場合にはそのままでは適用できない。なぜならば、パイロットシンボルが無変調信号でなく時間的に変化する場合には、図３（ａ）に示した遅延検波回路出力信号の位相が固定値にはならず、図３（ｂ）のように変化してしまうため、平均結果が０となって、パイロットシンボルレベル検出回路１３ａ，１３ｂの出力が０になってしまうからである。
【００９９】
そこで、本実施の形態２では、このようにパイロットシンボルが無変調信号でない場合に対して搬送波周波数同期をとることができる。パイロットシンボルが無変調信号でない場合には、パイロットシンボルは、予め決められた既知のデータ系列に応じてその位相が変化する信号となる。したがって、受信側（ＯＦＤＭ復調器２）では、このデータ系列に応じて受信シンボルの位相がどのように変化するかが予め分かるので、遅延検波回路１１、パイロットシンボルレベル検出回路１３ａ，１３ｂの各入力段において、位相回転回路２１，２２ａ，２２ｂが受信シンボルの既知の位相変化を除去する。
【０１００】
すなわち、位相回転回路２１，２２ａ，２２ｂは、入力信号に対してパイロットシンボルの位相回転と逆の回転を与えて出力する。その結果、位相回転回路２１，２２ａ，２２ｂの出力信号はパイロットシンボル成分に関してはパイロットシンボルが無変調である場合と同じになる。
【０１０１】
これに対し、パイロットシンボルとパイロットシンボル以外のシンボルとの間には相関がないので、パイロットシンボル以外の成分に関しては、ランダムな位相変化をする信号となる。このように、遅延検波回路１１とパイロットシンボルレベル検出回路１３ａ，１３ｂの各入力段に位相回転回路２１，２２ａ，２２ｂを設けたので、各位相回転回路２１，２２ａ，２２ｂの出力信号に含まれるパイロットシンボルは無変調となる。なお、遅延検波回路１１とパイロットシンボルレベル検出回路１３ａ，１３ｂおよびそれ以降の回路の動作については、前述した実施の形態１と同様のため、説明を省略する。
【０１０２】
以上説明したように、本実施の形態２によれば、パイロットシンボルが無変調でない場合であっても減算器１７から出力される第１誤差信号ＥＲＲ１と位相検出回路１２から出力される第２誤差信号ＥＲＲ２はそれぞれ前述した実施の形態１と同一のものとなる。したがって、パイロットシンボルが無変調でない場合であっても、前述した実施の形態１と同様に、搬送波周波数の同期範囲が−２／Ｔｓから２／Ｔｓとなるので、大きな搬送波周波数オフセットΔｆが存在しても搬送波周波数の同期をとることが可能である。
【０１０３】
実施の形態３．
さて、前述した実施の形態１では、既知のパイロットシンボルが使用するサブキャリア周波数よりも１段大きいサブキャリア周波数と１段小さいサブキャリア周波数でそれぞれ受信されるパイロット信号のレベルを用いて第１誤差信号ＥＲＲを得るようしたが、本発明は、これに限定されず、以下に説明する実施の形態３のように、既知のパイロットシンボルが使用するサブキャリア周波数周辺のサブキャリア周波数の範囲を広げて、前述した実施の形態１よりも大きい搬送波周波数オフセットΔｆに対処できるようにしてもよい。
【０１０４】
まず、構成について説明する。図６は本発明の実施の形態３による搬送波周波数同期回路の一構成例を示すブロック図であり、同図において、３は本実施の形態３のＯＦＤＭ復調器を示している。このＯＦＤＭ復調器３は、前述した実施の形態１によるＯＦＤＭ復調器１と全体的には同様の構成を採用しており、ＯＦＤＭ復調器１とは搬送波周波数同期回路１０から搬送波周波数同期回路３０に置き換えた部分で相違する。したがって、このＯＦＤＭ復調器３においては、ＯＦＤＭ復調器１と同様の構成には同様の番号を付してその説明を省略する。
【０１０５】
搬送波周波数同期回路３０は、パイロットシンボルが無変調の場合で、搬送波周波数オフセットΔｆが前述の実施の形態１の構成では同期できないほど大きい場合に搬送波周波数の同期をとるための構成を備えている。すなわち、搬送波周波数同期回路３０は、パイロットシンボルを伝送するサブキャリア周波数よりも２つ離れたサブキャリア周波数で伝送されるパイロット信号についてもその信号レベルを第１誤差信号ＥＲＲ１生成のために使用する。すなわち、搬送波周波数同期回路３０には、ＦＦＴプロセッサ９７からの並列（復調信号Ｃ₀ 〜Ｃ_N-1 ）の内で、パイロットシンボルが伝送されるサブキャリア周波数とその周辺（上下２つずつ）のサブキャリア周波数での出力が接続される。
【０１０６】
搬送波周波数同期回路３０は、ＦＦＴプロセッサ９７に接続されるパイロットシンボルレベル検出回路１３ｃおよびパイロットシンボルレベル検出回路１３ｄを新たな構成として追加している。パイロットシンボルレベル検出回路１３ｃは、パイロットシンボルが伝送されるサブキャリアｍよりも番号が２つ小さいサブキャリアｍ−２、すなわちパイロットシンボルが伝送されるサブキャリア周波数よりも周波数がサブキャリア間隔の２倍だけ低いサブキャリアにおける復調出力Ｃ_m-2 を入力して、Ｃ_m-2 に含まれるパイロット信号のレベルを検出して検出結果を出力する。
【０１０７】
また、パイロットシンボルレベル検出回路１３ｄは、パイロットシンボルが伝送されるサブキャリアｍよりも番号が２つ大きいサブキャリアｍ＋２、すなわちパイロットシンボルが伝送されるサブキャリア周波数よりも周波数がサブキャリア間隔の２倍だけ高いサブキャリアにおける復調出力Ｃ_m+2 を入力して、Ｃ_m+2 に含まれるパイロット信号のレベルを検出して検出結果を出力する。なお、これらパイロットシンボルレベル検出回路１３ｃおよび１３ｄは、前述したパイロットシンボルレベル検出回路１３ａおよび１３ｂと同様の構成を有しているので、その構成についての説明を省略する。
【０１０８】
搬送波周波数同期回路３０は、さらに、パイロットシンボルが受信されるサブキャリア周波数よりも下のサブキャリア周波数で受信されるパイロット信号について信号レベルを合算する加算器３１ａと、パイロットシンボルが伝送されるサブキャリア周波数よりも上のサブキャリア周波数で伝送されるパイロット信号について信号レベルを合算する加算器３１ｂとを備えている。
【０１０９】
加算器３１ａは、パイロットシンボルレベル検出回路１３ａと１３ｃとに接続され、加算器３１ｂは、パイロットシンボルレベル検出回路１３ｂと１３ｄとに接続される。これら加算器３１ａと３１ｂは、その出力を減算器１７に接続させている。したがって、減算器１７は、パイロットシンボルが受信されるサブキャリア周波数よりも上のサブキャリア周波数で受信されるパイロット信号の総信号レベルからパイロットシンボルが伝送されるサブキャリア周波数よりも下のサブキャリア周波数で伝送されるパイロット信号の総信号レベルを減算して第１誤差信号ＥＲＲ１を求める。
【０１１０】
つぎに、主要な動作について説明する。図７は誤差信号を説明する図であり、同図（ａ）は搬送波周波数オフセットΔｆによるパイロットシンボルレベル検出回路１３ａ，１３ｂの変化を示し、同図（ｂ）は搬送波周波数オフセットΔｆによる第１誤差信号ＥＲＲ１の変化を示している。パイロットシンボル検出回路１３ａの出力は、図７（ａ）に示すように、ΔｆＴｓ＝−１の場合に最大となって、ΔｆＴｓが−１から離れるにしたがって小さくなるような信号の波形６０１ａである。
【０１１１】
また、パイロットシンボル検出回路１３ｂの出力は、図７（ａ）に示すように、ΔｆＴｓ＝１の場合に最大となって、ΔｆＴｓが１から離れるにしたがって小さくなるような信号の波形６０１ｂである。これら波形６０１ａ，６０１ｂはすでに図４で説明した波形３０１ａ，３０１ｂと同じである。
【０１１２】
新たに設けたパイロットシンボル検出回路１３ｃに入力される信号は、パイロットシンボル検出回路２７ａに入力される信号よりもサブキャリア周波数間隔だけ低い周波数に対応する復調シンボルＣ_m-2 であるから、ΔｆＴｓのピークはサブキャリア周波数間隔だけ低い周波数にシフトする波形６０１ｃとなる。
【０１１３】
すなわち、波形６０１ｃは、図７（ａ）に示すように、ΔｆＴｓ＝−２でピークとなる。同様に、パイロットシンボル検出回路１３ｄに入力される信号は、パイロットシンボル検出回路２７ｂに入力される信号よりもサブキャリア周波数間隔だけ高い周波数に対応する復調シンボルＣ_m+2 であるから、ΔｆＴｓのピークはサブキャリア周波数間隔だけ高い周波数にシフトする波形６０１ｄとなる。すなわち、波形６０１ｄは、図７（ａ）に示すようにΔｆＴｓ＝２でピークとなる。
【０１１４】
その結果、減算器１７では、加算器３１ｂの出力信号から加算器３１ａの出力信号が減算されて、誤差信号として図７（ｂ）の信号（波形６０２）が得られる。
【０１１５】
以上説明したように、本実施の形態３によれば、搬送波周波数同期用の誤差信号においては、搬送波周波数オフセットΔｆが−３／Ｔｓ〜３／Ｔｓの範囲で得られるので、搬送波周波数の同期範囲が従来例の６倍となり、従来例やすでに説明した実施形態１では同期できないほどの大きな搬送波周波数オフセットΔｆが存在しても搬送波周波数の同期をとることが可能である。
【０１１６】
実施の形態４．
さて、前述した実施の形態３では、パイロットシンボルが時間的に変化しない信号（無変調信号）である場合について説明したが、本発明は、これに限定されず、以下に説明する実施の形態４のように、パイロットシンボルが時間的に変化する信号（変調信号）である場合にも適用可能である。
【０１１７】
まず、構成について説明する。図８は本発明の実施の形態４による搬送波周波数同期回路の一構成例を示すブロック図であり、同図において、４は本実施の形態４のＯＦＤＭ復調器を示している。このＯＦＤＭ復調器４は、前述した実施の形態３によるＯＦＤＭ復調器３と全体的には同様の構成を採用しており、ＯＦＤＭ復調器３とは搬送波周波数同期回路３０から搬送波周波数同期回路４０に置き換えた部分で相違する。したがって、このＯＦＤＭ復調器４においては、ＯＦＤＭ復調器３と同様の構成には同様の番号を付してその説明を省略する。
【０１１８】
搬送波周波数同期回路４０は、前述した搬送波周波数同期回路３０とは、パイロットシンボルの時間的な変化を相殺するための回路を追加した部分で相違する。すなわち、搬送波周波数同期回路４０は、遅延検波回路１１、パイロットシンボルレベル検出回路１３ａ，１３ｂ，１３ｃ，１３ｄの前段にそれぞれ位相回転回路２１，２２ａ，２２ｂ，２２ｃ，２２ｄを設けている。これら位相回転回路２１，２２ａ，２２ｂ，２２ｃ，２２ｄは、いずれも入力信号（復調出力Ｃ_m ，Ｃ_m-1 ，Ｃ_m+1 ，Ｃ_m-2 ，Ｃ_m+2 ）に対してパイロットシンボルの位相回転と逆の回転を与えてパイロットシンボルの時間的な変化をうち消すものである。
【０１１９】
前述した搬送波周波数同期回路３０はパイロットシンボルが時間的に変化しない信号（無変調信号）である場合に適用可能な構成であるため、無変調信号ではない場合すなわち変調信号の場合にはそのままでは適用できない。なぜならば、パイロットシンボルが無変調信号でなく時間的に変化する場合には、図３（ａ）に示した遅延検波回路出力信号の位相が固定値にはならず、図３（ｂ）のように変化してしまうため、平均結果が０となって、パイロットシンボルレベル検出回路１３ａ，１３ｂの出力が０になってしまうからである。
【０１２０】
そこで、本実施の形態４では、このようにパイロットシンボルが無変調信号でない場合に対して搬送波周波数同期をとることができる。パイロットシンボルが無変調信号でない場合には、パイロットシンボルは、予め決められた既知のデータ系列に応じてその位相が変化する信号となる。
【０１２１】
したがって、受信側（ＯＦＤＭ復調器４）では、このデータ系列に応じて受信シンボルの位相がどのように変化するかが予め分かるので、遅延検波回路１１、パイロットシンボルレベル検出回路１３ａ，１３ｂ，１３ｃ，１３ｄの各入力段において、位相回転回路２１，２２ａ，２２ｂ，２２ｃ，２２ｄが受信シンボルの既知の位相変化を除去する。
【０１２２】
すなわち、位相回転回路２１，２２ａ，２２ｂ，２２ｃ，２２ｄは、入力信号に対してパイロットシンボルの位相回転と逆の回転を与えて出力する。その結果、位相回転回路２１，２２ａ，２２ｂ，２２ｃ，２２ｄの出力信号はパイロットシンボル成分に関してはパイロットシンボルが無変調である場合と同じになる。
【０１２３】
これに対し、パイロットシンボルとパイロットシンボル以外のシンボルとの間には相関がないので、パイロットシンボル以外の成分に関しては、ランダムな位相変化をする信号となる。このように、遅延検波回路１１とパイロットシンボルレベル検出回路１３ａ，１３ｂ，１３ｃ，１３ｄの各入力段に位相回転回路２１，２２ａ，２２ｂ，２２ｃ，２２ｄを設けたので、各位相回転回路２１，２２ａ，２２ｂ，２２ｃ，２２ｄの出力信号に含まれるパイロットシンボルは無変調となる。なお、遅延検波回路１１とパイロットシンボルレベル検出回路１３ａ，１３ｂ，１３ｃ，１３ｄおよびそれ以降の回路の動作については、前述した実施の形態３と同様のため、説明を省略する。
【０１２４】
以上説明したように、本実施の形態４によれば、実施の形態２の場合と同様に、位相回転回路によりパイロットシンボルの位相変化が除去されるので、前述した実施の形態３と同様に図７（ｂ）の如く誤差信号が得られ、搬送波周波数の同期範囲が従来例の６倍となる。これにより、従来例やすでに説明した実施の形態２では同期できないほどの大きなΔｆが存在しても搬送波周波数の同期をとることが可能である。
【０１２５】
実施の形態５．
さて、前述した実施の形態１〜４では、搬送波発振器９９の制御電圧をＬＦ１８ａと１８ｂのいずれか一方に決定するために、補正制御回路１９が組み込まれているが、その具体的な構成例については、言及されていない。そこで、一構成例について、実施の形態５により説明する。
【０１２６】
本実施の形態５の搬送波周波数同期回路は、前述した実施の形態１〜４のいずれの構成を適用してもよいので、補正制御回路１９周辺の回路構成についての図示を省略する。図９には、本実施の形態５による補正制御回路の一構成例が示されている。この補正制御回路は、図９に示したように、スイッチ５１、メモリ５２および切換制御回路５３を備えている。
【０１２７】
スイッチ５１は、切換制御回路５３から出力される切換信号ＳＥＬに従ってその出力をＬＦ１８ａとＬＦ１８ｂのいずれか一方へ切り換える。メモリ５２は、第１誤差信号ＥＲＲ１を使用する一定時間を規定する時間データを予め保持している。この一定時間とは、第１誤差信号ＥＲＲ１により十分に周波数オフセットが小さくなるのに必要な時間を表している。切換制御回路５３は、メモリ５２にあらかじめ保持されている時間データを参照して、同期確立開始後（初期動作時）、その時間データが示す一定時間の経過に応じて切換信号ＳＥＬをスイッチ５１へ出力する。
【０１２８】
つぎに、動作について説明する。図９に示した補正制御回路では、搬送波周波数同期の初期動作時にはスイッチ５１はＬＦ１８ａ側にセットされている。初期動作時には、切換制御回路５３によってメモリ５２にあらかじめ保持されている一定時間の経過が確認される。その一定時間が経過した後に切換制御回路５３によりＬＦ１８ｂ側に切り換えるための切換信号ＳＥＬが出力される。これにより、スイッチ５１の出力は、ＬＦ１８ａの第１誤差信号ＥＲＲ１からＬＦ１８ｂの第２誤差信号ＥＲＲ２に切り換えられる。
【０１２９】
以上説明したように、本実施の形態５によれば、制御電圧の補正に使用する誤差信号の切り換えタイミングをメモリ５２に記憶したデータを用いて図るようにしたので、第１誤差信号ＥＲＲ１による制御電圧の補正により周波数オフセットが十分に小さくなってから、第２誤差信号ＥＲＲ２による制御電圧の補正を実施することが可能である。また、外部から切り換えタイミングを与えなくても、簡単な構成でスイッチ５１を切り換えることが可能である。
【０１３０】
また、スイッチ５１により搬送波周波数のオフセット量が一定量よりも小さくなった時のタイミングで使用補正量を切り換えるようにしたので、搬送波周波数オフセットの状況に応じて適切な補正を与えることができる。これにより、搬送波周波数の同期確立をスムーズに行うことが可能である。
【０１３１】
また、同期確立開始後の一定時間の経過でスイッチ５１の切り換えタイミングを図るようにしたので、同期確立の際には、常に一定のタイミングで搬送波周波数の同期動作を実現することが可能である。
【０１３２】
実施の形態６．
さて、前述した実施の形態１〜４では、搬送波発振器９９の制御電圧をＬＦ１８ａと１８ｂのいずれか一方に決定するために、補正制御回路１９が組み込まれているが、その具体的な構成例については、言及されていない。そこで、一構成例について、前述の実施の形態５とは異なる方法を採用した実施の形態６により説明する。
【０１３３】
本実施の形態６の搬送波周波数同期回路は、前述した実施の形態１〜４のいずれの構成を適用してもよいので、補正制御回路１９周辺の回路構成についての図示を省略する。図１０には、本実施の形態６による補正制御回路の一構成例が示されている。この補正制御回路は、図１０に示したように、スイッチ６１とカウンタ回路６２を備えている。
【０１３４】
スイッチ６１は、カウンタ回路６２から出力される切換信号ＳＥＬに従ってその出力をＬＦ１８ａとＬＦ１８ｂのいずれか一方へ切り換える。カウンタ回路６２は、第１誤差信号ＥＲＲ１を使用する一定時間をカウントする値を予め保持している。この値とは、第１誤差信号ＥＲＲ１により十分に周波数オフセットが小さくなるのに必要な時間を表している。
【０１３５】
つぎに、動作について説明する。図１０に示した補正制御回路では、搬送波周波数同期の初期動作時にはスイッチ６１はＬＦ１８ａ側にセットされている。初期動作時には、カウンタ回路６２によってあらかじめセットされた値のカウントアップもしくはカウントダウンが行われる。そのカウント動作が終了すると、カウンタ回路６２からスイッチ６１に対してＬＦ１８ｂ側に切り換えるための切換信号ＳＥＬが出力される。これにより、スイッチ６１の出力は、ＬＦ１８ａの第１誤差信号ＥＲＲ１からＬＦ１８ｂの第２誤差信号ＥＲＲ２に切り換えられる。
【０１３６】
以上説明したように、本実施の形態６によれば、前述した実施の形態５と同様の効果が得られることはもちろん、カウンタ回路６２を用いても、前述した実施の形態５と同様に、第１誤差信号ＥＲＲ１による制御電圧の補正により周波数オフセットが十分に小さくなってから、第２誤差信号ＥＲＲ２による制御電圧の補正を実施することが可能である。
【０１３７】
実施の形態７．
さて、前述した実施の形態１〜６では、制御電圧を補正するための誤差信号の切り換えタイミングをあらかじめ保持する構成を設けていたが、本発明は、これに限定されず、以下に説明する実施の形態７のように、受信されるパイロット信号に基づいて切り換えタイミングを得るようにしてもよい。
【０１３８】
まず、構成について説明する。図１１は本発明の実施の形態７による搬送波周波数同期回路の一構成例を示すブロック図であり、同図において、７は本実施の形態７のＯＦＤＭ復調器を示している。このＯＦＤＭ復調器７は、前述した実施の形態１によるＯＦＤＭ復調器１と全体的には同様の構成を採用しており、ＯＦＤＭ復調器１とは搬送波周波数同期回路１０から搬送波周波数同期回路７０に置き換えた部分で相違する。したがって、このＯＦＤＭ復調器７においては、ＯＦＤＭ復調器１と同様の構成には同様の番号を付してその説明を省略する。
【０１３９】
前述した搬送波周波数同期回路１０には、誤差信号の切り換えのために、補正制御回路が設けられていたが、搬送波周波数同期回路７０には、その補正制御回路に替わってパイロットシンボルレベル検出回路１３ｅ、判定回路７１およびスイッチ７２が設けられる。パイロットシンボルレベル検出回路１３ｅは、パイロットシンボルが伝送されるサブキャリアｍにおける復調出力Ｃ_m を入力して、Ｃ_m に含まれるパイロット信号のレベルを検出して検出結果を出力する。このパイロットシンボルレベル検出回路１３ｅは、ＦＦＴプロセッサ９７（復調出力Ｃ_m ）に接続される。
【０１４０】
判定回路７１は、パイロットシンボルレベル検出回路１３ａ，１３ｂおよび１３ｅに接続され、各信号レベルに基づいてスイッチ７２の切り換えタイミングを求め、その切り換えタイミングでスイッチ７２に対して切換信号ＳＥＬを出力する。スイッチ７２は、判定回路７１から出力される切換信号ＳＥＬに応じてその出力をＬＦ１８ａから１８ｂへ切り換える。
【０１４１】
つぎに、主要な動作について説明する。図１１に示した搬送波周波数同期回路７０では、第１誤差信号ＥＲＲ１を用いて搬送波周波数の同期確立が行われると、先述のとおり搬送波周波数オフセットΔｆは０に近づく。
【０１４２】
その結果、図４（ａ）から明らかなように、パイロットシンボルレベル検出回路１３ａ，１３ｂの出力信号は小さくなる。逆に、パイロットシンボルレベル検出回路１３ｅの出力信号は大きくなる。そこで、これら３つのパイロットシンボルレベル検出回路１３ａ，１３ｂ，１３ｅの出力を観測することで、搬送波周波数の同期状態すなわち搬送波周波数オフセットΔｆが０に近いか否かを判定する。
【０１４３】
判定回路７１では、パイロットシンボル検出回路１３ｅの出力がパイロットシンボルレベル検出回路１３ａ，１３ｂの出力に比べて所定値以上大きくなったときのタイミングで、スイッチ７２への切換信号ＳＥＬを発生する。スイッチ７２にこの切換信号ＳＥＬが入力されると、第１誤差信号ＥＲＲ１から第２誤差信号ＥＲＲ２への出力切り換えが行われる。
【０１４４】
以上説明したように、本実施の形態７によれば、判定回路７１により第１誤差信号ＥＲＲ１から第２誤差信号ＥＲＲ２への切り換え動作が自動的に行われるので、前述した実施の形態５や６のようにあらかじめ切り換えタイミングを用意しておく必要がなくなり、装置の製造過程が単純化されるという利点がある。
【０１４５】
以上、この発明を実施の形態１〜７により説明したが、この発明の主旨の範囲内で種々の変形が可能であり、これらをこの発明の範囲から排除するものではない。
【０１４６】
【発明の効果】
以上説明したように、本発明によれば、同期確立の基準となる信号が使用する周波数周辺の周波数で受信された同期確立の基準となる信号の信号レベルに基づいて求めた搬送波周波数の補正量に従って搬送波周波数の補正制御を行い、その後で、同期確立の基準となる信号の位相変化量に基づいて求めた搬送波周波数の補正量に従って搬送波周波数の補正制御を行うようにしたので、初期の大きな搬送波周波数オフセットに対しても正しく補正量が得られることになり、この補正量に従って補正して搬送波周波数オフセットがある程度小さくなってから同期確立が行われ、これにより、大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１４７】
つぎの発明によれば、同期確立の基準となる信号が送信側で位相変化をもたないように無変調信号として生成された場合には、搬送波信号の位相が時間的に変化しないことから、同期確立のために、基準となる信号が使用する周波数の上下１つずつの周波数で検出される基準となる信号の信号レベルの差分をとって補正量を得る構成と、基準となる信号の位相変化量を補正量として求める構成とを用意すればよく、このような構成により、同期確立の基準となる信号が送信側で位相変化をもたなくても、初期の大きな搬送波周波数オフセットに対しても正しく補正量が得られることになり、この補正量に従って補正して搬送波周波数オフセットがある程度小さくなってから同期確立が行われるため、大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１４８】
つぎの発明によれば、同期確立の基準となる信号が送信側で位相変化をもつように変調信号として生成された場合には、搬送波信号の位相が時間的に変化することから、同期確立のために、まず位相変化を打ち消してから基準となる信号が使用する周波数の上下１つずつの周波数で検出される基準となる信号の信号レベルの差分をとって補正量を得る構成と、まず位相変化を打ち消してから基準となる信号の位相変化量を補正量として求める構成とを用意すればよく、このような構成により、同期確立の基準となる信号が送信側で位相変化をもっていても、初期の大きな搬送波周波数オフセットに対しても正しく補正量が得られることになり、この補正量に従って補正して搬送波周波数オフセットがある程度小さくなってから同期確立が行われるため、大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１４９】
つぎの発明によれば、同期確立の基準となる信号が送信側で位相変化をもたないように無変調信号として生成された場合には、搬送波信号の位相が時間的に変化しないことから、同期確立のために、基準となる信号が使用する周波数よりも大きい周辺の複数の周波数および小さい周辺の複数の周波数でそれぞれ検出された基準となる信号の信号レベルの差分をとって補正量を得る構成と、基準となる信号の位相変化量を補正量として求める構成とを用意すればよく、このような構成により、同期確立の基準となる信号が送信側で位相変化をもたなくても、基準となる信号が使用する周波数の上下１つずつの周波数で受信される搬送波信号から補正量を得る場合よりも幅広い搬送波周波数オフセットに対して補正量が得られ、搬送波周波数オフセットがある程度小さくなってから同期確立が行われるため、より大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１５０】
つぎの発明によれば、同期確立の基準となる信号が送信側で位相変化をもつように変調信号として生成された場合には、搬送波信号の位相が時間的に変化することから、同期確立のために、まず位相変化を打ち消してから基準となる信号が使用する周波数よりも大きい周辺の複数の周波数および小さい周辺の複数の周波数でそれぞれ受信された搬送波信号について信号レベルの差分をとって補正量を得る構成と、まず位相変化を打ち消してから基準となる信号の位相変化量を補正量として求める構成とを用意すればよく、このような構成により、同期確立の基準となる信号が送信側で位相変化をもっていても、基準となる信号が使用する周波数の上下１つずつの周波数で受信された搬送波信号から補正量を得る場合よりも広い搬送波周波数オフセットに対して補正量が得られ、搬送波周波数オフセットがある程度小さくなってから同期確立が行われるため、より大きな搬送波周波数オフセットが存在しても確実に搬送波周波数の同期を確立することが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１５１】
つぎの発明によれば、スイッチにより搬送波周波数のオフセット量が一定量よりも小さくなった時のタイミングで使用補正量を切り換えるようにしたので、搬送波周波数オフセットの状況に応じて適切な補正を与えることができ、これにより、搬送波周波数の同期確立をスムーズに行うことが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１５２】
つぎの発明によれば、同期確立開始後の一定時間の経過でスイッチの切り換えタイミングを図るようにしたので、同期確立の際には、常に一定のタイミングで搬送波周波数の同期動作を実現することが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１５３】
つぎの発明によれば、メモリに一定時間を記憶しておき、切換制御回路によりその一定時間を参照してスイッチの切り換えを制御するようにしたので、外部から切り換えタイミングを与えなくても、簡単な構成でスイッチを切り換えることが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１５４】
つぎの発明によれば、カウント回路によりあらかじめ設定された一定時間をカウントして、スイッチの切り換えタイミングを得るようにしたので、外部から切り換えタイミングを与えなくても、簡単な構成でスイッチを切り換えることが可能な搬送波周波数同期回路が得られるという効果を奏する。
【０１５５】
つぎの発明によれば、基準となる信号の信号レベルが基準となる信号が使用する周波数に隣接する少なくとも２つの周波数で検出された基準となる信号レベルよりも大きくなった時のタイミングで使用補正量を切り換えるようにしたので、あらかじめ切り換えタイミングを用意しておく必要がなく、装置の製造過程を単純化することが可能な搬送波周波数同期回路が得られるという効果を奏する。
【図面の簡単な説明】
【図１】 本発明の実施の形態１による搬送波周波数同期回路の一構成例を示すブロック図である。
【図２】 ＯＦＤＭ方式に使用される伝送フレームのフォーマット例を示す図である。
【図３】 実施の形態１において遅延回路出力を説明する図であり、同図（ａ）は無変調パイロットシンボル成分に対する遅延検波回路１４ａ，１４ｂの出力を示し、同図（ｂ）はパイロットシンボル以外の信号成分に対する遅延検波回路１４ａ，１４ｂの出力を示す。
【図４】 実施の形態１において誤差信号を説明する図であり、同図（ａ）は搬送波周波数オフセットΔｆによる検出されたパイロットシンボルレベルの変化を示し、同図（ｂ）は搬送波周波数オフセットΔｆによる第１誤差信号ＥＲＲ１の変化を示す。
【図５】 本発明の実施の形態２による搬送波周波数同期回路の一構成例を示すブロック図である。
【図６】 本発明の実施の形態３による搬送波周波数同期回路の一構成例を示すブロック図である。
【図７】 実施の形態３において誤差信号を説明する図であり、同図（ａ）は搬送波周波数オフセットΔｆによる検出されたパイロットシンボルレベルの変化を示し、同図（ｂ）は搬送波周波数オフセットΔｆによる第１誤差信号ＥＲＲ１の変化を示す。
【図８】 本発明の実施の形態４による搬送波周波数同期回路の一構成例を示すブロック図である。
【図９】 本発明の実施の形態５による搬送波周波数同期回路の要部の一構成例を示すブロック図である。
【図１０】 本発明の実施の形態６による搬送波周波数同期回路の要部の一構成例を示すブロック図である。
【図１１】 本発明の実施の形態７による搬送波周波数同期回路の一構成例を示すブロック図である。
【図１２】 従来例によるＯＦＤＭ変調器とＯＦＤＭ復調器間の関係を表す一般的な構成図である。
【図１３】 送信シンボルを説明する図であり、同図（ａ）は直並列変換前の送信シンボルのフォーマットを示し、同図（ｂ）は直並列変換後の送信シンボルのフォーマットを示している。
【図１４】 ＯＦＤＭ変調器から出力される送信ＩＦ信号のスペクトルを表す図である。
【図１５】 従来例による搬送波周波数同期回路を示すブロック図である。
【図１６】 送信ベースバンド信号波形の同相成分を示す図である。
【図１７】 受信ベースバンド信号の遅延と相関値との関係を示す図である。
【符号の説明】
１，２，３，４，５，６，７ ＯＦＤＭ復調器、１０，２０，３０，４０，７０ 搬送波周波数同期回路、１１ 遅延検波回路、１２ 位相検出回路、１３ａ，１３ｂ，１３ｃ，１３ｄ パイロットシンボルレベル検出回路、１４ａ，１４ｂ 遅延検波回路、１５ａ，１５ｂ 平均回路、１６ａ，１６ｂ 包絡線検出回路、１７ 減算器、１８ａ，１８ｂ ＬＦ、１９ 補正制御回路、２１，２２ａ，２２ｂ，２２ｃ，２２ｄ 位相回転回路、３１ａ，３１ｂ 加算器、５１，６１，７２ スイッチ、５２ メモリ、５３ 切換制御回路、６２ カウンタ回路、７１ 判定回路。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a carrier frequency synchronization circuit, and more particularly to a carrier frequency synchronization circuit applied to a demodulator that receives and demodulates a multicarrier signal transmitted by orthogonal frequency division multiplexing.
[0002]
[Prior art]
When trying to transmit high-speed data with a short bit width by digital wireless communication, a delayed wave reflected on a building or the like and arriving at a receiver is received with a delay of several to several tens of symbols.
For this reason, interference occurs between symbols, and frequency selective fading occurs. Frequency selective fading significantly distorts the received waveform and greatly degrades transmission characteristics. One method for preventing fading is a method called multicarrier transmission.
[0003]
In multi-carrier transmission, a transmission form is employed in which high-speed data is converted into a plurality of low-speed data with a long bit width after high-speed data is converted on the transmission side, and then a plurality of carriers (subcarriers) are modulated and transmitted. On the receiving side, the received signal of each subcarrier is demodulated and then subjected to parallel-serial conversion to obtain demodulated data. This prevents the occurrence of intersymbol interference. Here, a method called “Orthogonal Frequency Division Multiplexing (OFDM)” is one method for realizing this multicarrier transmission.
[0004]
The OFDM transmission system is described in detail in Reference 1, “OFDM digital transmission system”, Shunji Nakahara, ITU Journal, Vol. 27, No. 1. FIG. 12 shows a general configuration representing the relationship between the OFDM modulator and the OFDM demodulator disclosed in the above-mentioned document 1. In FIG. 12, 8 is an OFDM modulator and 9 is an OFDM demodulator. The OFDM modulator 8 includes a serial-parallel converter 81, an IFFT (inverse fast Fourier transform) processor 82, D / A converters 83a and 83b, LPFs (low-pass filters) 84a and 84b, mixers 85a and 85b, and a π / 2 phase shift. A device 86, a carrier wave oscillator 87, and an adder 88 are provided. The OFDM demodulator 9 is a BPF (band pass filter) 91, mixers 92a and 92b, a π / 2 phase shifter 93, a carrier oscillator 94, LPFs 95a and 95b, and A / D converters 96a, 96b and 17 are FFT ( (Fast Fourier Transform) processor 97 and parallel-serial converter 98.
[0005]
Next, an outline of the OFDM transmission method will be described. FIG. 13 shows a format of a transmission symbol. First, a description will be given using the configuration of the OFDM modulator 8 shown in FIG. In the OFDM modulator 8, as shown in FIG. 13A, N transmission symbols C (N is a natural number) arranged in series are arranged.₀~ C_N-1Are rearranged in parallel by the serial-parallel converter 81.
[0006]
At this time, if the width of the transmission symbols arranged in series is T, the width Ts of the symbols arranged in parallel output from the serial-to-parallel converter 81 is N × T as shown in FIG. Thus, the symbol width is increased N times. Here, transmission symbol C_k(K = 0 to N-1) is generally a_k+ Jb_kThe phase and amplitude change according to the data to be transmitted. a_k, B_kVaries depending on the modulation method employed. For example, in the case of QPSK, it takes any value of ± 1 depending on transmission data, and its phase is π / 4, 3π / 4, −3π / 4, −π / 4 of 4 is taken.
[0007]
N symbols C output from the serial-parallel converter 81₀~ C_N-1Are subjected to inverse Fourier transform processing by the IFFT processor 82, and as a result, an in-phase component I and a quadrature component Q of the transmission baseband signal are generated. The in-phase component signal I and the quadrature component signal Q output from the IFFT processor 82 are converted into analog signals by the D / A converters 83a and 83b, respectively, and then unnecessary harmonic components are removed by the LPFs 84a and 84b. Output signals from the LPFs 84a and 84b are input to the mixers 85a and 85b, respectively, and converted into IF (Intermediate Frequency) signals, respectively.
[0008]
The output signal of the LPF 84a is multiplied in the mixer 85a with the output signal of the carrier wave oscillator 87 that is input to the other input terminal of the mixer 85a. The output signal of the LPF 84b is multiplied in the mixer 85b with the output signal of the π / 2 phase shifter 86 that is input to the other input terminal of the mixer 85b. The π / 2 phase shifter 86 receives the output signal of the carrier wave oscillator 87 and outputs a signal obtained by shifting the phase of the output signal by π / 2. The signals output from the mixers 85a and 85b are added by an adder 88. The transmission IF signal output from the adder 88 is converted into a desired RF (Radio Frequency) signal by a subsequent frequency conversion circuit (not shown), like an ordinary transmitter, and then an antenna (not shown). Is sent from.
[0009]
In the configuration of the above-described OFDM modulator 8, the portion constituted by the D / A converters 83a and 83b, the LPFs 84a and 84b, the mixers 85a and 85b, the π / 2 phase shifter 86, the carrier wave oscillator 87 and the adder 88 is The configuration is the same as the quadrature modulation unit of a general modulator. Therefore, the characteristic parts of the OFDM modulator 8 are the serial-parallel converter 81 and the IFFT processor 82. Here, the inverse Fourier transform process performed by the IFFT processor 82 is a process of converting a signal on the frequency axis into a signal on the time axis.
[0010]
Therefore, N transmission symbol symbols C input to IFFT processor 82₀~ C_N-1Can be regarded as N signals arranged on the frequency axis. That is, each of N transmission symbols C₀~ C_N-1The IFFT processor 82 implements the modulation processing in multicarrier transmission in which each of N carriers (subcarriers) is modulated by the IF method.
[0011]
FIG. 14 is a diagram showing a spectrum of a transmission IF signal output from the OFDM modulator 8. In FIG. 14, each of N transmission symbols C₀~ C_N-1Each N subcarriers W modulated by₀~ W_N-1Are shown on the frequency axis. Here, since the interval between subcarriers is as small as 1 / Ts, the feature of the OFDM scheme is that adjacent subcarriers overlap each other.
[0012]
Next, the demodulation operation in the OFDM system will be described using the configuration of the general OFDM demodulator 9 shown in FIG. An RF signal received by an antenna (not shown) is converted into a reception IF signal by a frequency conversion circuit (not shown) in the same manner as a general receiver. The reception IF signal is first input to the BPF 91. The BPF 91 removes unnecessary frequency components included in the reception IF signal.
[0013]
The output signal of the BPF 91 is branched into two and input to the mixers 92a and 92b, respectively. One signal branched into two after output from the BPF 91 is multiplied by the output signal of the carrier wave oscillator 94 input to the other input terminal of the mixer 92a in the mixer 92a. The output signal of the mixer 92a is input to the LPF 15a, and unnecessary harmonic components are removed to become in-phase components of the baseband signal.
[0014]
The other signal branched into two after the output of the BPF 91 is multiplied in the mixer 92b with the output signal of the π / 2 phase shifter 93 input to the other input terminal of the mixer 92b. The π / 2 phase shifter 93 receives the output signal of the carrier wave oscillator 94 and outputs a signal obtained by shifting the phase of the output signal by π / 2. The output signal of the mixer 92b is input to the LPF 95b, where unnecessary harmonic components are removed and become orthogonal components of the baseband signal. The output signals of the LPFs 95a and 95b are respectively input to A / D converters 96a and 96b, converted into digital signals, and then input to the FFT processor 97.
[0015]
The FFT processor 97 performs a Fourier transform process on the input in-phase component signal I and quadrature component signal Q to obtain N demodulated symbols C.₀~ C_N-1Is output. The signal output from the FFT processor 97, that is, N demodulated symbols arranged in parallel, is converted into N demodulated symbols arranged in series by the parallel-serial converter 98 and output from the OFDM demodulator 9.
[0016]
In the configuration of the above-described OFDM demodulator 9, a portion including the BPF 91, the mixers 92a and 92b, the π / 2 phase shifter 93, the carrier wave oscillator 94, the LPFs 95a and 95b, and the A / D converters 96a and 96b is generally used. This configuration is the same as that often used as a quasi-synchronous detector of a demodulator. Therefore, the characteristic parts of the OFDM demodulator 9 are an FFT processor 97 and a parallel-serial converter 98. By these two parts, the reverse process of the process performed by the serial-parallel converter 81 and the IFFT processor 82 in the OFDM modulator 8 is performed to reproduce the transmission symbol.
[0017]
That is, if the FFT process is performed on the IFFT signal, the original signal before the IFFT can be obtained from the FFT-processed signal, so that N demodulated symbols C output from the FFT processor 97 are obtained.₀~ C_N-1Is the transmission symbol C₀~ C_N-1Matches. That is, demodulation processing in multicarrier transmission for demodulating N modulated waves is realized by the FFT processor 97 in the OFDM method.
[0018]
As described above, in the OFDM system, the frequency interval between subcarriers is 1 / Ts. In general, the subcarrier interval 1 / Ts is as small as several kHz. Then, the difference (frequency offset) between the oscillation frequencies of the carrier wave oscillators 87 and 94 becomes a problem. If an offset exists in the carrier frequency, interference occurs between subcarriers in the OFDM demodulator 9.
[0019]
That is, the symbol C transmitted on the subcarrier k on the transmission side_kHowever, due to the carrier frequency offset, the receiving side also mixes with subcarriers around the original subcarrier k, such as k-1, k, k + 1,. The transmission characteristics are significantly degraded due to interference. Therefore, the OFDM demodulator 9 requires a carrier frequency synchronization circuit for matching the oscillation frequency of the carrier oscillator 94 with the oscillation frequency of the carrier oscillator 87, that is, the carrier frequency of the received IF signal.
[0020]
A conventional carrier frequency synchronization circuit will be described. Fig. 15 shows Reference 2 "A study on a new frequency synchronization method using guard period in OFDM", Takashi Seki, Noboru Taga, Tatsuya Ishikawa, Television Society Technical Report, Vol.19, No.38, pp.13-18. 1 is a configuration diagram of an OFDM demodulator including a conventional carrier frequency synchronization circuit shown in (1995). The same parts as those of the general OFDM demodulator 9 shown in FIG.
[0021]
The OFDM demodulator shown in FIG. 15 is provided with a carrier wave oscillator 99 that makes the oscillation frequency variable in place of the carrier wave oscillator 94 described above, and a carrier frequency that makes the oscillation frequency of the carrier wave oscillator 99 variable according to the control voltage. A synchronization circuit 100 is added. The carrier frequency synchronization circuit 100 delays the input signal by one symbol time (= Ts) and outputs the delay signal 101, the output signals of the A / D converters 96a and 96b, and the output signal of the delay circuit 101. A correlator 102 that inputs and obtains a correlation value of these signals and outputs the result, a phase detection circuit 103 that inputs an output signal of the correlator 102 and detects a phase of the signal, and an output signal of the phase detection circuit 103 And a LF (loop filter) 105 that removes unnecessary noise components from the output signal of the latch 104 and outputs the result. Here, the output signal of the LF 105 is a voltage for controlling the oscillation frequency of the voltage controlled carrier oscillator 99.
[0022]
The correlator 102 is a complex multiplier 102b that outputs a complex conjugate of an input signal, a complex multiplier of the output signal of the A / D converters 96a and 96b and the output signal of the conjugate circuit 102b, and outputs the result. 102a and a moving average circuit 102c for obtaining a moving average of the output signal of the complex multiplier 102a and outputting the result.
[0023]
Next, the operation of the carrier frequency synchronization circuit 100 will be described. In the carrier frequency synchronization circuit 100 shown in FIG. 15, the output signals (digitized reception baseband signals) of the A / D converters 96 a and 96 b are respectively branched into two, and one output signal is input to the correlator 102. The other is input to the delay circuit 101 and delayed by one symbol time (= Ts). In the correlator 102, the correlation of the input signal is obtained by the conjugate circuit 102b, the complex multiplier 102a, and the moving average circuit 102c. That is, the correlation between the currently received baseband signal and the baseband signal received before Ts time is obtained.
[0024]
Since the carrier frequency synchronization circuit 100 is a circuit using the fact that a repetitive component is inserted into the transmitted baseband signal, the repetitive component inserted into the transmitted baseband signal will be described here. Complement. FIG. 16 shows the in-phase component of the transmission baseband signal waveform, and FIG. 17 shows the relationship between the delay of the reception baseband signal and the correlation value. This in-phase component is an output signal waveform of the D / A converter 83a of the OFDM modulator 8 shown in FIG. 12, and the output of the A / D converter 16a in the OFDM demodulator shown in FIG. 15 is signal-converted. Is.
[0025]
As shown in FIG. 16, there is a period called a guard interval having a width of Tg at the beginning of the transmission baseband signal, and the same waveform as the waveform of the width Tg at the end of the transmission baseband signal is copied during this period. Inserted. The part excluding the guard interval is called a valid symbol. The guard interval is inserted for the purpose of reducing the influence of the delayed wave. The conventional carrier frequency synchronization circuit 100 shown in FIG. 15 is a circuit that synchronizes the carrier frequency using the point that the waveform of the guard interval is the same as the waveform of the end portion of the effective symbol.
[0026]
That is, since the waveform of the received guard interval part and the waveform of the last part of the effective symbol are the same, it shows a strong correlation. Therefore, the received baseband signal is branched into two and one is delayed by Ts time. If correlation is taken, a large correlation output can be obtained every Ts time as shown in FIG. This correlation output includes a carrier frequency offset component as described below. The conventional method detects this component and synchronizes the carrier frequency.
[0027]
In FIG. 17, the signal rA1 (t) of the guard interval portion A1 of the received baseband signal can be expressed by the following equation (1) when expressed as a complex number.
[0028]
[Expression 1]

[0029]
Here, ρ (t) is an envelope, and θ (t) is a phase. On the other hand, the signal rA2 (t) of the portion A2 received after the time Ts is obtained by rotating the same waveform as that of the portion A1 by the phase of the carrier frequency offset, and can be expressed as the following equation (2).
[0030]
[Expression 2]

[0031]
Here, Δf is a carrier frequency offset. The signal represented by the above equation (1) corresponds to the output signal of the delay circuit 101 in the configuration of the carrier frequency synchronization circuit 100, and the signal represented by the above equation (2) is the output of the A / D converters 96a and 96b. It corresponds to the signal. Since the output of the conjugate circuit 102b is a complex conjugate signal of the signal of the above equation (1), the following equation (3) is obtained.
[0032]
[Equation 3]

[0033]
Here, * in the above formula (3) represents a complex conjugate. Since the output signal of the complex multiplier 102a is the product of the above equations (2) and (3), the following equation (4) is obtained.
[0034]
[Expression 4]

[0035]
Since the above equation (4) includes a carrier frequency offset Δf, this carrier frequency offset Δf is detected by a circuit in the subsequent stage. Since the moving average circuit 102c averages the input signals for the guard interval period Tg, the output signal of the moving average circuit 102c is expressed by the following equation (5).
[0036]
[Equation 5]

[0037]
Where Y is ρ (t)²Is an averaged value over the Tg time, and is a substantially constant value. The phase detection circuit 103 detects the phase of the signal represented by the above equation (5). Accordingly, since the output signal of the phase detection circuit 24 is 2πΔfTs, a signal proportional to the carrier frequency offset Δf is obtained. This 2πΔfTs is used as an error signal for carrier frequency synchronization. As shown in FIG. 17, this error signal is obtained at the time when the correlation value is at a peak, and is sampled by the latch 104 at the symbol period.
[0038]
An unnecessary noise component is removed from the output signal of the latch 104 by the LF 105 and used as a control voltage of the voltage controlled carrier oscillator 99. The voltage-controlled carrier oscillator 99 decreases the output frequency when the control voltage is a positive voltage, and conversely increases it when the control voltage is a negative voltage. Therefore, when Δf> 0, the oscillation frequency is corrected to be small, and when Δf <0, it is corrected to be large, so that the error signal represents a correction amount.
In this way, control is performed so that the carrier frequency offset Δf becomes 0, and synchronization of the carrier frequency is established.
[0039]
[Problems to be solved by the invention]
Since the conventional carrier frequency synchronization circuit is configured to synchronize the carrier frequency using the same waveform repeatedly transmitted as described above, the error signal for carrier frequency synchronization is 2πΔfTs as described above. This value is equal to the phase angle (in radians) that changes within the Ts time due to the carrier frequency offset Δf.
[0040]
Therefore, the range of values that this value can take is limited to -π to π as shown in equation (6). This relationship can be expressed by the following equation. That is,
−π <2πΔfTs <π (6)
It is.
[0041]
Therefore, the range of the carrier frequency offset Δf that can be synchronized by the carrier frequency synchronization circuit 100 as described above is limited to a range of ± 1 / (2Ts) as expressed by the following equation (7). That is,
-1 / (2Ts) <Δf <1 / (2Ts) (7)
It is.
[0042]
Looking at the relationship between adjacent subcarriers, as shown in FIG. 14, since 1 / Ts is the subcarrier frequency interval, the synchronization range is half of the subcarrier frequency interval. If Δf is outside this range, synchronization cannot be achieved. In general, the subcarrier frequency interval is as small as several kHz. As a specific example, the subcarrier frequency interval of a digital audio broadcasting system in Europe is 4 kHz. In FIG. 12, the carrier frequency offset is caused by a difference in oscillation frequency between the carrier oscillator 87 on the transmission side and the carrier oscillator 94 on the reception side.
[0043]
Therefore, as an example, the accuracy of the carrier wave oscillators 87 and 94 is ± 1 ppm (= ± 1 × 10 ×).^-6), Assuming that the RF (Radio Frequency) frequency is 1.9 GHz, the value of the maximum carrier frequency offset Δf is Δf_max= ± 3.8 kHz. In this case, assuming a system with a subcarrier frequency interval of 4 kHz, the conventional method can only synchronize up to a frequency offset up to ± 2 kHz, and thus cannot synchronize with a large frequency offset of ± 3.8 kHz.
[0044]
As described above, the configuration such as the above-described carrier frequency synchronization circuit 100 has a problem that synchronization cannot be performed when a carrier frequency offset equal to or greater than ½ of the subcarrier frequency interval exists.
[0045]
The present invention has been made to solve the above problems, and as a carrier frequency synchronization circuit for an OFDM demodulator, synchronization of carrier frequency is reliably established even when a large carrier frequency offset exists. An object of the present invention is to obtain a carrier frequency synchronization circuit that can be used.
[0046]
[Means for Solving the Problems]
In order to solve the above-described problems and achieve the object, the carrier frequency synchronization circuit according to the present invention is configured such that, on the transmission side, a plurality of signals including a reference signal for establishing carrier frequency synchronization are orthogonal frequency division multiplexed. This is applied to a system that corrects the carrier frequency according to the state of the reference signal in the carrier signal generated on the transmitting side in order to establish the synchronization of the carrier frequency on the receiving side. In the carrier frequency synchronization circuit used on the reception side of the system, the correction amount of the carrier frequency is obtained based on the signal level of the reference signal received at a frequency around the frequency used by the reference signal. First generation means, second generation means for obtaining a correction amount of the carrier frequency based on the phase change amount of the reference signal, and correction obtained by the first generation means Characterized in that it and a control means for correcting control of the carrier frequency correction amount of the order which has been determined by the second generating means.
[0047]
According to the present invention, the correction control of the carrier frequency is performed according to the correction amount of the carrier frequency obtained based on the signal level of the signal serving as the reference for synchronization establishment received at a frequency around the frequency used by the signal used as the reference for establishment of synchronization. After that, correction control of the carrier frequency is performed according to the correction amount of the carrier frequency obtained based on the phase change amount of the signal that is a reference for establishing synchronization. The correct correction amount can be obtained, and the synchronization is established after the carrier frequency offset is reduced to some extent by correcting according to this correction amount. This ensures that the carrier frequency is synchronized even if a large carrier frequency offset exists. Can be established.
[0048]
In the carrier frequency synchronization circuit according to the next invention, the reference signal is a signal generated as an unmodulated signal so that there is no phase change on the transmission side, and the first generating means A pair of delay detection circuits that respectively delay detect the carrier signals received at the upper and lower frequencies of each frequency used by the signal, and a pair that averages the signals detected by the pair of delay detection circuits. An average circuit, a pair of envelope detection circuits for detecting a signal level based on envelopes of signals averaged by the pair of average circuits, and a signal level detected by the pair of envelope detection circuits, respectively. An arithmetic circuit that obtains the correction amount by taking a difference between the second generation means, a delay detection circuit that delay-detects the reference signal, and the delay detection circuit Characterized in that it contains a phase detection circuit for obtaining the correction amount by detecting the phase variation of more delayed detection signal.
[0049]
According to the present invention, when the signal that is the reference for establishing synchronization is generated as an unmodulated signal so that there is no phase change on the transmission side, the phase of the carrier signal does not change with time. For the establishment, a configuration for obtaining a correction amount by taking a difference in signal level of a reference signal detected at a frequency one above and below a frequency used by the reference signal, and a phase change of the reference signal It is sufficient to prepare a configuration for obtaining the amount as a correction amount. With such a configuration, even if the signal that is a reference for establishing synchronization does not have a phase change on the transmission side, it can be used for an initial large carrier frequency offset The correct correction amount will be obtained, and the carrier frequency offset will be reduced to some extent after correction according to this correction amount, so synchronization will be established, so even if there is a large carrier frequency offset It is possible to establish synchronization indeed the carrier frequency.
[0050]
In the carrier frequency synchronization circuit according to the next invention, the reference signal is a signal generated as a modulation signal so as to have a phase change on the transmission side, and the first generation means A pair of first phase rotation circuits for removing the phase change of the carrier wave signal received at one frequency above and below the frequency to be used, and the carrier wave from which the phase change has been removed by the pair of first phase rotation circuits, respectively. A pair of delay detection circuits for delay detection of the signals, a pair of average circuits for averaging the signals respectively delayed detected by the pair of delay detection circuits, and an envelope of the signals averaged by the pair of average circuits, respectively A pair of envelope detection circuits for detecting a signal level based on a line, and the difference between the signal levels detected by the pair of envelope detection circuits, respectively. A second phase rotation circuit for removing a phase change of the reference signal, and the reference from which the phase change has been removed by the second phase rotation circuit. And a phase detection circuit that detects a phase change amount of the signal delayed detected by the delay detection circuit and obtains the correction amount.
[0051]
According to the present invention, when the signal serving as a reference for establishing synchronization is generated as a modulation signal so as to have a phase change on the transmission side, the phase of the carrier signal changes with time. First, the phase change is first canceled and then the difference between the signal levels of the reference signal detected at the frequency one above and below the frequency used by the reference signal is obtained to obtain the correction amount. It is only necessary to prepare a configuration in which the phase change amount of the reference signal is calculated as a correction amount after canceling out the signal, and even if the signal used as the reference for establishing synchronization has a phase change on the transmission side, the A correct correction amount can be obtained even for a large carrier frequency offset, and synchronization is established after the carrier frequency offset is reduced to some extent by correcting according to this correction amount. Therefore, surely even if there is a large carrier frequency offset is possible to establish synchronization of the carrier frequency.
[0052]
In the carrier frequency synchronization circuit according to the next invention, the reference signal is a signal generated as an unmodulated signal so that there is no phase change on the transmission side, and the first generating means A plurality of delay detection circuits for delay-detecting the carrier signals respectively received at a plurality of peripheral frequencies larger than a frequency used by the signal and a plurality of peripheral frequencies smaller than the frequency used by the signal, and delayed by the plurality of delay detection circuits, respectively. A plurality of average circuits that average the detected signals, a plurality of envelope detection circuits that detect signal levels based on the envelopes of the signals averaged by the plurality of average circuits, and the plurality of envelopes Of the signal levels detected by the detection circuit, the signal level detected at a frequency higher than the frequency used by the reference signal. And a calculation circuit that obtains the correction amount by taking a difference between the signal level received at a frequency lower than the frequency used by the reference signal and the second generation means includes the reference And a phase detection circuit that detects a phase change amount of the signal delayed detected by the delay detection circuit and obtains the correction amount.
[0053]
According to the present invention, when the signal that is the reference for establishing synchronization is generated as an unmodulated signal so that there is no phase change on the transmission side, the phase of the carrier signal does not change with time. In order to establish a configuration, a correction amount is obtained by taking the difference in signal level of a reference signal detected at a plurality of peripheral frequencies larger and lower than a frequency used by the reference signal, respectively. And a configuration for obtaining the phase change amount of the reference signal as a correction amount. With this configuration, even if the reference signal for establishing synchronization does not have a phase change on the transmission side, the reference A correction amount can be obtained with respect to a wider carrier frequency offset than when a correction amount is obtained from a carrier signal received at a frequency one above and below a frequency used by the signal to be used. For establishing synchronization after preparative is decreased to a certain extent is carried out, it is possible to establish synchronization more surely carrier frequencies even large carrier frequency offset exists.
[0054]
In the carrier frequency synchronization circuit according to the next invention, the reference signal is a signal generated as a modulation signal so as to have a phase change on the transmission side, and the first generation means A plurality of first phase rotation circuits for removing phase changes of the carrier signal received at a plurality of peripheral frequencies larger than a frequency to be used and a plurality of peripheral frequencies smaller than the frequency to be used; and the plurality of first phase rotation circuits A plurality of delay detection circuits that respectively delay-detect the carrier signals from which phase changes have been removed, a plurality of average circuits that average the signals that are respectively delayed-detected by the plurality of delay detection circuits, and the plurality of average circuits A plurality of envelope detection circuits for detecting a signal level based on the envelopes of the signals averaged by the plurality of envelope detection circuits, and the plurality of envelope detection circuits. Among the detected signal levels, the sum of the signal levels detected at a frequency higher than the frequency used by the reference signal and the frequency received by the reference signal are lower than the frequency used by the reference signal. An arithmetic circuit that obtains the correction amount by taking a difference from the sum of the signal levels, and wherein the second generation means removes a phase change of the reference signal, and A delay detection circuit for delay-detecting the reference signal from which the phase change has been removed by the second phase rotation circuit; and a phase for obtaining the correction amount by detecting a phase change amount of the signal delayed-detected by the delay detection circuit And a detection circuit.
[0055]
According to the present invention, when the signal serving as a reference for establishing synchronization is generated as a modulation signal so as to have a phase change on the transmission side, the phase of the carrier signal changes with time. First, after canceling the phase change, the amount of correction is calculated by taking the difference in signal level for each of the carrier signals received at a plurality of peripheral frequencies larger than the frequency used by the reference signal and at a plurality of smaller peripheral frequencies. And a configuration in which the phase change amount of the reference signal is first calculated as a correction amount after canceling the phase change, and with this configuration, the signal that becomes the reference for establishing synchronization is phase-shifted on the transmission side. Even if there is a change, the carrier frequency is off wider than when the correction amount is obtained from the carrier signal received at the frequency one above and below the frequency used by the reference signal. Therefore, even if a larger carrier frequency offset exists, it is possible to reliably establish carrier frequency synchronization. is there.
[0056]
In the carrier frequency synchronization circuit according to the next invention, the control means uses the correction amount obtained by the first generating means at the timing when the offset amount of the carrier frequency becomes smaller than a predetermined amount. 2 is a switch for switching to the correction amount obtained by the generating means.
[0057]
According to the present invention, since the use correction amount is switched at the timing when the offset amount of the carrier frequency becomes smaller than a certain amount by the switch, an appropriate correction can be given according to the situation of the carrier frequency offset. This makes it possible to smoothly establish synchronization of the carrier frequency.
[0058]
The carrier frequency synchronization circuit according to the next invention is characterized in that the timing is supplied to the switch when a fixed time elapses after the start of synchronization establishment.
[0059]
According to the present invention, since the switching timing of the switch is achieved after a lapse of a fixed time after the start of synchronization establishment, the carrier frequency synchronization operation can always be realized at a constant timing when synchronization is established. It is.
[0060]
The carrier frequency synchronization circuit according to the next invention further comprises a memory that stores the predetermined time, and a switching control circuit that controls switching of the switch with reference to the predetermined time stored in the memory. Features.
[0061]
According to the present invention, since the predetermined time is stored in the memory, and the switching of the switch is controlled by referring to the predetermined time by the switching control circuit, it is simple even without giving the switching timing from the outside. It is possible to switch the switch in the configuration.
[0062]
The carrier frequency synchronization circuit according to the next invention further includes a count circuit for counting the predetermined time set in advance.
[0063]
According to the present invention, the switch switching timing is obtained by counting a predetermined time set in advance by the count circuit, so that the switch can be switched with a simple configuration without giving the switching timing from the outside. Is possible.
[0064]
In the carrier frequency synchronization circuit according to the next invention, the control means is such that the signal level of the reference signal received at the frequency used by the reference signal is adjacent to the frequency used by the reference signal. The second generation means obtains the use correction amount from the correction amount obtained by the first generation means at a timing when the signal level of the reference signal detected at at least two frequencies is greater than a predetermined value. It is a switch for switching to a correction amount.
[0065]
According to the present invention, the signal level of the reference signal is used when the signal level becomes higher than the signal level of the reference signal detected at at least two frequencies adjacent to the frequency used by the reference signal. Since the correction amount is switched, it is not necessary to prepare a switching timing in advance, and the manufacturing process of the apparatus can be simplified.
[0066]
DETAILED DESCRIPTION OF THE INVENTION
Exemplary embodiments of a carrier frequency synchronization circuit according to the present invention will be explained below in detail with reference to the accompanying drawings.
[0067]
Embodiment 1 FIG.
Embodiment 1 is an example in which a pilot signal (generally an unmodulated pilot symbol) is transmitted using a specific subcarrier by the OFDM method. Here, an unmodulated pilot symbol is a symbol composed of data that does not change in time, such as all “0” or all “1”.
[0068]
First, the configuration will be described. FIG. 1 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to the first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an OFDM demodulator according to the first embodiment. In FIG. 1, the same parts as those in the conventional example are designated by the same reference numerals and the description thereof is omitted. Of the output signal of the FFT processor 97, subcarrier m represents a subcarrier number for transmitting a pilot symbol, and C_m-1, C_m, C_{m + 1}Represents demodulated symbols on subcarriers m-1, m, and m + 1, respectively.
[0069]
The OFDM demodulator 1 shown in FIG. 1 has a carrier frequency synchronization circuit 10 that replaces the carrier frequency synchronization circuit 100 in the overall configuration of the OFDM demodulator of FIG. Similar to the carrier frequency synchronization circuit 100 (see FIG. 15) described above, the carrier frequency synchronization circuit 10 performs voltage control of the carrier oscillator 99 to establish carrier frequency synchronization. The carrier frequency synchronization circuit 10 is connected to the output of the FFT processor 97 and is different from the carrier frequency synchronization circuit 100 described above in connection.
Specifically, the parallel signal from the FFT processor 97 (demodulated signal C₀~ C_N-1) Are connected to the subcarrier frequency at which the pilot symbol is transmitted and the outputs at the subcarrier frequencies around it (one at the top and one below).
[0070]
As shown in FIG. 1, the carrier frequency synchronization circuit 10 includes pilot symbol level detection circuits 13a and 13b, a first generation circuit including an adder 17 and an LF 18a, a delay detection circuit 11, a phase detection circuit 12 and an LF 18b. 2 generation circuit and correction control circuit 19 are provided.
[0071]
In the first generation circuit, the pilot symbol level detection circuit 13a has a frequency lower than the subcarrier m-1 whose number is one smaller than the subcarrier m in which the pilot symbol is transmitted, that is, the subcarrier frequency in which the pilot symbol is transmitted. Is the demodulated output C on a subcarrier whose subcarrier spacing is lower_m-1Enter C_m-1Is a circuit that detects the level of a pilot symbol component included in the signal and outputs a detection result.
[0072]
Similarly, pilot symbol level detection circuit 13b has subcarrier m + 1 that is one number higher than subcarrier m in which pilot symbols are transmitted, that is, a frequency that is higher than the subcarrier frequency in which pilot symbols are transmitted by the subcarrier interval. Demodulated output C in subcarrier_{m + 1}Enter C_{m + 1}Is a circuit that detects the level of a pilot symbol component included in the signal and outputs a detection result.
[0073]
The pilot symbol level detection circuit 13a includes a delay detection circuit 14a, an average circuit 15a, and an envelope detection circuit 16a. The pilot symbol level detection circuit 13b includes a delay detection circuit 14b, an average circuit 15b, and an envelope detection circuit 16b. Yes. The delay detection circuits 14a and 14b each receive an input signal (demodulation output C_m-1, C_{m + 1}) And delay detection is output. The averaging circuits 15a and 15b receive the output signals of the delay detection circuits 14a and 14b, respectively, average the input signals for a predetermined time, and output the results.
[0074]
The envelope detection circuits 16a and 16b receive the output signals of the averaging circuits 15a and 15b, respectively, detect the magnitude of the envelope of the input signals, and output the results. Adder 17 subtracts the output of pilot symbol level detection circuit 13a from the output of pilot symbol level detection circuit 13b and outputs the result. Here, the output signal of the subtracter 17 becomes the first error signal ERR1 for carrier frequency synchronization.
The LF 18a removes unnecessary noise components from the first error signal ERR1, which is the output signal of the subtractor 17, and outputs the result.
[0075]
In the second generation circuit, the delay detection circuit 11 includes a demodulation signal C of the FFT processor 97._mDemodulated output C in subcarrier m connected to the output and carrying pilot symbols_mTo perform delayed detection. The phase detection circuit 12 obtains the phase of the output signal of the delay detection circuit 11 and outputs the result. Here, the output signal of the phase detection circuit 12 becomes the second error signal ERR2. The LF 18b removes unnecessary noise components from the second error signal ERR2, which is an output signal of the phase detection circuit 12, and outputs the result.
[0076]
  The correction control circuit 19 is connected to the LFs 18a and LF18b and the carrier wave oscillator 99, and is connected to the first error signals ERR1 and ERR2 at a predetermined timing.ZOne of them is supplied as a control voltage for the carrier wave oscillator 99. Here, the predetermined timing is a timing when the offset amount of the carrier frequency becomes smaller than a certain amount, and the use correction amount is the first error signal ERR1 (voltage control correction amount obtained by the first generation circuit). To the second error signal ERR2 (the correction amount obtained by the second generation circuit). Various methods, such as time measurement, can be considered for taking this predetermined timing.
[0077]
FIG. 2 shows a format example of a transmission frame used in the OFDM system. The format of the transmission frame is composed of null symbols, data, pilot symbols, and data as shown in FIG. An unmodulated null symbol is inserted as the first symbol. This position is the demodulated symbol C₀It corresponds to the position of. After that, data is inserted. In Embodiment 1, since the pilot signal data sequence is known, the position of the pilot symbol is known, and the demodulated symbol C_mIt corresponds to the position of.
[0078]
Next, the error signal will be described. First, a method for generating the first error signal ERR1 will be described. If the carrier frequency offset Δf is 0 Hz, the received pilot symbol appears only in the subcarrier m, but if the carrier frequency offset Δf exists, a part of the power of the received pilot symbol is adjacent to the subcarrier (subcarrier). leaks to m−1 or subcarrier m + 1). When the carrier frequency offset Δf is negative, a part of the received pilot symbol power leaks to the subcarrier m−1, and when the carrier frequency offset Δf is positive, a part of the received pilot symbol power is Leaks into subcarrier m + 1.
[0079]
The level of pilot symbols leaking to adjacent subcarriers varies depending on the magnitude of the carrier frequency offset Δf. Therefore, the direction and magnitude of the carrier frequency offset Δf can be known by detecting the level of the pilot symbol included in the demodulated signal of two subcarriers adjacent to the subcarrier m in which the pilot symbol is transmitted. By using information indicating the direction and magnitude of the carrier frequency offset Δf as an error signal for carrier frequency synchronization, carrier frequency synchronization can be achieved.
[0080]
Next, a pilot symbol level detection method will be described. FIG. 3 is a diagram for explaining the output of the delay circuit. FIG. 3 (a) shows the outputs of the delay detection circuits 14a and 14b for the unmodulated pilot symbol components, and FIG. 3 (b) shows the delay for the signal components other than the pilot symbols. The outputs of the detection circuits 14a and 14b are shown. 4A and 4B are diagrams for explaining the error signal. FIG. 4A shows changes in the pilot symbol level detection circuits 13a and 13b due to the carrier frequency offset Δf, and FIG. 4B shows the first error caused by the carrier frequency offset Δf. The change of the signal ERR1 is shown.
[0081]
Here, assuming that the carrier frequency offset Δf is negative, the demodulated output C_{m- 1}Includes a non-modulated pilot symbol component and a symbol component other than the pilot symbol. The amplitude and phase of symbols other than pilot symbols vary depending on data to be transmitted. The pilot symbol level detection circuit 13a extracts the level of only the pilot symbol and outputs the level. In the output signal of the delay detection circuit 14a, a delay detection output for pilot symbols and a delay detection output for symbols other than pilot symbols are mixed.
[0082]
Here, as shown in FIG. 3A, the delayed detection output for the pilot symbol is a signal whose phase does not change with time. On the other hand, as shown in FIG. 3B, the delayed detection output for symbols other than the pilot symbols is a signal whose phase changes randomly.
[0083]
Here, FIG. 3B shows an example in which the modulation method is QPSK, and the phase of the output signal of the delay detection circuit takes any one of 0, π / 2, π, and −π / 2. When the output signal of the delay detection circuit 14a is averaged by the averaging circuit 15a, the average envelope for the pilot symbol components is large, whereas the average envelope for the symbol components other than the pilot symbols is almost 0 (zero). .
[0084]
Therefore, when the envelope detector 16a detects the envelope of the output signal of the averaging circuit 15a, the result is 0 (zero) for symbols other than the pilot symbol, and a level for only the pilot symbol component is obtained. It is done. Thus, pilot symbol level detection circuit 13a outputs the level of only the pilot symbol component among the signal components included in subcarrier number m-1.
[0085]
As shown in FIG. 4A, the pilot symbol level included in the subcarrier number m−1 is when the carrier frequency offset Δf is in the negative direction by the subcarrier frequency interval, that is, Δf = −1 / Ts ( The waveform 301a of the signal is maximized when ΔfTs = −1) and becomes smaller as Δf is away from −1 / Ts (as ΔfTs is away from −1).
[0086]
The same applies to pilot symbol level detection circuit 13b, which outputs the level of only the pilot symbol component among the signal components included in subcarrier m + 1. As shown in FIG. 4A, the pilot symbol level included in the subcarrier m + 1 is the case where the carrier frequency offset Δf is in the positive direction by the subcarrier frequency interval, that is, Δf = 1 / Ts (ΔfTs = 1). In this case, the signal waveform 301b is maximized and becomes smaller as Δf is separated from 1 / Ts (as ΔfTs is separated from 1).
[0087]
The subtracter 17 subtracts the output of the pilot symbol level detection circuit 13a from the output of the pilot symbol level detection circuit 13b. As a result, the output signal of the subtracter 17 has a waveform 302 shown in FIG. Accordingly, the first error signal ERR1 for carrier frequency synchronization is obtained in the range where the carrier frequency offset Δf is −2 / Ts to 2 / Ts. The first error signal ERR1 functions as a control voltage of the voltage controlled carrier oscillator 99 after the noise component is removed by the LF 18a.
[0088]
Next, a method for generating the second error signal ERR2 will be described. After the carrier frequency offset Δf becomes sufficiently small due to the first error signal ERR1, the symbol component input to the delay detection circuit 11 is almost only the pilot signal component.
When the pilot symbol input to the delay detection circuit 11 is represented by a complex number, it is represented by the following equation (8).
[0089]
[Formula 6]

[0090]
Here, ρ and θ are an envelope and a phase, respectively, and are constant values that do not change in the case of an unmodulated pilot symbol. Since the delay detection circuit 28c performs delay detection of the input signal every symbol (every Ts time) and outputs the result, the output signal is expressed by the following equation (9).
[0091]
[Expression 7]

[0092]
The phase detection circuit 12 detects and outputs the phase 2πΔfTs of the output signal from the delay detection circuit 11 expressed by the above equation (8). The output signal from the phase detection circuit 11 becomes the second error signal ERR2. Therefore, the second error signal ERR2 is a signal (= 2πΔfTs) proportional to the carrier frequency offset Δf. The second error signal ERR2 becomes the control voltage of the carrier wave oscillator 99 after the noise component is removed by the LF 18b.
[0093]
As described above, according to the first embodiment, first, the carrier frequency is synchronized using the first error signal ERR1 that can generate an error signal in a wide frequency range, and Δf becomes sufficiently small. Since the carrier frequency is synchronized by switching to the second error signal ERR2 later, it is possible to establish the synchronization of the carrier frequency if Δf is in the range of −2 / Ts to 2 / Ts. As a result, the synchronization range of the carrier frequency is -2 / Ts to 2 / Ts, which is four times that of the conventional example, and the carrier frequency can be synchronized even if a large carrier frequency offset Δf exists.
[0094]
Further, the subcarrier frequency interval 1 / Ts is 4 kHz, the RF (Radio Frequency) frequency is 1.9 GHz, and the accuracy of the oscillator is ± 1 ppm (= ± 1 × 10 ×).^-6), The maximum value of Δf is Δf_max= ± 3.8 kHz. In this case, since the conventional method can only deal with frequency offsets up to ± 2 kHz, carrier frequency synchronization cannot be achieved. However, according to the first embodiment, frequency offsets up to four times ± 8 kHz can be handled. Even when such a large carrier frequency offset Δf exists, the carrier frequency can be synchronized.
[0095]
Embodiment 2. FIG.
In the first embodiment described above, the case where the pilot symbol is a signal that does not change in time (unmodulated signal) has been described. However, the present invention is not limited to this, and the second embodiment described below. As described above, the present invention is also applicable when the pilot symbol is a signal (modulation signal) that changes with time.
[0096]
First, the configuration will be described. FIG. 5 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to the second embodiment of the present invention. In FIG. 5, reference numeral 2 denotes an OFDM demodulator according to the second embodiment. This OFDM demodulator 2 has the same overall configuration as that of the OFDM demodulator 1 according to the first embodiment described above. The OFDM demodulator 1 is changed from the carrier frequency synchronization circuit 10 to the carrier frequency synchronization circuit 20. It is different in the replaced part. Therefore, in this OFDM demodulator 2, the same number is attached | subjected to the structure similar to OFDM demodulator 1, and the description is abbreviate | omitted.
[0097]
The carrier frequency synchronization circuit 20 is different from the above-described carrier frequency synchronization circuit 10 in that a circuit for canceling temporal changes of pilot symbols is added. That is, the carrier frequency synchronization circuit 20 is provided with phase rotation circuits 21, 22a, and 22b, respectively, before the delay detection circuit 11 and the pilot symbol level detection circuits 13a and 13b. These phase rotation circuits 21, 22a, 22b are all input signals (demodulation output C_m, C_m-1, C_{m + 1}) To give a rotation opposite to the phase rotation of the pilot symbol to cancel the temporal change of the pilot symbol.
[0098]
The carrier frequency synchronization circuit 10 described above is applicable when the pilot symbol is a signal that does not change in time (non-modulated signal), and thus is applied as it is when the signal is not an unmodulated signal, that is, a modulated signal. Can not. This is because when the pilot symbol is not an unmodulated signal but changes over time, the phase of the delay detection circuit output signal shown in FIG. 3A does not become a fixed value, as shown in FIG. This is because the average result becomes 0 and the outputs of the pilot symbol level detection circuits 13a and 13b become 0.
[0099]
Therefore, in the second embodiment, carrier frequency synchronization can be achieved with respect to the case where the pilot symbol is not an unmodulated signal. When the pilot symbol is not an unmodulated signal, the pilot symbol is a signal whose phase changes in accordance with a predetermined known data sequence. Therefore, since the receiving side (OFDM demodulator 2) knows in advance how the phase of the received symbol changes in accordance with this data series, each input of the delay detection circuit 11 and the pilot symbol level detection circuits 13a and 13b. In the stage, the phase rotation circuits 21, 22a, 22b remove known phase changes of the received symbols.
[0100]
That is, the phase rotation circuits 21, 22a, 22b give the input signal a rotation opposite to the phase rotation of the pilot symbol and output it. As a result, the output signals of the phase rotation circuits 21, 22a, and 22b are the same as those in the case where the pilot symbols are unmodulated with respect to the pilot symbol components.
[0101]
On the other hand, since there is no correlation between pilot symbols and symbols other than pilot symbols, components other than pilot symbols are signals that undergo random phase changes. As described above, since the phase rotation circuits 21, 22a and 22b are provided at the input stages of the delay detection circuit 11 and the pilot symbol level detection circuits 13a and 13b, they are included in the output signals of the phase rotation circuits 21, 22a and 22b. Pilot symbols are unmodulated. Since the operations of the delay detection circuit 11, the pilot symbol level detection circuits 13a and 13b, and the subsequent circuits are the same as those in the first embodiment, description thereof is omitted.
[0102]
As described above, according to the second embodiment, the first error signal ERR1 output from the subtractor 17 and the second error output from the phase detection circuit 12 even when the pilot symbol is not unmodulated. The signal ERR2 is the same as that in the first embodiment. Therefore, even when the pilot symbols are not unmodulated, the carrier frequency synchronization range is changed from −2 / Ts to 2 / Ts as in Embodiment 1 described above, and therefore there is a large carrier frequency offset Δf. However, it is possible to synchronize the carrier frequency.
[0103]
Embodiment 3 FIG.
In Embodiment 1 described above, the first error is determined by using the levels of pilot signals received at a subcarrier frequency that is one step higher and a subcarrier frequency that is one step lower than the subcarrier frequency used by a known pilot symbol. Although the signal ERR is obtained, the present invention is not limited to this, and the range of subcarrier frequencies around the subcarrier frequency used by a known pilot symbol is expanded as in the third embodiment described below. The carrier frequency offset Δf larger than that of the first embodiment may be dealt with.
[0104]
First, the configuration will be described. FIG. 6 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to the third embodiment of the present invention. In FIG. 6, reference numeral 3 denotes an OFDM demodulator according to the third embodiment. The OFDM demodulator 3 employs the same configuration as that of the OFDM demodulator 1 according to the first embodiment described above. The OFDM demodulator 1 is changed from the carrier frequency synchronization circuit 10 to the carrier frequency synchronization circuit 30. It is different in the replaced part. Therefore, in this OFDM demodulator 3, the same number is attached | subjected to the structure similar to the OFDM demodulator 1, and the description is abbreviate | omitted.
[0105]
The carrier frequency synchronization circuit 30 has a configuration for synchronizing the carrier frequency when the pilot symbol is unmodulated and the carrier frequency offset Δf is too large to be synchronized with the configuration of the first embodiment. That is, the carrier frequency synchronization circuit 30 uses the signal level of the pilot signal transmitted at a subcarrier frequency that is two distances away from the subcarrier frequency for transmitting the pilot symbol in order to generate the first error signal ERR1. That is, the carrier frequency synchronization circuit 30 is connected in parallel (demodulated signal C from the FFT processor 97).₀~ C_N-1) Are connected to the subcarrier frequency at which the pilot symbol is transmitted, and the outputs at the subcarrier frequencies around the subcarrier frequency (upper and lower two).
[0106]
The carrier frequency synchronization circuit 30 adds a pilot symbol level detection circuit 13c and a pilot symbol level detection circuit 13d connected to the FFT processor 97 as new configurations. Pilot symbol level detection circuit 13c has subcarrier m-2, which is two smaller in number than subcarrier m on which pilot symbols are transmitted, that is, a frequency twice the subcarrier interval than the subcarrier frequency on which pilot symbols are transmitted. Demodulated output C on subcarriers as low as_m-2Enter C_m-2The level of the pilot signal included in is detected and the detection result is output.
[0107]
Also, the pilot symbol level detection circuit 13d has a subcarrier m + 2 that is two numbers higher than the subcarrier m in which the pilot symbol is transmitted, that is, the frequency is twice the subcarrier interval than the subcarrier frequency in which the pilot symbol is transmitted. Demodulated output C at subcarriers higher by_{m + 2}Enter C_{m + 2}The level of the pilot signal included in is detected and the detection result is output. Since pilot symbol level detection circuits 13c and 13d have the same configuration as pilot symbol level detection circuits 13a and 13b described above, description of the configuration is omitted.
[0108]
The carrier frequency synchronization circuit 30 further includes an adder 31a that sums signal levels of pilot signals received at subcarrier frequencies lower than the subcarrier frequency at which pilot symbols are received, and a subcarrier on which pilot symbols are transmitted. And an adder 31b for adding the signal levels of pilot signals transmitted at a subcarrier frequency higher than the frequency.
[0109]
Adder 31a is connected to pilot symbol level detection circuits 13a and 13c, and adder 31b is connected to pilot symbol level detection circuits 13b and 13d. These adders 31a and 31b have their outputs connected to the subtractor 17. Accordingly, the subtracter 17 sub-frequency below the subcarrier frequency at which the pilot symbol is transmitted from the total signal level of the pilot signal received at the subcarrier frequency above the subcarrier frequency at which the pilot symbol is received. The first error signal ERR1 is obtained by subtracting the total signal level of the pilot signal transmitted in step (1).
[0110]
Next, main operations will be described. FIG. 7 is a diagram for explaining the error signal. FIG. 7A shows changes in the pilot symbol level detection circuits 13a and 13b due to the carrier frequency offset Δf, and FIG. 7B shows the first error due to the carrier frequency offset Δf. The change of the signal ERR1 is shown. As shown in FIG. 7A, the output of the pilot symbol detection circuit 13a is a signal waveform 601a that becomes maximum when ΔfTs = −1 and decreases as ΔfTs goes away from −1.
[0111]
Further, as shown in FIG. 7A, the output of the pilot symbol detection circuit 13b is a waveform 601b of a signal that becomes maximum when ΔfTs = 1 and decreases as ΔfTs goes away from 1. These waveforms 601a and 601b are the same as the waveforms 301a and 301b already described in FIG.
[0112]
The signal input to the newly provided pilot symbol detection circuit 13c is a demodulated symbol C corresponding to a frequency lower by a subcarrier frequency interval than the signal input to the pilot symbol detection circuit 27a._m-2Therefore, the peak of ΔfTs becomes a waveform 601c shifted to a frequency lower by the subcarrier frequency interval.
[0113]
That is, the waveform 601c has a peak at ΔfTs = −2, as shown in FIG. Similarly, the signal input to pilot symbol detection circuit 13d is demodulated symbol C corresponding to a frequency higher by a subcarrier frequency interval than the signal input to pilot symbol detection circuit 27b._{m + 2}Therefore, the peak of ΔfTs becomes a waveform 601d that shifts to a higher frequency by the subcarrier frequency interval. That is, the waveform 601d has a peak at ΔfTs = 2 as shown in FIG.
[0114]
As a result, in the subtracter 17, the output signal of the adder 31a is subtracted from the output signal of the adder 31b, and the signal (waveform 602) of FIG. 7B is obtained as an error signal.
[0115]
As described above, according to the third embodiment, in the error signal for carrier frequency synchronization, the carrier frequency offset Δf is obtained in the range of −3 / Ts to 3 / Ts. However, the carrier frequency can be synchronized even if there is a carrier frequency offset Δf that is too large to be synchronized in the conventional example or the first embodiment described above.
[0116]
Embodiment 4 FIG.
In the third embodiment described above, the case where the pilot symbol is a signal (non-modulated signal) that does not change with time has been described. However, the present invention is not limited to this, and the fourth embodiment described below. As described above, the present invention is also applicable when the pilot symbol is a signal (modulation signal) that changes with time.
[0117]
First, the configuration will be described. FIG. 8 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to the fourth embodiment of the present invention. In FIG. 8, reference numeral 4 denotes an OFDM demodulator according to the fourth embodiment. This OFDM demodulator 4 has the same overall configuration as that of the OFDM demodulator 3 according to the third embodiment described above. The OFDM demodulator 3 is changed from the carrier frequency synchronization circuit 30 to the carrier frequency synchronization circuit 40. It is different in the replaced part. Therefore, in this OFDM demodulator 4, the same number is attached | subjected to the structure similar to OFDM demodulator 3, and the description is abbreviate | omitted.
[0118]
The carrier frequency synchronization circuit 40 is different from the above-described carrier frequency synchronization circuit 30 in that a circuit for canceling temporal changes of pilot symbols is added. That is, the carrier frequency synchronization circuit 40 is provided with phase rotation circuits 21, 22a, 22b, 22c, and 22d, respectively, before the delay detection circuit 11 and the pilot symbol level detection circuits 13a, 13b, 13c, and 13d. These phase rotation circuits 21, 22a, 22b, 22c and 22d all have input signals (demodulation output C)._m, C_m-1, C_{m + 1}, C_m-2, C_{m + 2}) To give a rotation opposite to the phase rotation of the pilot symbol to cancel the temporal change of the pilot symbol.
[0119]
The carrier frequency synchronization circuit 30 described above can be applied when the pilot symbol is a signal that does not change in time (non-modulated signal), and is therefore applied as it is when the signal is not an unmodulated signal, that is, a modulated signal. Can not. This is because when the pilot symbol is not an unmodulated signal but changes over time, the phase of the delay detection circuit output signal shown in FIG. 3A does not become a fixed value, as shown in FIG. This is because the average result becomes 0 and the outputs of the pilot symbol level detection circuits 13a and 13b become 0.
[0120]
Therefore, in the fourth embodiment, carrier frequency synchronization can be achieved with respect to the case where the pilot symbol is not an unmodulated signal. When the pilot symbol is not an unmodulated signal, the pilot symbol is a signal whose phase changes in accordance with a predetermined known data sequence.
[0121]
Therefore, since the receiving side (OFDM demodulator 4) knows in advance how the phase of the received symbol changes according to this data series, the delay detection circuit 11, the pilot symbol level detection circuits 13a, 13b, 13c, At each input stage 13d, phase rotation circuits 21, 22a, 22b, 22c, 22d remove known phase changes in the received symbols.
[0122]
That is, the phase rotation circuits 21, 22a, 22b, 22c, and 22d give the input signal a rotation opposite to the phase rotation of the pilot symbol and output it. As a result, the output signals of the phase rotation circuits 21, 22a, 22b, 22c, and 22d are the same as those when the pilot symbols are not modulated with respect to the pilot symbol components.
[0123]
On the other hand, since there is no correlation between pilot symbols and symbols other than pilot symbols, components other than pilot symbols are signals that undergo random phase changes. Thus, since the phase rotation circuits 21, 22a, 22b, 22c, and 22d are provided at the input stages of the delay detection circuit 11 and the pilot symbol level detection circuits 13a, 13b, 13c, and 13d, the phase rotation circuits 21 and 22a are provided. , 22b, 22c and 22d are unmodulated pilot symbols. The operations of the delay detection circuit 11 and the pilot symbol level detection circuits 13a, 13b, 13c, 13d and subsequent circuits are the same as those in the third embodiment described above, and a description thereof will be omitted.
[0124]
As described above, according to the fourth embodiment, as in the case of the second embodiment, the phase change of the pilot symbol is removed by the phase rotation circuit. As shown in FIG. 7B, an error signal is obtained, and the synchronization range of the carrier frequency is six times that of the conventional example. As a result, it is possible to synchronize the carrier frequency even when there is a large Δf that cannot be synchronized in the conventional example or the already described second embodiment.
[0125]
Embodiment 5 FIG.
In the first to fourth embodiments described above, the correction control circuit 19 is incorporated in order to determine the control voltage of the carrier wave oscillator 99 as one of the LFs 18a and 18b. Is not mentioned. Therefore, a configuration example will be described with reference to the fifth embodiment.
[0126]
Since the carrier frequency synchronization circuit of the fifth embodiment may apply any of the configurations of the first to fourth embodiments described above, the circuit configuration around the correction control circuit 19 is not shown. FIG. 9 shows a configuration example of the correction control circuit according to the fifth embodiment. The correction control circuit includes a switch 51, a memory 52, and a switching control circuit 53, as shown in FIG.
[0127]
Switch 51 switches its output to either LF 18a or LF 18b in accordance with switching signal SEL output from switching control circuit 53. The memory 52 holds in advance time data that defines a certain time during which the first error signal ERR1 is used. This fixed time represents the time required for the frequency offset to be sufficiently reduced by the first error signal ERR1. The switching control circuit 53 refers to the time data stored in the memory 52 in advance, and after the establishment of synchronization (at the time of initial operation), the switching signal SEL is sent to the switch 51 according to the elapse of a fixed time indicated by the time data. Output.
[0128]
Next, the operation will be described. In the correction control circuit shown in FIG. 9, the switch 51 is set to the LF 18a side during the initial operation of carrier frequency synchronization. During the initial operation, the switching control circuit 53 confirms the passage of a predetermined time held in the memory 52 in advance. After the fixed time has elapsed, the switching control circuit 53 outputs a switching signal SEL for switching to the LF 18b side. As a result, the output of the switch 51 is switched from the first error signal ERR1 of the LF 18a to the second error signal ERR2 of the LF 18b.
[0129]
As described above, according to the fifth embodiment, the switching timing of the error signal used for the correction of the control voltage is set using the data stored in the memory 52, so that the control using the first error signal ERR1 is performed. It is possible to correct the control voltage with the second error signal ERR2 after the frequency offset becomes sufficiently small due to the voltage correction. Further, it is possible to switch the switch 51 with a simple configuration without giving an external switching timing.
[0130]
Further, since the use correction amount is switched at the timing when the offset amount of the carrier wave frequency becomes smaller than a certain amount by the switch 51, it is possible to give an appropriate correction according to the situation of the carrier wave frequency offset. Thereby, it is possible to smoothly establish synchronization of the carrier frequency.
[0131]
In addition, since the switch 51 is switched at a certain time after the start of synchronization establishment, the synchronization operation of the carrier frequency can always be realized at a constant timing when the synchronization is established.
[0132]
Embodiment 6 FIG.
In the first to fourth embodiments described above, the correction control circuit 19 is incorporated in order to determine the control voltage of the carrier wave oscillator 99 as one of the LFs 18a and 18b. Is not mentioned. Therefore, a configuration example will be described with reference to a sixth embodiment that employs a method different from the fifth embodiment.
[0133]
Since the carrier frequency synchronization circuit of the sixth embodiment may apply any of the configurations of the first to fourth embodiments described above, the circuit configuration around the correction control circuit 19 is not shown. FIG. 10 shows a configuration example of the correction control circuit according to the sixth embodiment. This correction control circuit includes a switch 61 and a counter circuit 62 as shown in FIG.
[0134]
The switch 61 switches its output to either one of the LF 18a and the LF 18b in accordance with the switching signal SEL output from the counter circuit 62. The counter circuit 62 holds in advance a value for counting a certain time during which the first error signal ERR1 is used. This value represents the time required for the frequency offset to be sufficiently reduced by the first error signal ERR1.
[0135]
Next, the operation will be described. In the correction control circuit shown in FIG. 10, the switch 61 is set on the LF 18a side during the initial operation of carrier frequency synchronization. During the initial operation, the counter circuit 62 counts up or down a preset value. When the counting operation is completed, a switching signal SEL for switching to the LF 18b side is output from the counter circuit 62 to the switch 61. As a result, the output of the switch 61 is switched from the first error signal ERR1 of the LF 18a to the second error signal ERR2 of the LF 18b.
[0136]
As described above, according to the sixth embodiment, the same effect as in the fifth embodiment described above can be obtained, and even if the counter circuit 62 is used, as in the fifth embodiment described above, It is possible to correct the control voltage using the second error signal ERR2 after the frequency offset is sufficiently reduced by correcting the control voltage using the first error signal ERR1.
[0137]
Embodiment 7 FIG.
In the first to sixth embodiments described above, a configuration is provided in which the switching timing of the error signal for correcting the control voltage is held in advance. However, the present invention is not limited to this, and is described below. As in the seventh embodiment, the switching timing may be obtained based on the received pilot signal.
[0138]
First, the configuration will be described. FIG. 11 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to the seventh embodiment of the present invention. In FIG. 11, reference numeral 7 denotes an OFDM demodulator according to the seventh embodiment. This OFDM demodulator 7 has the same overall configuration as that of the OFDM demodulator 1 according to the first embodiment described above. The OFDM demodulator 1 is changed from the carrier frequency synchronization circuit 10 to the carrier frequency synchronization circuit 70. It is different in the replaced part. Therefore, in this OFDM demodulator 7, the same number is attached | subjected to the structure similar to the OFDM demodulator 1, and the description is abbreviate | omitted.
[0139]
The carrier frequency synchronization circuit 10 described above is provided with a correction control circuit for switching the error signal. However, the carrier frequency synchronization circuit 70 has a pilot symbol level detection circuit 13e, A determination circuit 71 and a switch 72 are provided. The pilot symbol level detection circuit 13e has a demodulated output C in subcarrier m on which pilot symbols are transmitted._mEnter C_mThe level of the pilot signal included in is detected and the detection result is output. This pilot symbol level detection circuit 13e is provided with an FFT processor 97 (demodulation output C_m).
[0140]
Determination circuit 71 is connected to pilot symbol level detection circuits 13a, 13b and 13e, obtains the switching timing of switch 72 based on each signal level, and outputs switching signal SEL to switch 72 at the switching timing. Switch 72 switches its output from LF 18a to 18b in response to switching signal SEL output from determination circuit 71.
[0141]
Next, main operations will be described. In the carrier frequency synchronization circuit 70 shown in FIG. 11, when the carrier frequency synchronization is established using the first error signal ERR1, the carrier frequency offset Δf approaches 0 as described above.
[0142]
As a result, as apparent from FIG. 4A, the output signals of the pilot symbol level detection circuits 13a and 13b become small. Conversely, the output signal of pilot symbol level detection circuit 13e increases. Therefore, by observing the outputs of these three pilot symbol level detection circuits 13a, 13b, and 13e, it is determined whether or not the carrier frequency synchronization state, that is, the carrier frequency offset Δf is close to zero.
[0143]
The determination circuit 71 generates a switching signal SEL to the switch 72 at a timing when the output of the pilot symbol detection circuit 13e becomes larger than the output of the pilot symbol level detection circuits 13a and 13b by a predetermined value or more. When the switch signal SEL is input to the switch 72, the output is switched from the first error signal ERR1 to the second error signal ERR2.
[0144]
As described above, according to the seventh embodiment, since the determination circuit 71 automatically performs the switching operation from the first error signal ERR1 to the second error signal ERR2, the above-described fifth and sixth embodiments. Thus, there is an advantage that it is not necessary to prepare the switching timing in advance, and the manufacturing process of the apparatus is simplified.
[0145]
As mentioned above, although this invention was demonstrated by Embodiment 1-7, a various deformation | transformation is possible within the range of the main point of this invention, and these are not excluded from the scope of this invention.
[0146]
【The invention's effect】
As described above, according to the present invention, the correction amount of the carrier frequency obtained based on the signal level of the reference signal for synchronization establishment received at frequencies around the frequency used by the signal for establishment of synchronization. The carrier frequency correction control is performed according to the carrier frequency correction amount, and then the carrier frequency correction control is performed according to the carrier frequency correction amount obtained based on the phase change amount of the signal serving as a reference for establishing synchronization. A correct correction amount can be obtained for the frequency offset, and the synchronization is established after the carrier frequency offset is reduced to some extent by performing correction according to this correction amount, so that even if a large carrier frequency offset exists. There is an effect that a carrier frequency synchronization circuit capable of reliably establishing synchronization of carrier frequencies can be obtained.
[0147]
According to the next invention, when the signal serving as a reference for establishing synchronization is generated as an unmodulated signal so as not to have a phase change on the transmission side, the phase of the carrier signal does not change with time. In order to establish synchronization, a configuration for obtaining a correction amount by taking a difference in signal level of a reference signal detected at frequencies one above and below a frequency used by the reference signal, and a phase of the reference signal It is sufficient to prepare a configuration for obtaining the amount of change as a correction amount. With such a configuration, even if the signal used as a reference for establishing synchronization does not have a phase change on the transmission side, it can be used for an initial large carrier frequency offset. The correct amount of correction can be obtained, and synchronization is established after the carrier frequency offset is reduced to some extent by correcting according to this correction amount. Therefore, there is a large carrier frequency offset. Ensure an effect that the carrier frequency synchronization circuit capable of establishing the synchronization of the carrier frequency is obtained.
[0148]
According to the next invention, when the signal serving as a reference for establishing synchronization is generated as a modulation signal so as to have a phase change on the transmission side, the phase of the carrier signal changes with time. For this purpose, firstly, a configuration in which a correction amount is obtained by calculating a difference between signal levels of a reference signal detected at frequencies one above and below a frequency used by the reference signal after canceling the phase change, It is sufficient to prepare a configuration in which the phase change amount of the reference signal is calculated as a correction amount after canceling the change. With such a configuration, even if the reference signal for establishing synchronization has a phase change on the transmission side, A correct correction amount can be obtained even for a large carrier frequency offset, and synchronization is established after the carrier frequency offset is reduced to some extent by correcting according to this correction amount. Because an effect that the carrier frequency synchronization circuit capable of establishing synchronization of the large carrier frequency reliably carrier frequency be offset exists is obtained.
[0149]
According to the next invention, when the signal serving as a reference for establishing synchronization is generated as an unmodulated signal so as not to have a phase change on the transmission side, the phase of the carrier signal does not change with time. In order to establish synchronization, a correction amount is obtained by taking the difference in signal level of the reference signal detected at a plurality of peripheral frequencies larger than the frequency used by the reference signal and at a plurality of smaller peripheral frequencies. It is only necessary to prepare a configuration and a configuration for obtaining a phase change amount of a reference signal as a correction amount. With such a configuration, even if a signal serving as a reference for establishing synchronization does not have a phase change on the transmission side, A correction amount can be obtained for a wider range of carrier frequency offsets than when a correction amount is obtained from a carrier signal received at one frequency above and below the frequency used by the reference signal. Since Tsu bets synchronization establishment is performed after decreased to a certain extent, an effect that a larger carrier frequency synchronizing circuit capable of carrier frequency offset to establish synchronization reliably carrier frequency be present is obtained.
[0150]
According to the next invention, when the signal serving as a reference for establishing synchronization is generated as a modulation signal so as to have a phase change on the transmission side, the phase of the carrier signal changes with time. Therefore, first, the phase change is canceled, and then the amount of correction is calculated by taking the difference in signal level for each of the carrier signals received at a plurality of peripheral frequencies larger and smaller than the frequency used by the reference signal. And a configuration in which the phase change amount of the reference signal is first calculated as a correction amount after canceling the phase change. Even if there is a phase change, the carrier frequency frequency is wider than when the correction amount is obtained from the carrier signal received at one frequency above and below the frequency used by the reference signal. Since the amount of correction is obtained for the set, and synchronization is established after the carrier frequency offset becomes small to some extent, the carrier can reliably establish synchronization of the carrier frequency even if a larger carrier frequency offset exists. There is an effect that a frequency synchronization circuit can be obtained.
[0151]
According to the next invention, since the use correction amount is switched at the timing when the offset amount of the carrier frequency becomes smaller than a certain amount by the switch, an appropriate correction is given according to the situation of the carrier frequency offset. As a result, the carrier frequency synchronization circuit capable of smoothly establishing the synchronization of the carrier frequency can be obtained.
[0152]
According to the next invention, the switching timing of the switch is achieved after a lapse of a certain time after the start of synchronization establishment. Therefore, when synchronization is established, the carrier frequency synchronization operation can always be realized at a constant timing. There is an effect that a possible carrier frequency synchronization circuit can be obtained.
[0153]
According to the next invention, a predetermined time is stored in the memory, and the switching control circuit controls the switching of the switch with reference to the predetermined time, so that it is easy even without giving the switching timing from the outside. An advantageous effect is obtained in that a carrier frequency synchronization circuit capable of switching the switch with a simple configuration can be obtained.
[0154]
According to the next invention, the switch switching timing is obtained by counting a predetermined time set in advance by the count circuit, so that the switch can be switched with a simple configuration without giving the switching timing from the outside. An effect is obtained that a carrier frequency synchronization circuit capable of performing the above is obtained.
[0155]
According to the next invention, the use correction is performed at the timing when the signal level of the reference signal becomes higher than the reference signal level detected at at least two frequencies adjacent to the frequency used by the reference signal. Since the amount is switched, there is no need to prepare a switching timing in advance, and there is an effect that a carrier frequency synchronization circuit capable of simplifying the manufacturing process of the device can be obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to a first embodiment of the present invention.
FIG. 2 is a diagram illustrating a format example of a transmission frame used in the OFDM scheme.
FIG. 3 is a diagram for explaining delay circuit output in the first embodiment. FIG. 3 (a) shows outputs of delay detection circuits 14a and 14b for unmodulated pilot symbol components, and FIG. 3 (b) shows pilot symbols. The outputs of the delay detection circuits 14a and 14b with respect to other signal components are shown.
4A and 4B are diagrams for explaining an error signal in the first embodiment. FIG. 4A shows a change in detected pilot symbol level due to a carrier frequency offset Δf, and FIG. 4B shows a carrier frequency offset Δf. The change of the 1st error signal ERR1 by is shown.
FIG. 5 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to a second embodiment of the present invention.
FIG. 6 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to a third embodiment of the present invention.
7A and 7B are diagrams for explaining an error signal in the third embodiment. FIG. 7A shows a change in detected pilot symbol level due to a carrier frequency offset Δf, and FIG. 7B shows a carrier frequency offset Δf. The change of the 1st error signal ERR1 by is shown.
FIG. 8 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to a fourth embodiment of the present invention.
FIG. 9 is a block diagram showing a configuration example of a main part of a carrier frequency synchronization circuit according to a fifth embodiment of the present invention.
FIG. 10 is a block diagram showing a configuration example of a main part of a carrier frequency synchronization circuit according to a sixth embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration example of a carrier frequency synchronization circuit according to a seventh embodiment of the present invention.
FIG. 12 is a general configuration diagram showing a relationship between an OFDM modulator and an OFDM demodulator according to a conventional example.
13A and 13B are diagrams for explaining transmission symbols. FIG. 13A shows a format of transmission symbols before serial-parallel conversion, and FIG. 13B shows a format of transmission symbols after serial-parallel conversion. .
FIG. 14 is a diagram illustrating a spectrum of a transmission IF signal output from an OFDM modulator.
FIG. 15 is a block diagram showing a carrier frequency synchronization circuit according to a conventional example.
FIG. 16 is a diagram showing an in-phase component of a transmission baseband signal waveform.
FIG. 17 is a diagram illustrating a relationship between a delay of a received baseband signal and a correlation value.
[Explanation of symbols]
1, 2, 3, 4, 5, 6, 7 OFDM demodulator 10, 20, 30, 40, 70 Carrier frequency synchronization circuit, 11 Delay detection circuit, 12 Phase detection circuit, 13a, 13b, 13c, 13d Pilot symbol Level detection circuit, 14a, 14b Delay detection circuit, 15a, 15b Average circuit, 16a, 16b Envelope detection circuit, 17 Subtractor, 18a, 18b LF, 19 Correction control circuit, 21, 22a, 22b, 22c, 22d Phase rotation Circuit, 31a, 31b adder, 51, 61, 72 switch, 52 memory, 53 switching control circuit, 62 counter circuit, 71 determination circuit.

Claims (10)

On the transmitting side, a plurality of signals including a reference signal for establishing carrier frequency synchronization are orthogonally frequency-division multiplexed to generate a carrier signal, and on the receiving side, the transmitting side is used to establish carrier frequency synchronization. In the carrier frequency synchronization circuit applied to the system that corrects the carrier frequency according to the state of the reference signal in the carrier signal generated in Step 1, and used on the receiving side of the system,
First generating means for obtaining a carrier frequency correction amount based on a signal level of the reference signal received at a frequency around a frequency used by the reference signal;
Second generating means for obtaining a correction amount of the carrier frequency based on the phase change amount of the reference signal;
Control means for performing correction control of the carrier frequency in the order of the correction amount obtained by the first generation means and the correction amount obtained by the second generation means;
With
Further, a signal serving as the reference, the signals generated as a non-modulated signal to have no phase change at the transmitting side,
The first generating means includes
A pair of delay detection circuits that respectively delay detect the carrier signals received at one frequency above and below the frequency used by the reference signal;
A pair of averaging circuits for averaging the signals delayed detected by the pair of delay detection circuits, respectively;
A pair of envelope detection circuits for detecting signal levels based on the envelopes of the signals averaged by the pair of averaging circuits, respectively;
An arithmetic circuit that obtains the correction amount by taking the difference between the signal levels respectively detected by the pair of envelope detection circuits;
Including
The second generating means includes
A delay detection circuit for delay detection of the reference signal;
A phase detection circuit for detecting the phase change amount of the signal delayed detected by the delay detection circuit and obtaining the correction amount;
Carrier wave frequency synchronization circuit characterized by containing. On the transmitting side, a plurality of signals including a reference signal for establishing carrier frequency synchronization are orthogonally frequency-division multiplexed to generate a carrier signal, and on the receiving side, the transmitting side is used to establish carrier frequency synchronization. In the carrier frequency synchronization circuit applied to the system that corrects the carrier frequency according to the state of the reference signal in the carrier signal generated in Step 1, and used on the receiving side of the system,
First generating means for obtaining a carrier frequency correction amount based on a signal level of the reference signal received at a frequency around a frequency used by the reference signal;
Second generating means for obtaining a correction amount of the carrier frequency based on the phase change amount of the reference signal;
Control means for performing correction control of the carrier frequency in the order of the correction amount obtained by the first generation means and the correction amount obtained by the second generation means;
With
Further, a signal serving as the reference, the generated signal as a modulated signal to have a phase change in the transmitting side,
The first generating means includes
A pair of first phase rotation circuit for removing the phase change of the carrier signal signal serving as the reference is received in the upper and lower one at the frequency of the frequency used,
A pair of delay detection circuits that respectively delay detect the carrier signals from which phase changes have been removed by the pair of first phase rotation circuits;
A pair of averaging circuits for averaging the signals delayed detected by the pair of delay detection circuits, respectively;
A pair of envelope detection circuits for detecting signal levels based on the envelopes of the signals averaged by the pair of averaging circuits, respectively;
An arithmetic circuit that obtains the correction amount by taking the difference between the signal levels respectively detected by the pair of envelope detection circuits;
Including
The second generating means includes
A second phase rotation circuit for removing a phase change of the reference signal;
A delay detection circuit that delay-detects the reference signal from which the phase change has been removed by the second phase rotation circuit;
A phase detection circuit for detecting the phase change amount of the signal delayed detected by the delay detection circuit and obtaining the correction amount;
Carrier wave frequency synchronization circuit characterized by containing. On the transmitting side, a plurality of signals including a reference signal for establishing carrier frequency synchronization are orthogonally frequency-division multiplexed to generate a carrier signal, and on the receiving side, the transmitting side is used to establish carrier frequency synchronization. In the carrier frequency synchronization circuit applied to the system that corrects the carrier frequency according to the state of the reference signal in the carrier signal generated in Step 1, and used on the receiving side of the system,
First generating means for obtaining a carrier frequency correction amount based on a signal level of the reference signal received at a frequency around a frequency used by the reference signal;
Second generating means for obtaining a correction amount of the carrier frequency based on the phase change amount of the reference signal;
Control means for performing correction control of the carrier frequency in the order of the correction amount obtained by the first generation means and the correction amount obtained by the second generation means;
With
Further, a signal serving as the reference, the signals generated as a non-modulated signal to have no phase change at the transmitting side,
The first generating means includes
A plurality of delay detection circuits for delay-detecting the carrier signals respectively received at a plurality of peripheral frequencies larger than a frequency used by the reference signal and a plurality of small peripheral frequencies;
A plurality of averaging circuits for averaging the signals delayed detected by the plurality of delay detection circuits, respectively;
A plurality of envelope detection circuits for detecting a signal level based on the envelope of the signal averaged by each of the plurality of averaging circuits;
Of the signal levels detected by the plurality of envelope detection circuits, the sum of the signal levels detected at a frequency higher than the frequency used by the reference signal and the frequency used by the reference signal An arithmetic circuit that obtains the correction amount by taking a difference from the sum of the signal levels detected at a frequency lower than
Including
The second generating means includes
A delay detection circuit for delay detection of the reference signal;
A phase detection circuit for detecting the phase change amount of the signal delayed detected by the delay detection circuit and obtaining the correction amount;
Carrier wave frequency synchronization circuit characterized by containing. On the transmitting side, a plurality of signals including a reference signal for establishing carrier frequency synchronization are orthogonally frequency-division multiplexed to generate a carrier signal, and on the receiving side, the transmitting side is used to establish carrier frequency synchronization. In the carrier frequency synchronization circuit applied to the system that corrects the carrier frequency according to the state of the reference signal in the carrier signal generated in Step 1, and used on the receiving side of the system,
First generating means for obtaining a carrier frequency correction amount based on a signal level of the reference signal received at a frequency around a frequency used by the reference signal;
Second generating means for obtaining a correction amount of the carrier frequency based on the phase change amount of the reference signal;
Control means for performing correction control of the carrier frequency in the order of the correction amount obtained by the first generation means and the correction amount obtained by the second generation means;
With
Further, a signal serving as the reference, the generated signal as a modulated signal to have a phase change in the transmitting side,
The first generating means includes
A plurality of first phase rotation circuits for removing phase changes of the carrier signal received at a plurality of peripheral frequencies larger than a frequency used by the reference signal and a plurality of small peripheral frequencies;
A plurality of delay detection circuits that respectively delay detect the carrier signals from which phase changes have been removed by the plurality of first phase rotation circuits;
A plurality of averaging circuits for averaging the signals delayed detected by the plurality of delay detection circuits, respectively;
A plurality of envelope detection circuits for detecting a signal level based on the envelope of the signal averaged by each of the plurality of averaging circuits;
Of the signal levels detected by the plurality of envelope detection circuits, the sum of the signal levels detected at a frequency higher than the frequency used by the reference signal and the frequency used by the reference signal An arithmetic circuit that obtains the correction amount by taking a difference from the sum of the signal levels detected at a frequency lower than
Including
The second generating means includes
A second phase rotation circuit for removing a phase change of the reference signal;
A delay detection circuit that delay-detects the reference signal from which the phase change has been removed by the second phase rotation circuit;
A phase detection circuit for detecting the phase change amount of the signal delayed detected by the delay detection circuit and obtaining the correction amount;
Carrier wave frequency synchronization circuit characterized by containing. The control means switches the use correction amount from the correction amount obtained by the first generation means to the correction amount obtained by the second generation means at a timing when the offset amount of the carrier frequency becomes smaller than a certain amount. carrier frequency synchronization circuit according to any one of claims 1-4, characterized in that it. 6. The carrier frequency synchronization circuit according to claim 5 , wherein the timing is supplied to the switch when a predetermined time elapses after the start of synchronization establishment. 7. The carrier frequency according to claim 6 , further comprising: a memory that stores the predetermined time; and a switching control circuit that controls switching of the switch with reference to the predetermined time stored in the memory. Synchronous circuit. 7. The carrier frequency synchronization circuit according to claim 6 , further comprising a count circuit that counts the predetermined time set in advance. The control means includes the reference detected at at least two frequencies adjacent to the frequency used by the reference signal and the signal level of the reference signal received at the frequency used by the reference signal. A switch for switching the use correction amount from the correction amount obtained by the first generation means to the correction amount obtained by the second generation means at a timing when the signal level of the signal becomes greater than a predetermined value. The carrier wave frequency synchronization circuit according to any one of claims 1 to 4 . On the transmitting side, a carrier signal is generated by orthogonal frequency division multiplexing a plurality of signals including a reference signal for establishing synchronization of the carrier frequency, and on the receiving side, the carrier frequency The carrier frequency synchronization applied to the system for correcting the carrier frequency according to the state of the reference signal in the carrier signal generated on the transmission side and used on the reception side of the system to establish the synchronization of the number In the circuit
  First generating means for obtaining a carrier frequency correction amount based on a signal level of the reference signal received at a frequency around a frequency used by the reference signal;
  Second generating means for obtaining a correction amount of the carrier frequency based on the phase change amount of the reference signal;
  Control means for performing correction control of the carrier frequency in the order of the correction amount obtained by the first generation means and the correction amount obtained by the second generation means;
  With
  Further, the control means detects the signal level of the reference signal received at the frequency used by the reference signal at at least two frequencies adjacent to the frequency used by the reference signal. A switch that switches the use correction amount from the correction amount obtained by the first generation means to the correction amount obtained by the second generation means at a timing when the signal level of the reference signal is greater than a predetermined value. A carrier frequency synchronization circuit.

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