JPH11330299A - Bare chip mounting board - Google Patents

Bare chip mounting board

Info

Publication number
JPH11330299A
JPH11330299A JP13002398A JP13002398A JPH11330299A JP H11330299 A JPH11330299 A JP H11330299A JP 13002398 A JP13002398 A JP 13002398A JP 13002398 A JP13002398 A JP 13002398A JP H11330299 A JPH11330299 A JP H11330299A
Authority
JP
Japan
Prior art keywords
mounting board
bare chip
chip mounting
hole
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13002398A
Other languages
Japanese (ja)
Inventor
Masako Maeda
雅子 前田
Yuji Hotta
祐治 堀田
Fuyuki Eriguchi
冬樹 江里口
Fumiteru Asai
文輝 浅井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nitto Denko Corp
Original Assignee
Nitto Denko Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nitto Denko Corp filed Critical Nitto Denko Corp
Priority to JP13002398A priority Critical patent/JPH11330299A/en
Publication of JPH11330299A publication Critical patent/JPH11330299A/en
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a bare chip mounting board which is highly reliable in electrical connection, even when heated. SOLUTION: A bare chip mounting board consists of an IC chip 2 and a mounting board 4, which are electrically connected through an anisotropic conductive film 1. The bare chip mounting board is provided with at least one through-hole 5, which communicates with the external from a region surrounded by a wiring pattern 3 on the mounting board 4. Even if a micro-void exists between the IC chip 2 and the mounting board 4, since the expanded air in the heated condition goes out through the through-hole 5, a high heat resistant connection reliability can be obtained even during high temperature.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、ベアチップ実装基
板に関し、より詳しくは、異方導電性フィルムを介して
ICチップと実装基板とを電気的に接続するベアチップ
実装基板に関する。
The present invention relates to a bare chip mounting board, and more particularly, to a bare chip mounting board for electrically connecting an IC chip and a mounting board via an anisotropic conductive film.

【0002】[0002]

【従来の技術】近年の電子機器の多機能化、小型軽量化
に伴い、半導体分野においては、配線回路のパターンが
高集積化され、多ピン、狭ピッチ化のファインパターン
が採用されるようになってきた。
2. Description of the Related Art With the recent increase in the number of functions and reduction in size and weight of electronic devices, in the field of semiconductors, patterns of wiring circuits have been highly integrated, and fine patterns with a large number of pins and a narrow pitch have been adopted. It has become.

【0003】このような回路のファインパターン化に対
応すべく、基板上に形成された複数の導体パターンとI
C、LSIとの接続に異方導電性フィルムが使用され始
めている。
In order to cope with such a fine circuit pattern, a plurality of conductor patterns formed on a substrate and I
C. Anisotropic conductive films have begun to be used for connection to LSIs.

【0004】異方導電性フィルムとしては、接着性フィ
ルム中に導電性微粒子を分散させた構造のものなどが知
られている。しかし、この構造の異方導電性フィルム
は、分散により導電性微粒子を接着性フィルムに配合し
ているため、狭ピッチの電気的接合に関しては信頼性に
欠けるという問題点があった。
As the anisotropic conductive film, a film having a structure in which conductive fine particles are dispersed in an adhesive film is known. However, the anisotropic conductive film having this structure has a problem in that the conductive fine particles are mixed into the adhesive film by dispersion, so that the reliability of the electrical connection at a narrow pitch is lacking.

【0005】そこで、狭ピッチに対応させるために、特
願平9−117244号では、絶縁性フィルムの厚み方
向を貫通するように導電性材料からなる導通路が設けら
れている異方導電性フィルム及びその製造方法が提案さ
れている。
To cope with the narrow pitch, Japanese Patent Application No. 9-117244 discloses an anisotropic conductive film in which a conductive path made of a conductive material is provided so as to penetrate the insulating film in the thickness direction. And a method for producing the same have been proposed.

【0006】この方法で製造された異方導電性フィルム
を使用してICチップと実装基板とを電気的に接続する
代表的な方法としては、例えば図2に断面図を示すよう
な構造のものが挙げられる。異方導電性フィルム1を介
在させて素子の実装などを行うことで、微小なベアチッ
プ2上の多数の電極と外部の基板4上の配線パターン3
とを接続できる。このようにして、狭ピッチの電気的接
合に関しては信頼性に欠けるという問題点が解決され
た。
A typical method for electrically connecting an IC chip to a mounting board using the anisotropic conductive film manufactured by this method is, for example, one having a structure as shown in a sectional view in FIG. Is mentioned. By mounting the element with the anisotropic conductive film 1 interposed therebetween, a large number of electrodes on the minute bare chip 2 and the wiring pattern 3 on the external substrate 4 are formed.
And can be connected. In this way, the problem that the reliability of the electrical connection at the narrow pitch is lacking has been solved.

【0007】しかし、この方法により作られたベアチッ
プ実装基板は、異方導電性フィルム1と実装基板4との
間にマイクロボイドが存在し、環境試験における加熱時
にボイド内の空気の膨張により、接続の信頼性が低下す
る。従って、加熱時においても電気的接続の信頼性の高
いベアチップ実装基板を開発する必要があった。
However, the bare chip mounting substrate manufactured by this method has microvoids between the anisotropic conductive film 1 and the mounting substrate 4, and is connected by expansion of air in the voids during heating in an environmental test. The reliability of the device decreases. Therefore, it is necessary to develop a bare chip mounting board with high electrical connection reliability even during heating.

【0008】[0008]

【発明が解決しようとする課題】本発明の目的は、上記
問題を解決し、加熱時においても電気的接続の信頼性の
高いベアチップ実装基板を提供することにある。
SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems and to provide a bare chip mounting substrate having high reliability of electrical connection even during heating.

【0009】[0009]

【課題を解決するための手段】本発明者らは、上記の課
題を解決すべく鋭意検討した結果、実装基板上の配線パ
ターンで取り囲まれている部分から外部へ通ずる少なく
とも1の貫通孔を設けることで、加熱時においても電気
的接続の信頼性が高いことが判明した。即ち、本発明は
以下のとおりである。 異方導電性フィルムを介して電気的に接続されたI
Cチップと実装基板とからなるベアチップ実装基板であ
って、実装基板上の配線パターンで取り囲まれている部
分から外部へ通ずる少なくとも1の貫通孔が設けられて
いることを特徴とするベアチップ実装基板。 前記貫通孔が、基板の厚み方向を貫通する貫通孔で
あるに記載のベアチップ実装基板。 前記異方導電性フィルムは、絶縁材料からなるフィ
ルム基板中に、導電性材料からなる少なくとも1の導通
路が、互いに絶縁された状態で、かつ該フィルム基板を
厚み方向に貫通した状態で配置され、各導通路は、当該
フィルム基板の表裏面に両端部が露出しているまたは
に記載のベアチップ実装基板。
Means for Solving the Problems As a result of intensive studies to solve the above problems, the present inventors have provided at least one through hole communicating from a portion surrounded by a wiring pattern on a mounting board to the outside. This proved that the reliability of the electrical connection was high even during heating. That is, the present invention is as follows. I electrically connected through an anisotropic conductive film
What is claimed is: 1. A bare chip mounting board comprising a C chip and a mounting board, wherein at least one through hole is provided to communicate from a portion surrounded by a wiring pattern on the mounting board to the outside. 3. The bare chip mounting board according to claim 1, wherein the through-hole is a through-hole passing through the thickness direction of the board. The anisotropic conductive film is disposed in a film substrate made of an insulating material in a state where at least one conductive path made of a conductive material is insulated from each other and penetrates the film substrate in a thickness direction. The bare chip mounting substrate according to or, wherein each of the conduction paths has both ends exposed on the front and back surfaces of the film substrate.

【0010】[0010]

【作用】本発明は、上記手段を講じたので、加熱時にマ
イクロボイド内で空気が膨張しても、実装基板上の配線
パターンで取り囲まれている部分から外部に通ずる少な
くとも1の貫通孔を有しており、この貫通孔を通じて膨
張した空気が外部へ抜けるので、電気的接続の信頼性を
高く維持できる。
According to the present invention, at least one through-hole is provided which leads from the portion surrounded by the wiring pattern on the mounting board to the outside even if air expands in the microvoid during heating. Since the air expanded through the through holes escapes to the outside, the reliability of the electrical connection can be maintained high.

【0011】[0011]

【発明の実施の形態】以下、本発明を詳細に説明する。
図1は、本発明によるベアチップ実装基板の一例を示す
模式図である。図1に示す態様では、異方導電性フィル
ム1により、ICチップ2と配線パターン3を有する実
装基板4とが電気的に接続されている。実装基板4は、
加温により、マイクロボイド内で膨張した空気が抜け出
るための孔5を有している。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail.
FIG. 1 is a schematic diagram showing an example of a bare chip mounting board according to the present invention. In the embodiment shown in FIG. 1, the IC chip 2 and the mounting substrate 4 having the wiring pattern 3 are electrically connected by the anisotropic conductive film 1. The mounting board 4
There is a hole 5 through which air expanded in the microvoid is released by heating.

【0012】なお、この明細書において、ベアチップと
は、パッケージ化されていないベア(裸)のICチップ
のことをいう。
In this specification, a bare chip refers to a bare (naked) IC chip that is not packaged.

【0013】本発明で使用される異方導電性フィルム1
としては、異方導電性を有すれば種類は特に限定され
ず、接着性フィルム中に導電性微粒子を分散させた構造
のものや、絶縁性フィルムの厚み方向を貫通するよう導
電性材料からなる導通路を設けた構造のものなどが挙げ
られる。好ましい異方導電性フィルム1は、絶縁性フィ
ルムの厚み方向を貫通するよう導電性材料からなる導通
路を設けた構造のものである。このような異方導電性フ
ィルムを使用すると、狭ピッチの電気的接続に関しては
信頼性に富む。
Anisotropic conductive film 1 used in the present invention
The type is not particularly limited as long as it has anisotropic conductivity, and has a structure in which conductive fine particles are dispersed in an adhesive film, or is made of a conductive material so as to penetrate in the thickness direction of the insulating film. One having a structure provided with a conduction path is exemplified. The preferred anisotropic conductive film 1 has a structure in which a conductive path made of a conductive material is provided so as to penetrate in the thickness direction of the insulating film. When such an anisotropic conductive film is used, the electrical connection at a narrow pitch is highly reliable.

【0014】本発明のベアチップ実装基板に使用される
異方導電性フィルム基板を構成する絶縁性接着材料とし
ては、異方導電性フィルムのフィルム基板として使用で
きる材料が挙げられ、公知のものを使用すればよい。本
発明のベアチップ実装基板に使用される異方導電性フィ
ルム1は、プリント基板とICチップの接着に使用され
るため、接着性を有する材料を使用する必要がある。ま
た、異方導電性を発揮するため、絶縁性接着材料は、十
分な絶縁特性を有している必要もある。接着性を有する
材料としては、熱硬化性樹脂、熱可塑性樹脂などの公知
の接着性材料が挙げられる。具体的には、フェノール
系、ビフェニル系などのエポキシ樹脂、アクリル樹脂、
ポリカルボジイミド樹脂、ポリウレタン樹脂等の熱硬化
性樹脂や、フェノキシ樹脂、ナイロン6やナイロン6,
6などのポリアミド樹脂、PET系やPBT系などの飽
和ポリエステル樹脂、ポリアミドイミド樹脂等のポリイ
ミド樹脂、フッ素樹脂、ポリエーテルイミド樹脂等の熱
可塑性樹脂が挙げられ、目的に応じて適宜選択される。
これらの樹脂は単独でも、2種以上混合して使用しても
よい。好ましくはガラス転移点が150℃以上230℃
以下の接着性材料である。ガラス転移点が150℃以上
であれば半導体素子と回路基板の接着信頼性をより高め
ることができ、ガラス転移点が230℃以下であれば作
業性に優れるからである。
Examples of the insulating adhesive material constituting the anisotropic conductive film substrate used for the bare chip mounting substrate of the present invention include materials that can be used as the film substrate of the anisotropic conductive film, and known materials are used. do it. Since the anisotropic conductive film 1 used for the bare chip mounting board of the present invention is used for bonding the printed board and the IC chip, it is necessary to use an adhesive material. Further, in order to exhibit anisotropic conductivity, the insulating adhesive material needs to have sufficient insulating properties. Examples of the material having adhesiveness include known adhesive materials such as thermosetting resins and thermoplastic resins. Specifically, phenol-based, biphenyl-based epoxy resin, acrylic resin,
Thermosetting resins such as polycarbodiimide resin and polyurethane resin, phenoxy resin, nylon 6, nylon 6,
And polyamide resins such as PET and PBT, polyimide resins such as polyamideimide resins, and thermoplastic resins such as fluororesins and polyetherimide resins, which are appropriately selected according to the purpose.
These resins may be used alone or in combination of two or more. Glass transition point is preferably 150 ° C. or higher and 230 ° C.
The following adhesive materials are used. If the glass transition point is 150 ° C. or higher, the bonding reliability between the semiconductor element and the circuit board can be further improved. If the glass transition point is 230 ° C. or lower, workability is excellent.

【0015】異方導電性フィルム1の形状は、ICチッ
プ2と実装基板4との間で電気的接続ができれば形状は
特に制限されず、ICチップ2と同じ形状でなくてもよ
い。例えば、中央部分がカットされている形状であって
もよい。
The shape of the anisotropic conductive film 1 is not particularly limited as long as electrical connection can be made between the IC chip 2 and the mounting board 4, and may not be the same shape as the IC chip 2. For example, a shape in which a central portion is cut may be used.

【0016】導通路は、少なくともフィルムの厚み方向
に貫通し、当該フィルム基板の表裏面に両端部が露出さ
れるように設ける。導通路の材料としては、導電性を有
するものであれば特に限定されず、例えば銅、金、アル
ミニウム、ニッケルなどの金属材料、これらの金属材料
とポリイミド樹脂、エポキシ樹脂、アクリル樹脂、フッ
素樹脂などの高分子材料との混合物、ポリアセンなどの
導電性高分子材料などが使用できる。導電性材料は、用
途により適宜選択されるが、電気的特性の点で金属材料
が好ましく、特に導電性の点で銅、金が好ましい。
The conductive path is provided so as to penetrate at least in the thickness direction of the film and to expose both ends on the front and back surfaces of the film substrate. The material of the conduction path is not particularly limited as long as it has conductivity, and examples thereof include metal materials such as copper, gold, aluminum, and nickel, and these metal materials and polyimide resin, epoxy resin, acrylic resin, and fluorine resin. , A conductive polymer material such as polyacene, and the like. The conductive material is appropriately selected depending on the application, but a metal material is preferable in terms of electrical characteristics, and copper and gold are particularly preferable in terms of conductivity.

【0017】絶縁性フィルムの厚み方向を貫通するよう
導電性材料からなる導通路を設けた構造の異方導電性フ
ィルムの製造方法は、特に制限されないが、例えば、接
着性フィルムに貫通孔を設け、鍍金により金属孔内に充
填する方法や金属細線に絶縁材料を用いて被覆層を形成
し、これを芯材にロール状に巻いたのち、加熱および/
あるいは加圧により、被覆層同士を互いに融着および/
または圧着させ、さらにロール状物の軸方向に刃物をい
れる方法などが挙げられる。
The method of manufacturing an anisotropic conductive film having a structure in which a conductive path made of a conductive material is provided so as to penetrate in the thickness direction of the insulating film is not particularly limited. For example, a through hole is formed in an adhesive film. A method of filling a metal hole by plating or forming a coating layer on a thin metal wire using an insulating material, winding this in a core material in a roll shape, heating and / or
Alternatively, the coating layers are fused together and / or
Alternatively, there is a method in which a blade is inserted in the axial direction of the roll-shaped material by pressing and pressing.

【0018】本発明で使用される実装基板4は、種類は
特に制限されず、例えば、ガラスエポキシ基板、セラミ
ック基板、ポリイミド樹脂などで構成されるフレキシブ
ル基板などが使用できる。
The type of the mounting substrate 4 used in the present invention is not particularly limited, and for example, a glass epoxy substrate, a ceramic substrate, a flexible substrate made of a polyimide resin or the like can be used.

【0019】実装基板4には、配線パターン3がプリン
ト等されている。配線パターン3は、銅などの導体で形
成されている。配線パターン3は、一般に、図1の正面
図に示されるようにICチップ2の搭載部分6の外縁を
取り囲むように形成される。
The wiring pattern 3 is printed on the mounting board 4. The wiring pattern 3 is formed of a conductor such as copper. The wiring pattern 3 is generally formed so as to surround the outer edge of the mounting portion 6 of the IC chip 2 as shown in the front view of FIG.

【0020】本発明で実装基板4上の配線パターン3で
取り囲まれている部分に設けられる貫通孔5としては、
マイクロボイド内で膨張した空気が抜けるものであれ
ば、配線パターン3の幅方向を貫通するもの、基板4の
厚み方向を貫通するもの、基板4の厚み方向の中途から
幅方向へ通じて基板4のいずれかの端部へ達するもの、
配線パターン3を潜通して実装基板4の上面に達するも
のなどいずれであってもよい。好ましい貫通孔として
は、作製の容易さから基板の厚み方向を貫通する貫通孔
である。
In the present invention, the through-hole 5 provided in the portion of the mounting substrate 4 surrounded by the wiring pattern 3 includes:
If the air that has expanded in the microvoids escapes, the air that passes through the wiring pattern 3 in the width direction, the air that passes through the thickness direction of the substrate 4, Reaching either end of the
Any of those that penetrate the wiring pattern 3 and reach the upper surface of the mounting substrate 4 may be used. A preferable through hole is a through hole penetrating in the thickness direction of the substrate for ease of production.

【0021】貫通孔は、配線パターン3を避けて設ける
のが好ましく、さらに配線パターン3より1mm以上離
れた場所に設けるのが好ましい。配線パターン3や配線
パターン3より1mm未満に貫通孔を設けると、配線の
欠損や腐食を生ずるおそれがあるからである。
The through-hole is preferably provided so as to avoid the wiring pattern 3, and is further preferably provided at a position separated from the wiring pattern 3 by 1 mm or more. This is because, if the wiring pattern 3 or the through hole is provided less than 1 mm from the wiring pattern 3, the wiring may be damaged or corroded.

【0022】貫通孔を設ける方法としては、特に制限さ
れるものではなく、公知の方法、例えば、パンチングや
ドリルなどの機械的加工法、レーザー、プラズマなどの
ドライエッチング法などが挙げられる。特に、基板に貫
通孔を設ける場合は、コストの面から、パンチングやド
リルなどの機械的加工法を用いることが好ましい。貫通
孔の形状も特に制限されるものではなく、円形、四角形
や菱形などの多角形などいずれの形状でもよい。
The method of providing the through-hole is not particularly limited, and may be a known method, for example, a mechanical processing method such as punching or drilling, a dry etching method using laser, plasma or the like. In particular, when a through hole is provided in the substrate, it is preferable to use a mechanical processing method such as punching or drilling from the viewpoint of cost. The shape of the through-hole is not particularly limited, and may be any shape such as a circle, a polygon such as a square or a rhombus.

【0023】貫通孔の直径(孔径)は、開口部の孔径で
通常50〜1000μm程度、好ましくは100〜30
0μm程度である。貫通孔の直径が50μmより小さい
場合は、ベアチップと実装基板との間のマイクロボイド
内で膨張した空気が抜けきらないおそれがあり、貫通孔
の直径が1000μmより大きい場合は、貫通孔から水
分や異物が侵入するおそれがあり、好ましくない。
The diameter of the through hole (hole diameter) is usually about 50 to 1000 μm, preferably 100 to 30 μm, in terms of the diameter of the opening.
It is about 0 μm. If the diameter of the through-hole is smaller than 50 μm, there is a possibility that the air expanded in the microvoid between the bare chip and the mounting board may not be able to escape.If the diameter of the through-hole is larger than 1000 μm, moisture or There is a possibility that foreign matter may enter, which is not preferable.

【0024】貫通孔の数は、ICチップの大きさ等に応
じて1以上設ければよく、基板4や配線パターン3の強
度を考慮して適宜決定できる。
The number of through holes may be one or more depending on the size of the IC chip and the like, and can be appropriately determined in consideration of the strength of the substrate 4 and the wiring pattern 3.

【0025】[0025]

【実施例】以下本発明を実施例に基づいて具体的に説明
するが、本発明はこれらの実施例に限定されるものでは
ない。
EXAMPLES The present invention will be specifically described below based on examples, but the present invention is not limited to these examples.

【0026】実施例1 ガラスエポキシ基板(FR−4)に、100μmピッチ
で銅線(金メッキ)の配線パターンが形成され、ICチ
ップ搭載部分の中央に直径200μmの貫通孔が1個設
けられた実装基板に、ICチップを異方導電性フィルム
を用いてベアチップ実装した。ICチップは、10mm
×10mmサイズのものを使用した。異方導電性フィル
ムは、イミド系の絶縁フィルム(ポリカルボジイミド樹
脂)に、導電層に導電材料として銅を使用し、銅の最表
面に金(Au)層が設けられているもので、大きさがI
Cチップと同じ10mm×10mmサイズで、厚さが7
0μmのものを使用した。ICチップと実装基板との接
続は、フリップチップボンダーを使用して、設定温度2
70℃、圧力30kg/cm、60秒で行った。得られ
たベアチップ実装基板は、パターン接続確率が100%
で、接続抵抗値20mΩ以下の良好な接続状態を示し
た。このベアチップ実装基板をプレッシャークッカーテ
スト(以下「PCT」という)(121℃、100%R
H、2atm)雰囲気中に100時間放置し、接続信頼
性評価を行った結果、パターン接続確率100%で、接
続抵抗値20mΩ以下の初期の良好な接続状態を保持し
ていた。
Example 1 A mounting in which a wiring pattern of copper wires (gold plating) is formed at a pitch of 100 μm on a glass epoxy substrate (FR-4), and one through hole having a diameter of 200 μm is provided at the center of the IC chip mounting portion. An IC chip was mounted on a substrate using a bare chip using an anisotropic conductive film. IC chip is 10mm
A size of × 10 mm was used. The anisotropic conductive film is an imide-based insulating film (polycarbodiimide resin) in which copper is used as a conductive material for a conductive layer, and a gold (Au) layer is provided on the outermost surface of copper. Is I
The same 10mm × 10mm size as the C chip and the thickness is 7
The thing of 0 μm was used. The connection between the IC chip and the mounting board is performed using a flip chip bonder at a set temperature of 2
The test was performed at 70 ° C. under a pressure of 30 kg / cm for 60 seconds. The obtained bare chip mounting board has a pattern connection probability of 100%.
Showed a good connection state with a connection resistance value of 20 mΩ or less. This bare chip mounting board was subjected to a pressure cooker test (hereinafter referred to as “PCT”) (121 ° C., 100% R
(H, 2 atm). After standing for 100 hours in an atmosphere, the connection reliability was evaluated. As a result, an initial good connection state having a connection resistance value of 20 mΩ or less was maintained at a pattern connection probability of 100%.

【0027】実施例2 異方導電性フィルムとして、大きさが10mm×10m
mサイズで、フィルムの中心部分に3mm×3mmの開
口を設けたロの字型のものを用いた以外は、実施例1と
同様の方法でベアチップ実装基板を得た。得られたベア
チップ実装基板は、パターン接続確率が100%で、接
続抵抗値20mΩ以下の良好な接続状態を示した。この
ベアチップ実装基板をPCT(121℃、100%R
H、2atm)雰囲気中に100時間放置し、接続信頼
性評価を行った結果、パターン接続確率100%で、接
続抵抗値20mΩ以下の初期の良好な接続状態を保持し
ていた。
Example 2 An anisotropic conductive film having a size of 10 mm × 10 m
A bare chip mounting board was obtained in the same manner as in Example 1 except that a square-shaped one having an m size and having a 3 mm × 3 mm opening in the center of the film was used. The obtained bare chip mounting board had a pattern connection probability of 100% and exhibited a good connection state with a connection resistance value of 20 mΩ or less. This bare chip mounting board is mounted on a PCT (121 ° C, 100% R
(H, 2 atm). After standing for 100 hours in an atmosphere, the connection reliability was evaluated. As a result, an initial good connection state having a connection resistance value of 20 mΩ or less was maintained at a pattern connection probability of 100%.

【0028】実施例3 ガラスエポキシ基板(FR−4)に、350μmピッチ
で銅線(金メッキ)の配線パターンが形成され、ICチ
ップ搭載部分の中央に直径300μmの貫通孔が1個設
けられた実装基板に、ICチップを異方導電性フィルム
を用いてベアチップ実装した。ICチップは、10mm
×10mmサイズのものを使用した。異方導電性フィル
ムは、エポキシ樹脂系の材料(ビスフェノール系エポキ
シ樹脂)に、金属粒子(ニッケル粒子、平均粒径5μ
m)を分散させたもので、大きさがICチップと同じ1
0mm×10mmサイズで、厚さが150μmのものを
使用した。ICチップと実装基板との接続は、フリップ
チップボンダーを使用して、設定温度200℃、圧力3
0kg/cm、60秒で行った。得られたベアチップ実
装基板は、パターン接続確率が100%で、接続抵抗値
20mΩ以下の良好な接続状態を示した。このベアチッ
プ実装基板をPCT(121℃、100%RH、2at
m)雰囲気中に72時間放置し、接続信頼性評価を行っ
た結果、パターン接続確率100%で、接続抵抗値20
mΩ以下の初期の良好な接続状態を保持していた。
Example 3 A mounting in which a wiring pattern of copper wires (gold plating) is formed at a pitch of 350 μm on a glass epoxy substrate (FR-4), and one through hole having a diameter of 300 μm is provided at the center of the IC chip mounting portion. An IC chip was mounted on a substrate using a bare chip using an anisotropic conductive film. IC chip is 10mm
A size of × 10 mm was used. The anisotropic conductive film is formed by adding metal particles (nickel particles, average particle diameter 5μ) to an epoxy resin material (bisphenol epoxy resin).
m) is dispersed, and the size is the same as the IC chip.
One having a size of 0 mm × 10 mm and a thickness of 150 μm was used. The connection between the IC chip and the mounting board is performed using a flip chip bonder at a set temperature of 200 ° C and a pressure of 3
The test was performed at 0 kg / cm for 60 seconds. The obtained bare chip mounting board had a pattern connection probability of 100% and exhibited a good connection state with a connection resistance value of 20 mΩ or less. This bare chip mounting board is mounted on a PCT (121 ° C., 100% RH, 2 at
m) After standing for 72 hours in an atmosphere and evaluating the connection reliability, the connection resistance value was 20 with a pattern connection probability of 100%.
The initial good connection state of mΩ or less was maintained.

【0029】比較例1 ガラスエポキシ樹脂基板のIC搭載部分に貫通孔を設け
ない以外は、実施例1と同様の方法でベアチップ実装基
板を得た。得られたベアチップ実装基板は、パターン接
続確率が100%で、接続抵抗値20mΩ以下の良好な
接続状態を示した。このベアチップ実装基板をPCT
(121℃、100%RH、2atm)雰囲気中に10
0時間放置し、接続信頼性評価を行った結果、パターン
接続確率95%で、接続抵抗値20mΩ以下の値を示
し、5%の接続不良が発生していた。
Comparative Example 1 A bare chip mounting board was obtained in the same manner as in Example 1 except that no through-hole was provided in the IC mounting portion of the glass epoxy resin substrate. The obtained bare chip mounting board had a pattern connection probability of 100% and exhibited a good connection state with a connection resistance value of 20 mΩ or less. This bare chip mounting board is PCT
(121 ° C., 100% RH, 2 atm)
It was left for 0 hours, and the connection reliability was evaluated. As a result, the connection resistance value was 20 mΩ or less with a pattern connection probability of 95%, and a connection failure of 5% occurred.

【0030】比較例2 ガラスエポキシ樹脂基板のIC搭載部分に貫通孔を設け
ない以外は、実施例2と同様の方法でベアチップ実装基
板を得た。得られたベアチップ実装基板は、パターン接
続確率が100%で、接続抵抗値20mΩ以下の良好な
接続状態を示した。このベアチップ実装基板をPCT
(121℃、100%RH、2atm)雰囲気中に10
0時間放置し、接続信頼性評価を行った結果、パターン
接続確率90%で、接続抵抗値20mΩ以下の値を示
し、10%の接続不良が発生していた。
Comparative Example 2 A bare chip mounting substrate was obtained in the same manner as in Example 2 except that no through-hole was formed in the IC mounting portion of the glass epoxy resin substrate. The obtained bare chip mounting board had a pattern connection probability of 100% and exhibited a good connection state with a connection resistance value of 20 mΩ or less. This bare chip mounting board is PCT
(121 ° C., 100% RH, 2 atm)
It was left for 0 hours, and the connection reliability was evaluated. As a result, the connection resistance value was 20 mΩ or less at a pattern connection probability of 90%, and a connection failure of 10% occurred.

【0031】比較例3 ガラスエポキシ樹脂基板のIC搭載部分に貫通孔を設け
ない以外は、実施例3と同様の方法でベアチップ実装基
板を得た。得られたベアチップ実装基板は、パターン接
続確率が100%で、接続抵抗値20mΩ以下の良好な
接続状態を示した。このベアチップ実装基板をPCT
(121℃、100%RH、2atm)雰囲気中に72
時間放置し、接続信頼性評価を行った結果、パターン接
続確率95%で、接続抵抗値20mΩ以下の値を示し、
5%の接続不良が発生していた。
Comparative Example 3 A bare chip mounting substrate was obtained in the same manner as in Example 3 except that no through-hole was formed in the IC mounting portion of the glass epoxy resin substrate. The obtained bare chip mounting board had a pattern connection probability of 100% and exhibited a good connection state with a connection resistance value of 20 mΩ or less. This bare chip mounting board is PCT
(121 ° C., 100% RH, 2 atm)
After leaving it for a time and evaluating the connection reliability, the connection resistance value was 20 mΩ or less with a pattern connection probability of 95%.
5% connection failure occurred.

【0032】実施例では、接続信頼性は良好であった
が、比較例では、いずれも接続不良が発生した。
In the example, the connection reliability was good, but in the comparative examples, connection failure occurred in all cases.

【0033】[0033]

【発明の効果】本発明のベアチップ実装基板は、実装基
板上の配線パターンで取り囲まれている部分から外部へ
通ずる少なくとも1の貫通孔を設けているので、ICチ
ップと実装基板との間にマイクロボイドが存在しても、
加熱状態で膨張した空気が貫通孔から外部に抜けること
ができるので、高温時においても高い耐熱接続信頼性を
得ることができる。
According to the bare chip mounting board of the present invention, at least one through-hole is provided which extends from the portion surrounded by the wiring pattern on the mounting board to the outside, so that the micro chip is provided between the IC chip and the mounting board. Even if voids exist,
Since the air expanded in the heated state can escape to the outside from the through-hole, high heat-resistant connection reliability can be obtained even at a high temperature.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明によるベアチップ実装基板の一例を示す
模式図である。
FIG. 1 is a schematic view showing an example of a bare chip mounting board according to the present invention.

【図2】従来のベアチップ実装基板の一例の断面を示す
模式図である。
FIG. 2 is a schematic view showing a cross section of an example of a conventional bare chip mounting board.

【符号の説明】[Explanation of symbols]

1 異方導電性フィルム 2 ICチップ 3 配線パターン 4 実装基板 5 貫通孔 6 ICチップ搭載部分 DESCRIPTION OF SYMBOLS 1 Anisotropic conductive film 2 IC chip 3 Wiring pattern 4 Mounting board 5 Through hole 6 IC chip mounting part

───────────────────────────────────────────────────── フロントページの続き (72)発明者 浅井 文輝 大阪府茨木市下穂積1丁目1番2号 日東 電工株式会社内 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Fumiki Asai 1-2-1, Shimohozumi, Ibaraki-shi, Osaka Nitto Denko Corporation

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 異方導電性フィルムを介して電気的に接
続されたICチップと実装基板とからなるベアチップ実
装基板であって、実装基板上の配線パターンで取り囲ま
れている部分から外部へ通ずる少なくとも1の貫通孔が
設けられていることを特徴とするベアチップ実装基板。
1. A bare chip mounting board comprising an IC chip and a mounting board which are electrically connected via an anisotropic conductive film, wherein the bare chip mounting board communicates with a portion surrounded by a wiring pattern on the mounting board to the outside. A bare chip mounting board, wherein at least one through hole is provided.
【請求項2】 前記貫通孔が、基板の厚み方向を貫通す
る貫通孔である請求項1に記載のベアチップ実装基板。
2. The bare chip mounting board according to claim 1, wherein said through hole is a through hole penetrating in a thickness direction of said board.
【請求項3】 前記異方導電性フィルムは、絶縁材料か
らなるフィルム基板中に、導電性材料からなる少なくと
も1の導通路が、互いに絶縁された状態で、かつ該フィ
ルム基板を厚み方向に貫通した状態で配置され、各導通
路は、当該フィルム基板の表裏面に両端部が露出してい
る請求項1または2に記載のベアチップ実装基板。
3. The anisotropic conductive film has a structure in which at least one conductive path made of a conductive material is insulated from each other in a film substrate made of an insulating material and penetrates the film substrate in a thickness direction. The bare chip mounting board according to claim 1, wherein both end portions of each conductive path are exposed on the front and back surfaces of the film substrate.
JP13002398A 1998-05-13 1998-05-13 Bare chip mounting board Pending JPH11330299A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13002398A JPH11330299A (en) 1998-05-13 1998-05-13 Bare chip mounting board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13002398A JPH11330299A (en) 1998-05-13 1998-05-13 Bare chip mounting board

Publications (1)

Publication Number Publication Date
JPH11330299A true JPH11330299A (en) 1999-11-30

Family

ID=15024260

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13002398A Pending JPH11330299A (en) 1998-05-13 1998-05-13 Bare chip mounting board

Country Status (1)

Country Link
JP (1) JPH11330299A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002237547A (en) * 2001-02-09 2002-08-23 Hitachi Chem Co Ltd Substrate for semiconductor package and manufacturing method, and semiconductor package and manufacturing method
JP2002279830A (en) * 2001-03-19 2002-09-27 Nitto Denko Corp Anisotropic conductive film
US6815830B2 (en) 2000-03-10 2004-11-09 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
CN116344460A (en) * 2023-03-28 2023-06-27 上海韬润半导体有限公司 Packaging and sheet-loading film, manufacturing method and application

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6815830B2 (en) 2000-03-10 2004-11-09 Seiko Epson Corporation Semiconductor device and method of manufacturing the same, circuit board and electronic instrument
JP2002237547A (en) * 2001-02-09 2002-08-23 Hitachi Chem Co Ltd Substrate for semiconductor package and manufacturing method, and semiconductor package and manufacturing method
JP4696368B2 (en) * 2001-02-09 2011-06-08 日立化成工業株式会社 Semiconductor package substrate and manufacturing method thereof, and semiconductor package and manufacturing method thereof
JP2002279830A (en) * 2001-03-19 2002-09-27 Nitto Denko Corp Anisotropic conductive film
JP4522604B2 (en) * 2001-03-19 2010-08-11 日東電工株式会社 Anisotropic conductive film
CN116344460A (en) * 2023-03-28 2023-06-27 上海韬润半导体有限公司 Packaging and sheet-loading film, manufacturing method and application
CN116344460B (en) * 2023-03-28 2023-09-01 上海韬润半导体有限公司 Packaging and sheet-loading film, manufacturing method and application

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