JPH11317779A - Reception signal absolute phase setting device of receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the circuit scale small. SOLUTION: When multi-PSK modulated waves of BPSK, QPSK, 8PSK begin to be received, a selector 16A of a demodulating circuit 1A reads the high-order three bits Δϕ(3) of phase error data corresponding to a Q-symbol stream out of one phase error table 15-1 for BPSK among tables provided by modulation systems and phase rotational angles. A reception signal phase rotational angle detecting circuit 8A detects the phase rotational angles of the parts corresponding to the bits (1) and (0) of the frame synchronizing signal of the reception symbol stream and outputs them to a remapper 7 to perform an absolute phase setting process. The selector 16A reads phase error data corresponding to the reception symbol stream out of the phase error table corresponding to the modulation system and phase rotational angle discriminated by a transmission constitution discriminating circuit 9 and output sit to a D/A converter 17 to correct the phase of a reference carrier for orthogonal detection, thereby placing the reception signal point in fixed phase with a transmit signal point.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for absolutely phase-shifting a received signal of a receiver, and more particularly, to a hierarchical transmission system and the like.
Receives a PSK modulated signal in which a BPSK-modulated frame synchronization signal, an 8PSK-modulated digital signal, a QPSK-modulated digital signal, and at least one of the BPSK-modulated digital signals are time-multiplexed. The present invention relates to a reception signal absolute phase shifter for a receiver that matches the signal point arrangement of reception signals of two series of I and Q baseband signals obtained by demodulation with a transmission side.

[0002]

2. Description of the Related Art A plurality of modulation schemes requiring different C / N, such as 8PSK modulated wave, QPSK modulated wave, BP
A digital satellite T based on a hierarchical transmission system in which SK modulated waves are time-multiplexed and repeatedly transmitted for each frame.
Practical use of V broadcasting is in progress.

FIG. 11A is an explanatory diagram showing an example of a frame configuration in the hierarchical transmission system. One frame is BP
A SK-modulated frame synchronization signal pattern consisting of 32 symbols (the latter 20 symbols are actually used as the frame synchronization signal in 32 symbols), and a TPSK-modulated T symbol for identifying a transmission multiplex configuration consisting of 128 symbols.
MCC (Transmission and Multiplexing Configuration)
n Control) pattern, a superframe identification signal pattern consisting of 32 symbols (the latter 20 symbols are actually used as a superframe identification signal in 32 symbols), 8PSK (trellis codec 8PSK) modulated main signal of 203 symbols, A 4-symbol burst symbol signal (BS) in which a pseudo-random noise (PN) signal is BPSK-modulated, a 203-symbol main signal in which 8PSK (trellis codec 8PSK) is modulated, and a 4-symbol in which a pseudo-random noise (PN) signal is BPSK-modulated Symbol burst symbol signal (BS),..., QPS
A K-modulated 203-symbol main signal, a 4-symbol burst symbol signal (BS) in which a pseudo-random noise (PN) signal is BPSK-modulated, and a QPSK-modulated 203
The symbol is composed of a main signal and a BPSK-modulated burst symbol signal (BS) of four symbols.

[0004] In a receiver for receiving a digital modulated wave (PSK modulated wave) by the hierarchical transmission system, an intermediate frequency signal of a received signal received by a receiving circuit is demodulated by a demodulating circuit, and I signals having orthogonal relations to each other. Two series of I and Q baseband signals (hereinafter, I and Q baseband signals are also referred to as I and Q symbol stream data) representing instantaneous values for each symbol on the axis and the Q axis are obtained. The frame synchronization signal is captured from the demodulated I and Q baseband signals, the current received signal phase rotation angle is obtained from the signal point arrangement of the captured frame synchronization signal, and demodulated based on the obtained received signal phase rotation angle. By rotating the I and Q base band signals in opposite phases, an absolute phase conversion circuit that performs absolute phase matching to the transmission signal phase angle is performed.

[0005] An absolute phase shift circuit of a receiver for receiving a PSK modulated wave by the conventional hierarchical transmission method is provided on the output side of the demodulation circuit 1 to capture a frame synchronization signal, as shown in FIG. It comprises a frame synchronization detecting / reproducing circuit 2 as a synchronizing signal capturing means, a remapper 7 as an anti-phase rotating means comprising a ROM, and a received signal phase rotation angle detecting circuit 8 as a received signal phase rotating angle detecting means. Reference numeral 9 denotes a transmission configuration identification circuit for identifying the transmission multiplex configuration shown in FIG. 11A, and outputs a 2-bit modulation scheme identification signal DM.

The demodulation circuit 1 performs quadrature detection on the intermediate frequency signal to obtain I and Q baseband signals. 10 of the demodulation circuits 1
Is synchronized in frequency and phase with the received carrier, and has a phase of 9
Two reference carriers f _C1 (= co
s ωt) and carrier recovery circuit for recovering f _C2 (= sin ωt), 60 and 61 are multipliers for multiplying the intermediate frequency signal IF by f _C1 and f _C2 , and 62 and 63 are the outputs of multipliers 60 and 61 A / D converters that perform A / D conversion at a sampling rate that is twice the symbol rate, and 64 and 65 are A / D converters 62 and 6
Digital filters for limiting the band of the output of the digital filter 3 by digital signal processing.
4 and 65 are thinned out to 1/2 sampling rate, and two series of I and Q baseband signals (I and Q symbol stream data) representing instantaneous values for each symbol on the I and Q axes are output. The decimation circuits 66 and 67 have I and Q baseband signals I (8) and Q (8) of 8 bits (two's complement system) (the numbers in parentheses indicate the number of quantization bits. (They are also simply referred to as I and Q with the number of coded bits omitted).

[0007] Here, mapping for each modulation scheme on the transmitting side will be described with reference to FIG. FIG.
(1) shows a signal point arrangement on an IQ phase plane (also referred to as an IQ vector plane or an IQ signal space diagram) when 8PSK is used as a modulation scheme. In the 8PSK modulation method, a 3-bit digital signal (abc) can be transmitted by one symbol, and the combination of bits constituting one symbol is (000), (001), (010), (01).
1), (100), (101), (110), (11)
There are 8 types of 1). These three-bit digital signals are converted into signal point arrangements “0” to “7” on the transmission-side IQ phase plane in FIG. 13A, and this conversion is called 8PSK mapping.

In the example shown in FIG. 13A, the bit string (00
0) to the signal point arrangement "0", the bit string (001) to the signal point arrangement "1", the bit string (011) to the signal point arrangement "2", and the bit string (010) to the signal point arrangement "3".
The bit string (100) is assigned to the signal point arrangement “4”, the bit string (101) is assigned to the signal point arrangement “5”, and the bit string (111) is assigned.
Is converted into a signal point arrangement "6", and the bit string (110) is converted into a signal point arrangement "7".

FIG. 13B shows a signal point arrangement on an IQ phase plane when QPSK is used as a modulation method.
In the modulation method, a 2-bit digital signal (de) can be transmitted by one symbol, and there are four combinations of bits constituting the symbol: (00), (01), (10), and (11). In the example of FIG. 13B, for example, the bit string (00) is set to the signal point arrangement “1”, the bit string (01) is set to the signal point arrangement “3”, the bit string (11) is set to the signal point arrangement “5”, and the bit string ( 10) is converted to a signal point arrangement “7”.

FIG. 13C shows a signal point arrangement in the case where BPSK is used as a modulation method. In the BPSK modulation method, a 1-bit digital signal (f) is transmitted by one symbol.
In the digital signal (f), for example, bit (0) is converted into a signal point arrangement "0" and bit (1) is converted into a signal point arrangement "4". The relationship between the signal point arrangement and the arrangement number of each modulation scheme is the same as the relation between the signal point arrangement and the arrangement number based on 8 BPSK. QPS in hierarchical transmission system
The I axis and Q axis of K and BPSK coincide with the I axis and Q axis of 8PSK.

If the phase of the received carrier wave and the phases of the reference carrier waves f _C1 and f _C2 reproduced by the carrier wave reproduction circuit 10 match, the signal point arrangement “0” to “0” on the IQ phase plane on the transmission side is obtained.
When the digital signal corresponding to “7” is received, the phase of the received signal point on the IQ phase plane by the I and Q baseband signals I (8) and Q (8) on the receiving side matches the transmitting side. I do. Therefore, the received digital signal can be correctly identified from the signal point arrangement of the received signal points, using the correspondence between the signal point arrangement and the digital signal on the transmitting side (see FIG. 13) as it is.

However, actually, the reference carriers f _C1 , f _C2
Can be in various phase states with respect to the received carrier, so that the received signal point on the receiving side has a phase position rotated by a certain angle θ with respect to the transmitting side. Then, if the phase of the received carrier changes, θ also changes. If the phase of the received signal point rotates randomly with respect to the transmitting side, the received digital signal cannot be identified. For example, when θ = π / 8, the transmission side 8P
The digital signal (000) having the signal point arrangement "0" in the SK modulation method is received at the signal point arrangement "0" because the reception signal point is located at the center between the signal point arrangements "0" and "1" on the receiving side. If it is assumed that the digital signal (000) has been received correctly, it is mistaken that the digital signal (001) has been received if it is assumed that the digital signal (001) has been received in the signal point arrangement "1". Therefore, the carrier recovery circuit 10 controls the reference carrier f so that the reception signal point keeps a certain rotation angle with respect to the transmission side.
The phases of _C1 and _fC2 are corrected so that digital signals can be correctly identified.

More specifically, the VCO of the carrier recovery circuit 10
Create a reference carrier f _C1 by oscillating the (voltage controlled oscillator) 11 in the transmission carrier frequency, also creates a reference carrier f _C2 a phase advance 90 ° to the oscillation signal at 90 ° phase shifter 12 of the VCO 11. Then, by varying the control voltage of the VCO 11, the phases of the reference carrier waves f _C1 and f _C2 can be varied. The carrier recovery circuit 10 has 8PS
Various data sets of I and Q baseband signals I (8) and Q (8) for each modulation scheme of K, QPSK and BPSK;
Carrier phase error data (hereinafter also simply referred to as phase error data) of 8 bits (two's complement system) of quantization bits Δφ
The phase error tables 13, 14-1 and 14-2, and 1 to 2 corresponding to (8) are stored in a ROM.
5-1 to 15-4 are provided (see FIG. 14). Each phase error table 13, 14-1 and 14-2, 15-1 to 1
5-4, I and Q baseband signals I (8), Q (8)
Are input in parallel. The phase error table selectively enabled by a selector described later includes I and Q baseband signals I (8) and Q (8) input from the demodulation circuit 1.
Is output as the phase error data Δφ (8).

The phase error table 13 is for 8PSK. The phase on the IQ phase plane of the received signal points indicated by the I and Q baseband signals I (8) and Q (8) input from the demodulation circuit 1 is shown. Angle φ (see FIG. 15) and phase error data Δφ
The relationship with (8) is configured as shown in FIG. The selector 16 receives the I and Q baseband signals I from the demodulation circuit 1.
(8) While the demodulation circuit 1 is demodulating the 8PSK modulation digital modulated wave in accordance with the clock CLK _SYB (see FIG. 11 (2)) having the symbol rate synchronized with the output of Q (8) (described later). (Specified by the modulation scheme identification signal DM from the transmission configuration identification circuit 9), only the phase error table 13 is enabled (active), and the demodulation circuit 1 outputs I and Q baseband signals I (8) for one symbol.
Every time Q (8) is output, phase error data Δφ (8) corresponding to the data set of I (8) and Q (8) is read.
The phase error data Δφ (8) is converted into a phase error voltage by the D / A converter 17, and then a low-frequency component is extracted by the LPF 18 and applied to the VCO 11 as a control voltage.
If the phase error data Δφ (8) is 0, the output of the LPF 18 does not change and the phases of the reference carriers f _C1 and _{fc 2} do not change, but if the phase error data Δφ (8) is +, the LPF
18 output is increased, the reference carrier wave f _C1, f phase _c2 is delayed, conversely, the phase error data [Delta] [phi (8) is - output if LPF18 is reduced, the reference carrier wave f _C1, f _c2
Advances in phase.

In the phase error table 13, the difference between φ and the phase of the nearest signal point arrangement “0” to “7” is the phase error data Δφ (8). Therefore, 8PS on the transmitting side
Phase 0, π / 4, 2π / 4, 3π / 4,
Digital signals having signal point arrangements of 4π / 4, 5π / 4, 6π / 4, and 7π / 4 are respectively expressed in the IQ phase plane on the receiving side by Θ.
= M × π / 4 (where m is an arbitrary integer from 0 to 7; see FIG. 16). Θ is the received signal phase rotation angle. As a result, the received signal points of the 8PSK modulation method have phases 0, π / 4, 2π / 4, 3π /
4, 4π / 4, 5π / 4, 6π / 4, 7π / 4, so the signal point arrangement “0” to “7” on the IQ phase plane on the receiving side is the same as that on the transmitting side. It can be assigned to the phase (however, the correspondence between the signal point arrangement and the digital signal changes according to Θ). If Θ is detected and the phase is rotated by -Θ, the correspondence between the signal point arrangement and the digital signal can be made the same as that on the transmitting side (absolute phase conversion), and the received digital signal can be easily identified.

The phase error tables 14-1 and 14-2 have Q
For PSK, I, Q baseband signals I (8), Q
The phase angle φ on the IQ phase plane of the received signal point shown in (8)
18 and 19 show the relationship between the phase error data Δφ (8) and
It is configured as follows. During normal reception, the selector 16 _{operates in} accordance with the symbol rate clock CLK _SYB ,
Is demodulating a digital modulated wave by the QPSK modulation method, the received signal phase rotation angle Θ is 0, 2π / 4, 4π.
/ 4, 6π / 4, only the phase error table 14-1 is enabled, and the demodulation circuit 1 outputs I, Q for one symbol.
Each time the baseband signals I (8) and Q (8) are output,
The phase error data Δφ (8) corresponding to the set data of I (8) and Q (8) is read from the phase error table 14-1.

In the phase error table 14-1, the difference between φ and the phase of the nearest signal point arrangement “1”, “3”, “5”, “7” is the phase error data Δφ. Therefore, the phase π / 4, 3π / 4 in the QPSK modulation scheme on the transmission side,
5π / 4, 7π / 4 signal point arrangement “1”, “3”,
The digital signals “5” and “7” are respectively transmitted to the I side on the receiving side.
The position is rotated to the position rotated by Θ on the −Q phase plane.
If Θ = 0, 2π / 4, 4π / 4, 6π / 4, QPS
The reception signal point of the K modulation method has a phase of π / 4, 3π / 4, 5π
/ 4, 7π / 4. If Θ is detected and the phase is rotated by -Θ, the correspondence between the signal point arrangement and the digital signal can be made the same as that on the transmitting side (absolute phase conversion), and the received digital signal can be easily identified.

Further, the selector 16 determines whether the demodulation circuit 1
While demodulating a digital modulated wave by the K modulation method, if Θ = π / 4, 3π / 4, 5π / 4, 7π / 4, only the phase error table 14-2 is enabled,
The demodulation circuit 1 outputs the I and Q baseband signals I for one symbol.
Each time (8) and Q (8) are output, the I (8) and Q (8)
Phase error data Δφ (8) corresponding to the set data of (8)
From the phase error table 14-2. In the phase error table 14-2, φ and the nearest signal point arrangement “0”,
The difference between the phases “2”, “4”, and “6” is the phase error data Δφ. Therefore, the digital signals of the signal point arrangements “1”, “3”, “5”, and “7” with phases π / 4, 3π / 4, 5π / 4, and 7π / 4 in the QPSK modulation scheme on the transmission side are obtained. , Respectively, are corrected to positions rotated by Θ on the IQ phase plane on the receiving side. Θ = π / 4, 3π / 4, 5π /
In the case of 4,7π / 4, the received signal point of the QPSK modulation method comes at the phase 0, 2π / 4, 4π / 4, 6π / 4. Θ
If the phase is detected and the phase is rotated by -Θ, the phase can be made the same as the transmitting side (absolute phase conversion), the correspondence between the signal point arrangement and the digital signal can be made the same as the transmitting side, and the digital signal received easily can be Can be identified.

The phase error tables 15-1 to 15-4 are B
For PSK, I, Q baseband signals I (8), Q
The phase angle φ on the IQ phase plane of the received signal point shown in (8)
The relationship between the phase error data Δφ (8) and
It is configured as follows. The selector 16 synchronizes with the symbol rate clock CLK _SYB , and the demodulation circuit 1
If the received signal phase rotation angle に よ る by correcting the phase of the 8PSK modulation portion is 0, 4π / 4 while demodulating the digital modulated wave by the K modulation method, the phase error table 15−
1 is enabled, and each time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, it corresponds to the set data of the I (8) and Q (8). The phase error data Δφ (8) to be read is read from the phase error table 15-1.

In the phase error table 15-1, the difference between φ and the phase of the nearest signal point arrangement “0” or “4” is the phase error data Δφ. Therefore, BPSK on the transmitting side
Signal point arrangement “0” of phase 0, 4π / 4 in modulation scheme,
Each of the digital signals "4" is corrected to the position rotated by the angle Θ on the IQ phase plane on the receiving side. Θ = 0, 4
In the case of π / 4, the received signal point of the BPSK modulation method comes at the phase 0, 4π / 4.

Further, while demodulating the digital modulated wave by the BPSK modulation method, the selector 16 outputs Θ = π /
In the case of 4, 5π / 4, only the phase error table 15-2 is enabled, and each time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-2. In the phase error table 15-2, the difference between φ and the phase of the nearest signal point arrangement “1” or “5” is the phase error data Δ
φ. Therefore, the digital signals of the signal points constellation “0” and “4” of the phase 0 and 4π / 4 in the BPSK modulation scheme on the transmitting side are respectively transmitted on the IQ phase plane of the receiving side by the above-mentioned Θ.
Corrected to the rotated position. Θ = π / 4, 5π / 4
In the case of, the received signal point of the BPSK modulation method has a phase of π / 4,
Come to 5π / 4.

Further, while demodulating the digital modulated wave by the BPSK modulation method, the selector 16 outputs Θ = 2π /
In the case of 4, 6π / 4, only the phase error table 15-3 is enabled, and every time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-3. In the phase error table 15-3, the difference between φ and the phase of the nearest signal point arrangement “2” or “6” is the phase error data Δ
φ. Therefore, the digital signals of the signal points constellation “0” and “4” of the phase 0 and 4π / 4 in the BPSK modulation scheme on the transmitting side are respectively transmitted on the IQ phase plane of the receiving side by the above-mentioned Θ.
Corrected to the rotated position. Θ = 2π / 4, 6π /
4, the received signal point of the BPSK modulation method has a phase of 2π /
Comes at 4,6π / 4.

Further, while demodulating the digital modulated wave by the BPSK modulation method, the selector 16 Θ = 3π /
In the case of 4, 7π / 4, only the phase error table 15-4 is enabled, and each time the demodulation circuit 1 outputs I and Q baseband signals I (8) and Q (8) for one symbol, (8) The phase error data Δφ (8) corresponding to the set data of Q (8) is read from the phase error table 15-4. In the phase error table 15-4, the difference between φ and the phase of the nearest signal point arrangement “3” or “7” is the phase error data Δ
φ. Therefore, the digital signals of the signal points constellation “0” and “4” of the phase 0 and 4π / 4 in the BPSK modulation scheme on the transmitting side are respectively transmitted on the IQ phase plane of the receiving side by the above-mentioned Θ.
Corrected to the rotated position. Θ = 3π / 4, 7π /
4, the received signal point of the BPSK modulation method has a phase of 3π /
Comes at 4,7π / 4. Also in the case of BPSK modulation, if Θ is detected and the phase is rotated by −Θ in opposite phase, the phase can be made the same as that on the transmitting side (absolute phase conversion), and the correspondence between the signal point arrangement and the digital signal can be made the same as on the transmitting side. The received digital signal can be easily identified.

On the other hand, as shown in FIG. 24, the frame synchronization detecting / reproducing circuit 2 comprises a BPSK demapper 3 and a synchronization detecting circuit 4.
0 to 47, a frame synchronization circuit 5, an OR gate circuit 53,
It comprises a frame synchronization signal generator 6. The reception signal phase rotation angle detection circuit 8 includes delay circuits 81, 82, 0
° / 180 ° phase rotation circuit 83, averaging circuits 84, 8
5. It comprises a reception phase determination circuit 86.

The I and Q baseband signals I (8) and Q (8) output from the demodulation circuit 1 are used to capture a BPSK-modulated frame synchronization signal, for example. 3 and BP
The SK demapped bit stream B0 is output. The BPSK demapper unit 3 is constituted by, for example, a ROM.

Next, the frame synchronization signal will be described.
In the hierarchical transmission method, the frame synchronization signal is transmitted after being subjected to BPSK modulation requiring the lowest C / N. The bit stream of the frame synchronization signal composed of 20 bits is (S0S1... S18S19) = (11101)
100110100101000), and are sequentially transmitted from S0. Hereinafter, the bit stream of the frame synchronization signal is also described as “SYNCPAT”. This bit stream is converted into a signal point arrangement “0” or “4” by the BPSK mapping shown in FIG. 13C on the transmission side, and the converted symbol stream is transmitted.

In order to capture a frame synchronization signal of 20 bits, that is, 20 symbols transmitted by BPSK modulation, contrary to the mapping converted on the transmission side,
It is necessary to convert received symbols into bits by the BPSK demapping shown in FIG. Therefore, as shown in FIG. 25A, when the demodulated signal is received in the hatched area on the IQ phase plane on the receiving side (0), and when the demodulated signal is received in the portion without the hatched ( 1) is determined. That is, the output is set to (0) or (1) depending on which of the two determination areas divided by the BPSK determination boundary line shown by the thick line in FIG. 25 (1) has been received, and thereby BPSK demapping is performed.

I, Q Baseband signals I (8), Q
(8) is BPSK demapping to perform BPSK demapping.
The bit stream B0 input to the K demapper unit 3 and subjected to BPSK demapping by the BPSK demapper unit 3.
Is output. In this specification, a demapper refers to a circuit that performs demapping. The bit stream B0 is input to the synchronization detection circuit 40, and the synchronization detection circuit 40 captures a bit stream of a frame synchronization signal from the bit stream B0.

Next, the synchronization detection circuit 40 will be described with reference to FIG. The synchronization detection circuit 40 is connected in series
It has 0 D-flip-flops (hereinafter referred to as DF / F) D19 to D0, and these DF / FD19 to D0 constitute a 20-stage shift register. The bit stream B0 is input to the DF / FD19, and sequentially
Shifted up to DF / FD0 and simultaneously DF
The outputs of / FD19 to / FD0 are input to the AND gate 51 after logical inversion is performed on predetermined bits. In the AND gate 51, the output states of DF / FD19 to D0 (D0D
1 ... D18D19) is (111011001101001)
01000), the output S of the AND gate 51
YNA0 becomes high potential. That is, when SYNCPAT is captured, SYNA0 has a high potential.

The output SYNA0 of the synchronization detection circuit 40 is OR
The signal is input to the frame synchronization circuit 5 via the gate circuit 53. In the frame synchronization circuit 5, when it is confirmed that the output SYA of the OR gate circuit 53 repeatedly becomes a high potential every fixed frame period, it is determined that the frame synchronization is established, and a frame synchronization pulse is output every frame period. You.

Normally, in a hierarchical transmission system in which a plurality of required modulation systems having different C / Ns are time-multiplexed and repeatedly transmitted for each frame, header data indicating their multiplexing structure is multiplexed. (T in FIG. 11 (1)
MCC pattern). After the frame synchronization detecting / reproducing circuit 2 determines that the frame synchronization is established, the transmission configuration identifying circuit 9 outputs the B input from the frame synchronization detecting / reproducing circuit 2.
A TMCC indicating a multiplex configuration is extracted from the bit stream after the PSK demapper, decoded, and a modulation scheme identification signal DM indicating the current I and Q baseband signals I and Q according to the modulation scheme is output to the selector 16 and the like. (Figure 1
1 (2)). Also, the reception signal phase rotation angle detection circuit 8
Detects the received signal phase rotation angle Θ based on the reproduced frame synchronization signal output from the frame synchronization signal generator 6 after the frame synchronization detection / reproduction circuit 2 determines that the frame is synchronized. The bit reception signal phase rotation angle signal AR (3) is output to the remapper 7, the selector 16 of the carrier recovery circuit 10, and the like.

The selector 16 of the carrier recovery circuit 10 receives the modulation scheme identification signal DM from the transmission configuration identification circuit 9 and the reception signal phase rotation angle signal AR (3) from the reception signal phase rotation angle detection circuit 8. After that, the phase error data Δφ (8) is read from the phase error table corresponding to the modulation method and the received signal phase rotation angle Θ, and is output to the D / A converter 17, but until then, the phase error for 8PSK is obtained. The phase error data Δφ (8) is read from the table 13.

Therefore, the demodulation circuit 1 always operates at 8PSK until the transmission configuration identification circuit 9 identifies the multiplex configuration and the reception signal phase rotation angle detection circuit 8 detects the reception signal phase rotation angle Θ.
Since it operates as a demodulation circuit, depending on the phase state of the reference carrier waves f _C1 and f _C2 reproduced by the carrier wave recovery circuit 10 in the demodulation circuit 1, the reception signal point becomes Θ = m ×
The phase is rotated by π / 4 (m is an integer from 0 to 7).

That is, as shown in FIG. 13 (3), BPSK mapping is performed on the transmission side to signal point arrangement "0" for bit (0) and to signal point arrangement "4" for bit (1). The received signal point of the symbol stream of the frame synchronization signal is a signal point arrangement “0” where Θ = 0 as in the transmitting side depending on the phase state of the reference carriers f _C1 and f _C2 ,
The signal point arrangements "1" and "5" appearing at "4", Θ = π / 4 phase rotation, and the signal point arrangements "2" and "6" appearing at Θ = 2π / 4 phase rotation. And Θ
= 3π / 4 phase-rotated signal point constellations “3” and “7”, Θ = 4π / 4 phase-rotated signal point constellations “4” and “0”, and Θ = 5π / In the case where the signal points appear in the signal point arrangements “5” and “1” rotated by four phases, and Θ = 6
The case where the signal point constellation “6” or “2” appears by rotating the phase by π / 4, or the signal point constellation “7” by rotating Θ = 7π / 4 phase.
There are eight different phase states of the demodulated frame synchronization signal, as in the case of appearing at “3”. For this reason, it is necessary to be able to capture a frame synchronization signal that has been demodulated at any phase.

Therefore, the BPSK demapper unit 3 is arranged as shown in FIG.
7, に = 0 (m = 0), Θ = π / 4 (m =
1), Θ = 2π / 4 (m = 2),..., Θ = 6π / 4
(M = 6) and BPSK demappers 30 to 37 corresponding to a phase rotation of Θ = 7π / 4 (m = 7).

FIG. 25 (2) shows that the symbol stream of the demodulated frame synchronization signal is rotated by Θ = π / 4 phase, bit (0) is in signal point arrangement “1” and bit (1) is
Shows the BPSK demapping for the case where appears in the signal point arrangement “5”. The BPSK determination boundary indicated by the bold line in FIG. 25 (2) is counterclockwise with respect to the BPSK determination boundary indicated by the bold line in the BPSK demapping of FIG. It rotates π / 4. By using a BPSK demapper (see reference numeral 31 in FIG. 27) for performing BPSK demapping as shown in FIG. 25 (2), a frame synchronization signal rotated by フ レ ー ム = π / 4 phase can be stably captured. BP with BPSK demapper 31
The SK demapped bit stream is the BP of FIG.
This is the output B1 of the SK demapper unit 3.

Similarly, the BPSK demappers 32 to 37
Are 2π / counterclockwise with respect to the BPSK determination boundary line indicated by the bold line of the BPSK demapping in FIG.
BPS rotated by 4, 3π / 4, ..., 7π / 4
BPSK demapping at the K decision boundary line, Θ = 2π /
A frame synchronization signal whose phase has been rotated by 4, 3π / 4,..., 7π / 4 is stably captured. BPSK demapper 32
The bit streams BPSK demapped by .about.37 are the outputs B2 to B7 of the BPSK demapper unit 3 in FIG. The BPSK demapper 30 performs BPSK demapping at the BPSK determination boundary indicated by the bold line of the BPSK demapping in FIG. 25A, and stably captures a frame synchronization signal of の = 0. BPSK with BPSK demapper 30
The demapped bit stream is BPSK of FIG.
This is the output B0 of the demapper unit 3.

The circuit configuration of the synchronization detection circuits 41 to 47 is the same as that of the synchronization detection circuit 40. By providing such synchronization detection circuits 40 to 47, the demodulation circuit 1
Irrespective of the phase rotation of the baseband signal due to the phase state of the reference carrier waves f _C1 and f _C2 reproduced by the carrier reproduction circuit 10 in any one of the synchronization detection circuits 40 to
At 47, the frame synchronization signal is captured, and the high-potential SYNAn
(N is an integer from 0 to 7) is transmitted.

S output from the synchronization detection circuits 40 to 47
YNAn is input to the OR gate circuit 53, and the OR gate circuit 53 outputs the logical sum SYNA of SYNAn. When it is confirmed that the high potential of the SYNA is alternately and repeatedly input at regular frame intervals, the frame synchronization circuit 5 determines that frame synchronization is established, and outputs a frame synchronization pulse FSYNC at each frame period. .
According to the frame synchronization pulse FSYNC output from the frame synchronization circuit 5, the frame synchronization signal generator 6
The pattern SY of the frame synchronization signal captured by the SK demapper 3, the synchronization detection circuits 40 to 47, and the frame synchronization circuit 5.
It generates the same bit stream as NCPAT (this is called a playback frame synchronization signal).

A frame synchronization signal is captured from the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1 by the frame synchronization detection / reproduction circuit 2 shown in FIG. The process until the reproduction frame synchronization signal is output from the frame synchronization signal generator 6 has been described. Next, the transmission configuration identification operation by the transmission configuration identification circuit 9 will be described. The transmission configuration identification circuit 9 includes bit streams B0 to B7 output from the BPSK demapper 3 of the frame synchronization detection / reproduction circuit 2, SYNA0 to SYNA7 output from the synchronization detection circuits 40 to 47, and a frame synchronization circuit 5.
Is input. Then, when the frame synchronization pulse FSYNC is input, a bit stream Bn of a system having a high potential repeatedly in SYNA0 to SYNA7 is fetched, and a predetermined timing signal generated from the frame synchronization pulse FSYNC is used in FIG. ) Is extracted and decoded to output a modulation scheme identification signal DM indicating what modulation scheme the current I and Q baseband signals I and Q are based on (see FIG. 11 (2)).

Next, the present received signal phase rotation angle is obtained from the signal point arrangement of the captured frame synchronization signal, and the demodulated I and Q baseband signals I (8 ) And Q (8) will be described in terms of absolute phase conversion by rotating them in opposite phases. Each symbol of the symbol stream of the frame synchronization signal, which is BPSK-mapped and transmitted on the transmitting side and demodulated into I and Q baseband signals I (8) and Q (8) by the demodulation circuit 1, is converted by the BPSK demapper unit 3 The symbol is demapped to bit (0) or (1). The phase difference between the symbol demapped to bit (0) and the symbol demapped to (1) is 180 °. Therefore, the symbol stream demapped to bit (0) can be obtained by rotating the symbol demapped to bit (1) of the frame synchronization signal portion of the received symbol stream by 180 °.

Further, by determining the average value over a plurality of symbols of the symbol stream demapped to all the bits (0), the reception signal point arrangement with respect to the BPSK bit (0) is obtained. Therefore, the received signal point for bit (0) of the determined BPSK,
On the transmitting side, a phase difference from the signal point arrangement “0” mapped to bit (0) is obtained, and this is calculated as the received signal phase rotation angle Θ
And η = − is applied to the entire demodulated I and Q baseband signals.
By performing the phase rotation of Θ, the absolute phase of the I and Q baseband signals I (8) and Q (8) can be achieved.

As described above, in response to the frame synchronization pulse output from the frame synchronization circuit 5, the frame synchronization signal generator 6 sets the pattern S of the captured frame synchronization signal.
The same bit stream as that of YNCPAT is generated and supplied to a 0 ° / 180 ° phase rotation circuit 83 in the reception signal phase rotation angle detection circuit 8 as a reproduced frame synchronization signal. 0
The {/ 180} phase rotation circuit 83 converts the I and Q baseband signals in the case of (1) based on the bit (0) or (1) in the bit stream of the supplied reproduced frame synchronization signal. The phase is rotated by 180 °, and in the case of (0), the phase is not rotated.

The timing of the bit stream of the reproduced frame synchronization signal sent from the frame synchronization signal generator 6 and the timing of the symbol stream of the frame synchronization signal in the I and Q symbol streams are 0 ° / 180 ° by the delay circuits 81 and 82. The phase is matched on the input side of the phase rotation circuit 83. Since the delay circuits 81 and 82 open their output gates only while the frame synchronization signal section signal is being output from the frame synchronization signal generator 6, the delay circuits 8 and 82 open.
From I and 82, I and Q symbol streams DI (8) and DQ (8) of the frame synchronization signal portion are output. These I and Q symbol streams DI (8) and DQ (8)
The symbol portion corresponding to bit (1) in the bit stream of the reproduced frame synchronization signal is rotated by 180 ° in the 0 ° / 180 ° phase rotation circuit 83, and the symbol portion corresponding to bit (0) is not phase-rotated. , Symbol streams VI (8) and VQ (8) to the averaging circuits 84 and 85. The symbol streams VI (8) and VQ (8) are symbol streams when a BPSK-mapped signal is received on the transmission side on the assumption that all 20 bits forming the frame synchronization signal are bits (0).

FIG. 28A shows the received signal phase rotation angle Θ = 0.
FIG. 28 (2) shows the signal point arrangement of the I and Q symbol streams I (8) and Q (8) of the frame synchronizing signal when the signal is received in FIG.
3, the I and Q symbol streams V converted
The signal point arrangement of I (8) and VQ (8) is shown. I and Q symbol streams VI (8), VQ (8)
Are sent to averaging circuits 84 and 85, respectively.
After the quantization bit length is converted to about 16 to 18 bits, four frames (20 × 4 = 80 symbols) are averaged, and the averaged value is based on the original 8-bit quantization bit length. Output as AVI (8) and AVQ (8). Here, the I and Q symbol streams VI (8), V
The averaging is performed on Q (8) so that the signal point arrangement can be stably obtained even when a small phase change or amplitude change of the received baseband signal occurs due to deterioration of the received C / N. To do that.

Received signal point [A of the signal in which bit (1) is BPSK mapped by averaging circuits 84 and 85 [A
VI (8), AVQ (8)]. Next, the received signal points [AVI (8), AVQ (8)] are input to a phase determination circuit 87 composed of a ROM, and the AVI shown in FIG.
The received signal phase rotation angle Θ is obtained according to the received signal phase rotation angle determination table on the AVQ phase plane, and the 3-bit (natural binary number) phase rotation angle signal AR corresponding to Θ is obtained.
(3) is output. R = 0 to 7 in FIG. 29 indicate a decimal number representation of the phase rotation angle signal AR (3). For example, the point Z = [AVI (8), AVQ shown in FIG.
(8)], the received signal phase rotation angle determined by the received signal phase rotation angle determination table is Θ = 0. Therefore, R = 0, and the received signal phase rotation angle signal AR
(000) is transmitted as (3). If the received signal phase rotation angle π is π / 4, R = 1, and (001) is transmitted as the received signal phase rotation angle signal AR (3).

The remapper 7 comprising a ROM receives the received signal phase rotation angle signal AR (3) and converts the I and Q baseband signals I (8) and Q (8) to the received signal phase rotation angle signal A (3).
By rotating the phase according to R (3), absolute phase conversion is achieved. The operation of the remapper 7 will be described. The remapper 7 receives the I and Q baseband signals I (8), Q
A phase conversion circuit is configured to make the signal point arrangement of (8) the same as that on the transmission side. The reception signal phase rotation angle detection circuit 8 calculates the reception signal phase rotation angle Θ, and supplies the reception signal phase rotation angle signal AR (3) corresponding to the reception signal phase rotation angle に to the remapper 7. here,
The decimal representation R of the received signal phase rotation angle signal AR (3) is 0.
And the relationship with the received signal phase rotation angle Θ is
It is defined as shown in the following equation (1).

R = Θ / (π / 4) (1) where Θ = m · (π / 4), and m is an integer of 0 to 7. For the absolute phase conversion of the I and Q baseband signals, the received signal phase rotation angle Θ may be subjected to reverse rotation, ie, −Θ phase rotation. Therefore, the remapper 7 rotates the phase of the input I and Q baseband signals I and Q by the angle η (= −Θ) according to the following equations (2) and (3), and sets the absolute phase I , Q baseband signal I ′
(8), Q '(8) (hereinafter the quantization bit number is omitted and I
'And Q'). I ′ = Icos (η) −Qsin (η) (2) Q ′ = Isin (η) + Qcos (η) (3)

[0049]

However, in the above-described conventional received signal phase rotation angle detection circuit, if the 0 ° / 180 ° phase rotation circuit 83 is configured by table conversion, the memory capacity required for the conversion is 128 k. Bytes (= 2
¹⁶ also becomes × 16bit), similarly, when to configure the received signal phase rotation angle judgment circuit 87 by table conversion, it required memory capacity will be in 2 ¹⁶ × 3bit, that the circuit becomes large There was a problem. SUMMARY OF THE INVENTION It is an object of the present invention to provide a reception signal absolute phasing device for a receiver that requires a small circuit scale.

[0050]

According to a first aspect of the present invention, there is provided an apparatus for absolutely phase-receiving a received signal, comprising: a BPSK-modulated frame synchronizing signal; an 8PSK-modulated digital signal; and a QPSK-modulated digital signal. And BPSK
A PSK modulated signal obtained by time-multiplexing at least an 8PSK-modulated digital signal among the modulated digital signals is demodulated using a carrier reproduced by a carrier reproducing means, and I and Q symbol stream data is output. Demodulation means, frame synchronization signal acquisition means for acquiring a frame synchronization signal from the demodulated I and Q symbol stream data, and reception for detecting the phase rotation angle of the I and Q symbol stream data output from the demodulation means with respect to the transmission side Signal phase rotation angle detection means, I output from demodulation means,
An anti-phase rotation means for rotating the phase of the Q symbol stream data by an amount corresponding to the phase rotation angle detected by the reception signal phase rotation angle detection means, and outputting the result. Separately, various I, Q after demodulation
It has a phase error table storing carrier phase error data for the symbol stream data set, and during normal reception,
While the demodulation means is demodulating a certain modulation scheme part, the phase error data corresponding to the demodulated I and Q symbol stream data is read from the phase error table of the corresponding modulation scheme, and the phase of the carrier is corrected. In the receiver, the reception signal phase rotation angle detection means detects the absolute value of the phase error among the phase error data corresponding to the demodulated I and Q symbol stream data from the phase error table for BPSK modulation of the carrier recovery means. The value is (π / 8) + s · (π
/ 8) phase error data reading means for reading out an upper bit that is known to be larger or smaller than (s is 0, 1, 2);
Code of I (or Q) symbol stream data corresponding to bit (0) (or (1)) of the frame synchronization signal captured by the frame synchronization signal capturing unit in the demodulated I and Q symbol stream data From the bit data and the phase error data read by the phase error data reading means corresponding to the relevant part, the bit (0) (0) of the frame synchronization signal in the I and Q symbol stream data output from the demodulation means Or the phase rotation angle of the symbol portion corresponding to (1)) with respect to the transmitting side is determined,
And a determination unit that outputs a determination result. According to the apparatus of the first aspect, the phase rotation angle of the received signal is such that the absolute value of the phase error of the phase error data of the phase error table for the BPSK modulation corresponding to the demodulated I and Q symbol stream data is (Π / 8) + s
(Π / 8) (s is 0, 1, 2) Higher-order bits that are known to be larger or smaller, and bit (0) of the frame synchronization signal
(Or (1)) is uniquely determined by the sign bit data of the I (or Q) symbol stream data corresponding to (1), and the received signal phase rotation angle can be determined by a simple operation. Therefore, it is not necessary to use a dedicated large-scale ROM to determine the phase rotation angle, and the circuit scale can be reduced. According to a second aspect of the present invention, there is provided a receiver absolute phase shifter for a receiver, wherein a BPSK-modulated frame synchronizing signal, an 8PSK-modulated digital signal, and a QPSK signal.
A PSK modulated signal in which at least an 8PSK-modulated digital signal and a QPSK-modulated digital signal of the modulated digital signal and the BPSK-modulated digital signal are time-multiplexed is converted into a carrier reproduced by a carrier reproducing means. Demodulation means for outputting I and Q symbol stream data by demodulation, frame synchronization signal acquisition means for acquiring a frame synchronization signal from the demodulated I and Q symbol stream data, and I and Q output from the demodulation means.
The received signal phase rotation angle detecting means for detecting the phase rotation angle of the Q symbol stream data with respect to the transmitting side, and the phases of the I and Q symbol stream data output from the demodulating means are detected by the received signal phase rotation angle detecting means. An anti-phase rotation means for outputting a phase-rotated anti-phase signal by an amount corresponding to the phase rotation angle. During normal reception, while the demodulation means is demodulating a certain modulation scheme part, the demodulated I and Q symbol stream data is referred to by referring to the phase error table of the corresponding modulation scheme. In the receiver, the phase error data corresponding to the received signal is read and the phase of the carrier wave is corrected. From the phase error table for QPSK modulation of the reproducing means, the upper bits of the phase error data corresponding to the demodulated I and Q symbol stream data, which indicate whether the absolute value of the phase error is larger or smaller than π / 8, Phase error data reading means to be read, and I and Q after demodulation
Of the symbol stream data, the code bit data of the I and Q symbol stream data corresponding to the bit (0) (or (1)) of the frame synchronization signal captured by the frame synchronization signal capturing means, and From the phase error data read out by the phase error data reading means, the bits (0) (or (1)) of the frame synchronization signal in the I and Q symbol stream data output from the demodulation means. Determining means for determining a phase rotation angle of the symbol portion with respect to the transmitting side and outputting a determination result. According to the apparatus of claim 2, the phase rotation angle of the received signal is I,
Among the phase error data according to the phase error table for QPSK modulation corresponding to the Q symbol stream data, upper bits for determining whether the absolute value of the phase error is larger or smaller than π / 8, and bit (0) of the frame synchronization signal (Or (1)) It is uniquely determined by the sign bit data of the I and Q symbol stream data corresponding to (1), and the received signal phase rotation angle can be determined by a simple calculation. Therefore, it is not necessary to use a dedicated large-scale ROM to determine the phase rotation angle, and the circuit scale can be reduced. According to a third aspect of the present invention, there is provided a reception signal absolute phase shifter for a receiver, comprising: a BPSK-modulated frame synchronization signal;
A PS in which at least one of a modulated digital signal, a QPSK modulated digital signal and a BPSK modulated digital signal is time-multiplexed.
A demodulation means for demodulating the K modulated signal using the carrier reproduced by the carrier reproduction means and outputting I and Q symbol stream data, and a frame for acquiring a frame synchronization signal from the demodulated I and Q symbol stream data A synchronization signal acquisition unit, a reception signal phase rotation angle detection unit that detects a phase rotation angle of the I and Q symbol stream data output from the demodulation unit with respect to the transmission side, and an I / Q symbol stream data output from the demodulation unit. Phase, and an anti-phase rotation means for outputting the phase in reverse phase rotation by the phase rotation angle detected by the reception signal phase rotation angle detection means, and the carrier recovery means of the demodulation means, for each modulation method, It has a phase error table that stores carrier phase error data for various I and Q symbol stream data sets. While demodulates the modulation method portion that,
I after demodulation from the phase error table of the corresponding modulation method,
In a receiver for reading phase error data corresponding to Q symbol stream data and correcting the phase of a carrier wave, the reception signal phase rotation angle detection means demodulates from a phase error table for BPSK modulation of the carrier wave reproduction means. Of the phase error data corresponding to the subsequent I and Q symbol stream data, the absolute value of the phase error is (π / 8) + s
A phase error data reading means for reading out an upper bit which is known to be larger or smaller than (π / 8) (s is 0, 1, 2); and a demodulated I and Q symbol stream data,
I of the portion corresponding to bit (0) (or (1)) of the frame synchronization signal captured by the frame synchronization signal capturing means
(Or Q) From the sign bit data of the symbol stream data and the phase error data read by the phase error data reading means corresponding to the part, of the I and Q symbol stream data output from the demodulation means,
A discrimination means for discriminating the phase rotation angle of the symbol portion corresponding to bit (0) (or (1)) of the frame synchronization signal with respect to the transmitting side and outputting a discrimination result. According to the third aspect of the present invention, the phase rotation angle of the received signal is such that the absolute value of the phase error of the phase error data of the phase error table for the BPSK modulation corresponding to the demodulated I and Q symbol stream data is (Π / 8) +
Upper bits that determine whether s · (π / 8) (s is 0, 1, 2) or less, and I (or Q) corresponding to bit (0) (or (1)) of the frame synchronization signal 2.) The phase rotation angle of the received signal is uniquely determined by the sign bit data of the symbol stream data, and can be determined by a simple operation. Therefore, it is not necessary to use a dedicated large-scale ROM to determine the phase rotation angle, and the circuit scale can be reduced. According to a fourth aspect of the present invention, there is provided a receiver absolute phase shifter for a receiver, comprising: a BPSK-modulated frame synchronizing signal; an 8PSK-modulated digital signal; a QPSK-modulated digital signal; Demodulating a PSK modulated signal obtained by time-multiplexing at least a QPSK-modulated digital signal using a carrier reproduced by the carrier reproducing means, and outputting I and Q symbol stream data; Frame synchronization signal capturing means for capturing a frame synchronization signal from the I and Q symbol stream data; and reception signal phase rotation angle detection means for detecting a phase rotation angle of the I and Q symbol stream data output from the demodulation means with respect to the transmitting side. , I and Q output from the demodulation means
An anti-phase rotation means for outputting the phase of the symbol stream data by performing an anti-phase rotation by the phase rotation angle detected by the reception signal phase rotation angle detection means, and outputting the carrier wave. And a phase error table storing carrier phase error data for various demodulated I and Q symbol stream data sets. During normal reception, while the demodulation means demodulates a certain modulation scheme, the corresponding modulation is performed. I and Q after demodulation with reference to the phase error table of the system
In a receiver which reads out phase error data corresponding to symbol stream data and corrects the phase of a carrier wave, the reception signal phase rotation angle detection means uses a phase error table for QPSK modulation of a carrier wave reproduction means to perform demodulation after demodulation. Phase error data reading means for reading out the upper bits of the phase error data corresponding to the I and Q symbol stream data for determining whether the absolute value of the phase error is larger or smaller than π / 8; Of the symbol stream data, the code bit data of the I and Q symbol stream data corresponding to the bit (0) (or (1)) of the frame synchronization signal captured by the frame synchronization signal capturing means, and And output from the demodulation means from the phase error data read by the phase error data reading means. Of the Q symbol stream data, a frame synchronization signal of the bit (0) (or (1))
And a discriminating means for discriminating a phase rotation angle of the symbol portion corresponding to the symbol with respect to the transmitting side and outputting a discrimination result. According to the apparatus of claim 4, the phase rotation angle of the received signal is such that the absolute value of the phase error of the phase error data of the phase error table for the QPSK modulation corresponding to the demodulated I and Q symbol stream data is It is unambiguously determined by upper bits that determine whether it is larger or smaller than π / 8 and code bit data of I and Q symbol stream data corresponding to bit (0) (or (1)) of the frame synchronization signal. The received signal phase rotation angle can be determined by a simple calculation. Therefore, it is not necessary to use a dedicated large-scale ROM to determine the phase rotation angle, and the circuit scale can be reduced.

[0051]

Next, a first embodiment of the present invention will be described with reference to FIG. FIG. 1 shows a PSK according to the present invention.
FIG. 13 is a block diagram of a main part of a receiver of a modulated wave, and the same components as those in FIG. 12 are denoted by the same reference numerals. After the start of reception, the selector 16A of the carrier recovery circuit 10A operates until the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8A detects the reception signal phase rotation angle (Θ). Is the symbol clock CLK _SYB
(H level section of CLK _SYB ; see FIG. 11 (2)) during the rise of the phase error table 13 for 8PSK.
(See FIG. 17), and the I and Q symbol stream data I output from the demodulation circuit 1A while the symbol clock CLK _SYB rises.
(8), phase error data Δφ (8) corresponding to Q (8)
Is read out and output to the D / A converter 17. In parallel with this, while the symbol clock CLK _SYB is falling (L level section of CLK _SYB ; see FIG. 11 (2)), the phase error table 15-1 for BPSK (FIG. 20)
) Is enabled and the symbol clock CLK
_{While the SYB} falls, the I and Q symbol stream data I (8), Q output from the demodulation circuit 1A
Of the phase error data Δφ (8) corresponding to (8), the upper 3 bits (referred to as phase error data Δφ (3)) are read and output to the reception signal phase rotation angle detection circuit 8A. From the phase error data Δφ (3), it can be determined whether the absolute value of the phase error is larger or smaller than (π / 8) + s · (π / 8) (s is 0, 1, 2).

After the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8A detects the reception signal phase rotation angle (Θ), the selector 16
A indicates that the I and Q symbol stream data I and Q are obtained from the phase error table corresponding to the modulation scheme of the received signal demodulated by the demodulation circuit 1A and the received signal phase rotation angle (Θ) while the symbol clock CLK _SYB rises. (8), Q
The phase error data Δφ (8) corresponding to (8) is read out and output to the D / A converter 17, while the symbol clock C
While the LK _SYB falls, the phase error data Δφ corresponding to the I and Q symbol stream data I (8) and Q (8) from the BPSK phase error table 15-1.
Out of (8), upper three bits of phase error data Δφ (3)
Is read.

Reference numeral 90 denotes a delay circuit, and the selector 16
A outputs the phase error data Δφ (3) read by A for a predetermined time. In the delay circuit 90, the frame synchronization detecting / reproducing circuit 2 uses the I and Q symbol stream data I
(8), When the frame synchronization signal is captured from Q (8) and the output of the reproduction frame synchronization signal is started, I, Q
Phase error data Δφ (3) corresponding to the first part of the frame synchronization signal is output from the symbol stream data I (8) and Q (8). Reference numeral 91 denotes a delay circuit, which is an MS of the Q symbol stream data Q (8).
The code bit data q (1) of B is output with a delay of a predetermined time. In the delay circuit 91, the frame synchronization detecting / reproducing circuit 2 uses I and Q symbol stream data I (8),
When the frame synchronization signal is captured from Q (8) and the output of the reproduction frame synchronization signal is started, the code bit data q (1 ) Is output.

Reference numeral 92 denotes a phase rotation angle discriminating circuit which outputs I and Q symbol streams I (8) and Q (8) output from the demodulation circuit 1A from a portion corresponding to the frame synchronization signal output from the delay circuits 90 and 91. ), The phase rotation angle with respect to the transmitting side is determined for the symbol portion corresponding to bit (1) of the frame synchronization signal, and the phase rotation angle with respect to the transmitting side is determined for the symbol portion corresponding to bit (0) of the frame synchronization signal. And sequentially outputs the result of the determination. In the phase rotation angle discriminating circuit 92, reference numeral 93 denotes a 4-bit adder for adding 4-bit data (however, the carry to the fifth bit is not carried out). , And the output of the delay circuit 90 is input to the lower three bits. Adder 9
A selector 94 is connected to the other input side of 3 and
The selector 94 inputs a bit stream of a reproduction frame synchronization signal output from the frame synchronization detection / reproduction circuit 2, and when a bit (0) portion is input, the selector 94 outputs A.
(4) = (0001) is output, and when the bit (1) is input, B (4) = (1001) is output.
The adder 93 outputs the upper 3 bits of the addition result as a phase rotation angle signal R (3).

Reference numeral 95 denotes an averaging circuit for averaging the phase rotation angle signal R (3). Here, as an example, the frame synchronization signal is averaged over four frames, and a remapper is obtained as the phase rotation angle signal AR (3). 7 and the selector 16A. A specific example of the averaging circuit 95 will be described later. The other components are configured exactly the same as in FIG.

Next, the operation of the above embodiment will be described. (1) Start of Reception After the start of reception, the selector 16A of the carrier recovery circuit 10A identifies the multiplexed configuration of the frame by the transmission configuration identification circuit 9, and the received signal phase rotation angle detection circuit 8A detects the received signal phase rotation angle. Until the symbol clock CLK
_{During the} rise of _SYB, only the phase error table 13 for 8PSK is enabled and the symbol clock CL
I and Q symbol stream data I (8), Q output from demodulation circuit 1A while K _SYB is rising
The phase error data Δφ (8) corresponding to (8) is read out and output to the D / A converter 17. In parallel with this,
While the symbol clock CLK _SYB is falling, B
Only the phase error table 15-1 for PSK is enabled, and corresponds to the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1A while the symbol clock CLK _SYB falls. The phase error data Δφ (3) is read and output to the delay circuit 90.

When the selector 16A outputs the phase error data Δφ (8) read from the 8PSK phase error table 13 to the D / A converter 17, the D / A converter 17 converts the phase error data into a phase error voltage. The low-frequency component is extracted by the LPF 18 and applied to the VCO 11 as a control voltage.
If the phase error data Δφ (8) is 0, the output of the LPF 18 does not change and the phases of the reference carriers f _C1 and _{fc 2} do not change, but if the phase error data Δφ (8) is +, the LPF
18 output is increased, the reference carrier wave f _C1, f phase _c2 is delayed, conversely, the phase error data [Delta] [phi (8) is - output if LPF18 is reduced, the reference carrier wave f _C1, f _c2
Advances in phase. As a result, the phases of the reference carriers f _C1 and f _c2 are corrected so as to maintain a fixed relationship with the phase of the received carrier. As a result, the demodulation circuit 1A outputs the phase 0,
π / 4, 2π / 4, 3π / 4, 4π / 4, 5π / 4, 6
The digital signals of the signal point arrangements “0” to “7” of π / 4 and 7π / 4 are respectively converted into Θ = mx on the IQ phase plane on the receiving side.
The position is corrected to a position rotated by π / 4 (where m is an arbitrary integer from 0 to 7).

On the other hand, in the phase error table 15-1, the I and Q symbol stream data I (8), Q
In the phase error data Δφ (3) of the upper 3 bits of the phase error data Δφ (8) corresponding to (8), the absolute value of the phase error is (π / 8) + s · (π / 8) (s is 0 1, 2) is the number of bits that can be determined to be larger or smaller (see FIG. 20). This Δφ (3) and Q symbol stream data Q
By combining with the sign bit data q (1), which is the MSB of (8), and performing simple arithmetic processing, it is possible to determine which of the eight signal point constellations “0” to “7” the received signal point corresponds to. Since the signal point constellation on the transmitting side of bit (0) (or bit (1)) of the frame synchronization signal is determined to be “0” (or “4”), Δφ (3) and Q symbol stream data The received signal phase rotation angle is uniquely determined from the sign bit data which is the MSB.

In the received signal phase rotation angle detection circuit 8A, first, the delay circuits 90 and 91 output the phase error data Δφ (3) output from the selector 16A and the Q symbol stream data Q ( 8) The code bit data q (1) is delayed, and the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal from the I and Q symbol stream data and starts outputting the reproduction frame synchronization signal. 90, the phase error data Δφ (3) corresponding to the head of the frame synchronization signal portion of the I and Q symbol stream data I (8) and Q (8) is output. The timing is adjusted so that the code bit data q (1) corresponding to the head of the frame synchronization signal portion of (8) is output. The to. Delay circuits 91 and 90
Are input as the upper bit and the lower bit on one input side of the adder 93.

A short time after the start of reception, the frame synchronization detecting / reproducing circuit 2 outputs the I and Q symbol streams I (8), Q
(8) The frame synchronization signal is captured and a reproduced frame synchronization signal is output. Then, the selector 94 determines that A (4) = A (4) = bit (0) of the reproduced frame synchronization signal.
(0001) is selected and output, and in the part of bit (1), B (4) = (1001) is selected and output. The adder 93 performs an addition operation of one input and the other input at each bit position of the 20-bit reproduced frame synchronization signal,
Outputs the upper 3 bits. Then, from the adder 93,
As shown in FIG. 2A, the received signal phase rotation angle ０ is 0, π
/ 4, 2π / 4, 3π / 4, 4π / 4, 5π / 4, 6π
/ 4, 7π / 4, and when corresponding to R = 0 to 7 in decimal notation, a received signal phase rotation angle signal R (3) in which R is expressed by a 3-bit natural binary number is output (FIG. 9). 2 (2)).

The averaging circuit 95 takes in the output of the adder 93 while the frame synchronization signal section signal is being input from the frame synchronization detection / reproduction circuit 2. And, for example, 4
The result is averaged over the frame, and the result is output to the remapper 7 as the received signal phase rotation angle signal AR (3), thereby performing absolute phase conversion. Further, it also outputs the received signal phase rotation angle signal AR (3) to the selector 16A. The averaging of the received signal phase rotation angle signal R (3) is performed stably even when a small phase change or amplitude change of the received baseband signal occurs due to deterioration of the received C / N. This is for obtaining the phase rotation angle.

FIG. 3 shows an example of the averaging circuit 95. Received signal phase rotation angle signal R (3) output from adder 93
Is converted into a 3-bit Gray code by a Gray code converter 96 in accordance with FIG. Gray codes have the property that only one bit position changes between adjacent codes. The output of the Gray code converter 96 has a bit position G
The majority decision circuits 97-1 to 97-3 are provided separately for 0 to G2, and the bits (1) and (0) are supplied from the gray code converter 96 while the frame synchronization signal section signal over four frames is being input. Are determined to be output more. Outputs F0 to F of majority decision circuits 97-1 to 97-3
2 is input to a binary code converter 98, and conversion reverse to that of the Gray code converter 96 is performed according to FIG. The output of the binary code converter 98 is output as the received signal phase rotation angle signal AR (3).

It is also possible to omit the gray code converter 96 and the binary code converter 98 and directly input the output of the adder 93 to the majority decision circuits 97-1 to 97-3 to make a majority decision. . However, once the Gray encoding is performed, even if the phase indicated by the received signal phase rotation angle signal R (3) changes by π / 4, the code always changes only in one bit position, and the received C / N deteriorates. Causes slight phase changes and amplitude fluctuations of the received baseband signal, and the received signal phase rotation angle signal R (3) is erroneously shifted by π / 4, the effect can be minimized, and the reliability is improved. Increase.

(2) Normal Reception Operation Immediately after the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal, the transmission configuration identification circuit 9 identifies the multiplex configuration and outputs the current I and Q output from the demodulation circuit 1A. A modulation scheme identification signal DM indicating which modulation scheme part the symbol stream is output to the selector 16A and the like.

The selector 16A, to which the received signal phase rotation angle signal AR (3) is input from the averaging circuit 95, uses, for example, the received signal phase rotation angle by using the modulation scheme identification signal DM input from the transmission configuration identification circuit 9. When the received signal phase rotation angle の indicated by the signal AR (3) is 3π / 4, the demodulation circuit 1A
During the demodulation of the 8PSK modulation method portion, while the symbol clock CLK _SYB rises,
Only the phase error table 13 for the SK modulation method is enabled. From the phase error table 13, I and Q symbol stream data I (8) output from the demodulation circuit 1A while the symbol clock CLK _SYB rises,
The phase error data Δφ (8) corresponding to Q (8) is read and output to the D / A converter 17. As a result, regardless of the phase variation of the received carrier, the signal point arrangement “0” on the transmitting side,
"1", "2", "3", "4", "5", "6",
The digital signal (a
bc) are signal point constellations “3”, “4”,
The phases of the reference carriers f _C1 and f _C2 are corrected so that they appear in “5”, “6”, “7”, “0”, “1”, and “2”.
I and Q symbol stream data I (8) and Q (8) of the 8PSK modulation scheme portion output from demodulation circuit 1A
Is rotated by η = −Θ = −3π / 4 by the remapper 7, so that the received signal points of the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 are transmitted. Match side.

When Θ is 3π / 4, the demodulation circuit 1A
During the demodulation of the SK modulation scheme, the selector 16A enables only the phase error table 14-2 while the symbol clock CLK _SYB is rising, and the selector 16A _{outputs the} phase error table 14-2 (see FIG. 19). ,
Phase error data Δφ corresponding to the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1A while the symbol clock CLK _SYB is rising.
(8) is read and output to the D / A converter 17. As a result, the signal point arrangements “1”, “3”, “5”,
The digital signal (d
e) are the signal point constellations “4”, “6”,
Since the phases of the reference carriers f _C1 and f _C2 are corrected so as to appear in “0” and “2”, the phase rotation angle of the received signal at 8PSK is maintained. The I and Q symbol stream data I (8) and Q (8) of the QPSK modulation scheme output from the demodulation circuit 1A are also converted by the remapper 7 into η.
= −Θ = −3π / 4, so that the I and Q symbol stream data I ′ output from the remapper 7
(8), the reception signal point of Q '(8) coincides with the transmission side.

When Θ is 3π / 4, the demodulation circuit 1A
During the demodulation of the SK modulation scheme, the selector 16A enables only the phase error table 15-4 (see FIG. 23) while the symbol clock CLK _SYB rises. , Phase error data Δφ corresponding to the I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1A while the symbol clock CLK _SYB is rising.
(8) is read and output to the D / A converter 17. As a result, the reference carrier f _C1, the phase of the f _C2 is modified, it is held in the same phase rotation angle as the received signal phase rotation angle at 8PSK. Since the I and Q symbol stream data I (8) and Q (8) of the BPSK modulation scheme output from the demodulation circuit 1A are also phase-rotated by η = −Θ = −3π / 4 by the remapper 7, the remapper 7 The received signal points of the I and Q symbol stream data I '(8) and Q' (8) output from the transmitting side coincide with the transmitting side.

Note that the selector 16A also operates during the normal reception operation.
While the symbol clock CLK _SYB is falling
Only the phase error table 15-1 is enabled, and the symbol clock CLK
I and Q symbol stream data I (8), Q (8) output from demodulation circuit 1A while _SYB is falling
Is read out and output to the delay circuit 90. Then, the phase rotation angle determination circuit 92 determines the phase rotation angle based on the outputs of the delay circuits 90 and 91, and outputs the determination result as the received signal phase rotation angle signal R.
The signal is output in the form of (3), and the averaging circuit 95 averages the data for four frames and outputs the result as the received signal phase rotation angle signal AR (3). If the received signal phase rotation angle の indicated by AR (3) is the same as before, the phase rotation angle of the remapper 7 does not change, and the phase error table selected by the selector 16A does not change. If the angle Θ changes, the remapper 7 rotates by −Θ with respect to the new Θ. Further, the selector 16A is connected to the symbol clock CL.
The phase error table to be selected while K _{SYB falls} is changed according to the change of Θ.

For example, during the period when the demodulation circuit 1A is demodulating the 8PSK modulation scheme, the symbol clock CL
While K _SYB is rising, 8 regardless of the value of ８
Only the phase error table 13 for the PSK modulation method is enabled, and the phase error data Δφ (8) is read from the phase error table 13. While CLK _SYB is rising, Θ = 0, 2π / 4,
In the case of 4π / 4 and 6π / 4, the phase error table 14-1
Is enabled, the phase error data Δφ (8) is read from the phase error table 14-1, and Θ = π / 4,
In the case of 3π / 4, 5π / 4, 7π / 4, only the phase error table 14-2 is enabled, and the phase error data Δφ (8) is read from the phase error table 14-2. During the period in which the demodulation circuit 1A is performing demodulation of the BPSK modulation scheme, while the symbol clock CLK _SYB is rising, if Θ = 0, 4π / 4, the phase error table 15
-1 is enabled and the phase error table 15-
The phase error data Δφ (8) is read from 1 and Θ = π /
In the case of 4, 5π / 4, only the phase error table 15-2 is enabled, the phase error data Δφ (8) is read from the phase error table 15-2, and Θ = 2π / 4, 6π
/ 4, only the phase error table 15-3 is enabled, the phase error data Δφ (8) is read from the phase error table 15-3, and if Θ = 3π / 4, 7π / 4, the phase error table 15-3 is enabled. -4 only enabled,
The phase error data Δφ is obtained from the phase error table 15-4.
Read (8).

According to this embodiment, the BP corresponding to the I and Q symbol stream data corresponding to bit (1) (bit (0)) of the demodulated frame synchronization signal
The absolute value of the phase error in the phase error data according to the SK modulation phase error table is (π / 8) + s · (π / 8)
(S is 0, 1, 2) Top 3 which is bigger or smaller
From the bits and the code bit data q (1) of the Q symbol stream data, the bit (1) of the frame synchronization signal is obtained.
Since the phase rotation angles of the I and Q symbol stream data I (8) and Q (8) corresponding to ((0)) are determined, the received signal phase rotation angle can be determined by a simple calculation. Therefore, a large-scale R dedicated for determining the phase rotation angle is used.
It is not necessary to use the OM, and the circuit scale can be reduced.

In the above-described embodiment, the code bit data q of the Q symbol stream data Q (8)
Although (1) is used, code bit data which is the MSB of the I symbol stream data I (8) may be used instead. Also, instead of reading out the phase error data Δφ (3) from the phase error table 15-1, one of the phase error tables 15-2, 15-3, and 15-4 reads out the phase error data Δφ (8). (See FIGS. 21 to 23). These changes are made in selector 9
This can be done simply by appropriately changing the values of A (4) and B (4) selected by 4. Further, although the phase rotation angles are determined for both the bit (1) and the bit (0) of the frame synchronization signal of the I and Q symbol stream data, only one of them may be performed. The averaging method in the averaging circuit 95 can be changed in various ways. For example, averaging may be performed for one frame or two frames, or one or more bits at a specific position of the frame synchronization signal may be changed. Averaging may be performed over a plurality of frames.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 5 is a block diagram of a main part of the PSK modulated wave receiver according to the present invention, and the same components as those in FIG. In the embodiment shown in FIG. 1, the phase error data Δφ (3) is read from the BPSK phase error table 15-1, but in FIG. 5, the QPSK phase error table 14-1 (see FIG. 18). , The phase error data Δφ (3) is read.

Selector 16B of carrier wave recovery circuit 10B
After the start of reception, the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame, and the reception signal phase rotation angle detection circuit 8B
Until the detection of the phase rotation angle of the received signal, only the 8PSK phase error table 13 is enabled while the symbol clock CLK _SYB rises.
From the phase error table 13 for the symbol clock CL
I and Q symbol stream data I (8), Q output from demodulation circuit 1B while K _SYB is rising
The phase error data Δφ (8) corresponding to (8) is read out and output to the D / A converter 17. In parallel with this,
While the symbol clock CLK _SYB is falling, Q
Only the phase error table 14-1 for PSK is enabled, and the I and Q symbol stream data I and Q output from the demodulation circuit 1B while the symbol clock CLK _{SYB falls} from the phase error table 14-1.
(8), phase error data Δφ (8) corresponding to Q (8)
Among them, the phase error data Δφ (3) of the upper 3 bits is read and output to the reception signal phase rotation angle detection circuit 8B. From the phase error data Δφ (3), the absolute value of the phase error is π /
You can see if it is larger or smaller than 8.

After the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8B detects the reception signal phase rotation angle Θ, the selector 16B
During which the rise of the symbol clock CLK _SYB, the modulation scheme of the received signal demodulating circuit 1B are demodulated, from the phase error table corresponding to the reception signal phase rotation angle theta, I, Q symbol stream data I (8 ), Q
The phase error data Δφ (8) corresponding to (8) is read out and output to the D / A converter 17, while the symbol clock C
While the LK _SYB falls, the phase error data Δφ corresponding to the I and Q symbol stream data I (8) and Q (8) is obtained from the phase error table for QPSK 14-1.
(3) is read out and output to the reception signal phase rotation angle detection circuit 8B.

Reference numeral 90 denotes a delay circuit,
B outputs the phase error data Δφ (3) read out with a predetermined time delay. In the delay circuit 90, the frame synchronization detecting / reproducing circuit 2 uses the I and Q symbol stream data I
(8), When the frame synchronization signal is captured from Q (8) and the output of the reproduction frame synchronization signal is started, I, Q
Phase error data Δφ corresponding to the first part of the frame synchronization signal of symbol stream data I (8), Q (8)
(3) is output. Reference numeral 91 denotes a delay circuit, which outputs the sign bit data q (1), which is the MSB of the Q symbol stream, with a predetermined delay. When the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal from the I and Q symbol stream data I (8) and Q (8) and starts outputting the reproduction frame synchronization signal, the delay circuit 91 outputs Q Symbol stream data Q
The code bit data q (1) of the first part of the frame synchronization signal in (8) is output.

Reference numeral 99 denotes a delay circuit which outputs the sign bit data i (1), which is the MSB of the I symbol stream data I (8), with a predetermined delay. When the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal from the I and Q symbol stream data I (8) and Q (8) and starts outputting the reproduction frame synchronization signal, the delay circuit 99 outputs the I signal. Code bit data i of the first part of the frame synchronization signal of symbol stream data I (8)
(1) is output.

Reference numeral 92B denotes a phase rotation angle discriminating circuit, which outputs I and Q from the demodulation circuit 1B from the portion corresponding to the frame synchronization signal output from the delay circuits 90, 91 and 99.
Among the symbol streams I (8) and Q (8), the phase rotation angle with respect to the transmitting side is determined for the symbol portion corresponding to the bit (1) of the frame synchronization signal, and the symbol portion corresponds to the bit (0) of the frame synchronization signal. The phase rotation angle with respect to the transmitting side is determined for the symbol portion to be changed, and the determination result is sequentially output. Of the phase rotation angle determination circuit 92B, 100 is 3
This is a 3-bit adder that adds bit data (but does not carry to the fourth bit), adds the output of the delay circuit 90 and C (3) = (110), and outputs the lower 2 bits. .

Reference numeral 101 denotes a binary converter which converts 2-bit data obtained by combining the output of the delay circuit 91 as upper bits and the output of 99 as lower bits into a binary code according to FIG. Reference numeral 102 denotes a 4-bit adder for adding 4-bit data (however, the carry to the 5th bit is not performed). The output of the binary converter 101 is input to the upper 2 bits on one input side, and the lower 2 bits. The lower two bits of the addition result of the adder 100 are input to the bits. A selector 103 is provided on the other input side of the adder 102.
Is connected to the selector 103. The selector 103 inputs the bit stream of the reproduced frame synchronization signal output from the frame synchronization detection / reproduction circuit 2, and when the bit (0) portion is input, D (4) = (0001), and when the bit (1) is input, E (4) = (100
1) is output. Adder 102 outputs the upper three bits of the addition result as received signal phase rotation angle signal R (3).

Reference numeral 95 denotes an averaging circuit for averaging the received signal phase rotation angle signal R (3). Here, as an example, the frame synchronization signal is averaged over four frames to obtain the received signal phase rotation angle signal AR (3). ) Is output to the remapper 7 and the selector 16B. The other components are configured exactly the same as in FIG.

Next, the operation of the above embodiment will be described. (1) Start of reception The selector 16B of the carrier recovery circuit 10B determines that the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame after the start of reception, and the reception signal phase rotation angle detection circuit 8B detects the reception signal phase rotation angle. Until the symbol clock CLK
_{During the} rise of _SYB, only the phase error table 13 for 8PSK is enabled, and the phase error table 1
3, phase error data Δφ (8) corresponding to a set of I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit 1B while the symbol clock CLK _SYB rises. D / A converter 17
Output to In parallel with this, while the symbol clock CLK _SYB falls, only the phase error table 14-1 for QPSK is enabled, and the symbol clock CLK _{SYB falls} from the phase error table 14-1. I output from the demodulation circuit 1B while the
Of the phase error data Δφ (8) corresponding to the set data of the Q symbol stream data I (8) and Q (8),
The bit phase error data Δφ (3) is read and output to the delay circuit 90.

The selector 16B reads out the phase error data Δφ (8) from the phase error table 13 for 8PSK.
Output to the A / A converter 17, the demodulation circuit 1B
Are the phases 0, π / 4, 2π / 4, 3π / 4 on the transmitting side,
4π / 4, 5π / 4, 6π / 4, and 7π / 4 signal point arrangements “0” to “7” are respectively converted to digital signals on the receiving side by I
Correction to a position rotated by Θ = m × π / 4 (where m is an arbitrary integer from 0 to 7) on the −Q phase plane.

On the other hand, in the phase error table 14-1, the I and Q symbol stream data I (8), Q
The upper three bits Δφ (3) of the phase error data Δφ (8) corresponding to (8) are the number of bits for determining whether the absolute value of the phase error is larger or smaller than π / 8 (see FIG. 18).
This Δφ (3) and I, Q symbol stream data I
(8), sign bit data i which is the MSB of Q (8)
By combining (1) and q (1) and performing simple arithmetic processing, it is possible to determine which of the eight signal point constellations “0” to “7” the received signal point corresponds to. Since the signal point constellation on the transmitting side of bit (0) (or bit (1)) of the frame synchronization signal is determined to be “0” (or “4”), Δφ (3) and the I and Q symbol streams Data I
(8), code bit data i (1), q (8) of Q (8)
From (1), the received signal phase rotation angle is uniquely determined.

In the received signal phase rotation angle detection circuit 8B, first, the delay circuits 90, 91 and 99 output the phase error data Δφ (3) output from the selector 16B and the demodulation circuit 1
Q symbol stream data Q extracted from the output of B
The code bit data q (1) of (8) and the code bit data i (1) of the I symbol stream data I (8) are delayed, and the frame synchronization detection / reproduction circuit 2 performs frame synchronization from the I and Q symbol stream data. When the signal is captured and the output of the reproduced frame synchronization signal is started, the I and Q symbol stream data I (8),
The phase error data Δφ (3) corresponding to the head of the frame synchronization signal portion of Q (8) is output, and the delay circuit 91 corresponds to the head of the frame synchronization signal portion of the Q symbol stream data Q (8). The timing so that the sign bit data q (1) is output and the delay circuit 99 outputs the sign bit data i (1) corresponding to the head of the frame synchronization signal portion of the I symbol stream data I (8). Make a match. After the outputs of the delay circuits 91 and 99 are binary-converted, the adder 1
02 is input as the upper bit of one input. The output of the delay circuit 90 is added to the adder 100 by C (3) = (11
0), the lower 2 bits are input as the lower 2 bits of one input of the adder 102.

A short time after the start of reception, the frame synchronization detecting / reproducing circuit 2 outputs the I and Q symbol streams I (8) and Q (Q).
(8) The frame synchronization signal is captured, and a reproduced frame synchronization signal is output. Then, in the bit (0) portion of the reproduced frame synchronization signal, the selector 103 sets D (4) =
(0001) is selected and output, and in the bit (1) portion, E (4) = (1001) is selected and output. The adder 102 performs an addition operation on one input and the other input at each bit position of the 20-bit reproduced frame synchronization signal, and outputs the upper 3 bits. Then, the adder 102 outputs the received signal phase rotation angle Θ as shown in FIG.
0, π / 4, 2π / 4, 3π / 4, 4π / 4, 5π /
Divided into 4, 6π / 4, 7π / 4, R = 0 in decimal notation
7, a received signal phase rotation angle signal R (3) expressing R as a 3-bit natural binary number is output (FIG. 2).
(See (2)).

The averaging circuit 95 takes in the output of the adder 102 while the frame synchronization signal section signal is being input from the frame synchronization detection / reproduction circuit 2 and averages it over four frames in the same manner as in FIG. , And outputs the result to the remapper 7 as the received signal phase rotation angle signal AR (3), thereby performing absolute phase conversion. Also, the received signal phase rotation angle signal AR
(3) is also output to the selector 16B.

(2) Normal Receiving Operation As soon as the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal, the transmission configuration identification circuit 9 identifies the multiplex configuration and the current I and Q output from the demodulation circuit 1B. A modulation scheme identification signal DM indicating which modulation scheme part the symbol streams I (8) and Q (8) is output to the selector 16B and the like.

The selector 16B, to which the received signal phase rotation angle signal AR (3) is input from the averaging circuit 95, uses the modulation scheme identification signal DM input from the transmission configuration identification circuit 9 to generate, for example, the signal AR (3). When the received signal phase rotation angle ２ is 2π / 4, the symbol clock CLK is used during the period when the demodulation circuit 10B is demodulating the 8PSK modulation scheme.
_{While SYB} is rising, only the phase error table 13 is enabled, and from the phase error table 13, I,
The phase error data Δφ (8) corresponding to the Q symbol stream data I (8), Q (8) is read and output to the D / A converter 17. As a result, regardless of the phase variation of the received carrier, the signal point arrangements “0”, “1”,
8 for “2”, “3”, “4”, “5”, “6”, “7”
The PSK-mapped digital signal (abc) is
The signal point arrangements “2”, “3”, “4”,
The phases of the reference carriers f _C1 and f _C2 are corrected so that they appear in “5”, “6”, “7”, “0”, and “1”. Since the I and Q symbol stream data I (8) and Q (8) of the 8PSK modulation scheme output from the demodulation circuit 1B are rotated by η = −Θ = −2π / 4 by the remapper 7, the remapper 7 The received signal points of the I and Q symbol stream data I '(8) and Q' (8) output from the transmitting side coincide with the transmitting side.

When Θ is 2π / 4, the demodulation circuit 1B
During the demodulation of the SK modulation scheme, only the phase error table 14-1 is enabled while the symbol clock CLK _SYB rises, and the I and Q symbol stream data I and Q are output from the phase error table 14-1.
(8), phase error data Δφ (8) corresponding to Q (8)
And outputs it to the D / A converter 17. As a result,
A digital signal (de) QPSK-mapped to signal point arrangements “1”, “3”, “5”, and “7” on the transmission side is:
The signal point arrangements “3”, “5”, “7”,
Since the phases of the reference carriers f _C1 and f _C2 are corrected so as to appear as “1”, the same phase rotation angle as the reception signal phase rotation angle at 8PSK is maintained. The I and Q symbol stream data I (8) and Q (8) of the QPSK modulation scheme output from the demodulation circuit 1B are also converted by the remapper 7 into η = −Θ =
Since the phase is rotated by −2π / 4, the I and Q symbol stream data I ′ (8) output from the remapper 7 are
The reception signal point of Q ′ (8) matches the transmission side.

When Θ is 2π / 4, the demodulation circuit 1B
During the demodulation of the SK modulation scheme, the selector 16B enables only the phase error table 15-3 while the symbol clock CLK _SYB rises, and _outputs the I and Q symbols from the phase error table 15-3. The phase error data Δφ (8) corresponding to the stream data I (8), Q (8) is read and output to the D / A converter 17. As a result, the signal point arrangement “0”, “4” on the transmission side
The digital signal (f) mapped to BPSK is
Since the phases of the reference carriers f _C1 and f _C2 are corrected so as to appear in the signal point arrangements “2” and “6” on the receiving side, respectively, 8
It is kept at the same phase rotation angle as the reception signal phase rotation angle in PSK. I and Q symbol stream data I (8), Q of the BPSK modulation scheme output from demodulation circuit 1B
(8) is also rotated by η = −Θ = −2π / 4 by the remapper 7, so that the I and Q output from the remapper 7 are
The reception signal points of the symbol stream data I '(8) and Q' (8) coincide with the transmission side.

Note that the selector 16B also operates during the normal reception operation.
While the symbol clock CLK _SYB is falling
Only the phase error table 14-1 is enabled, and the symbol clock CLK
I and Q symbol stream data I (8) and Q (8) output from demodulation circuit 1B while _SYB is falling
Is read out and output to the delay circuit 90. The phase rotation angle determination circuit 92B determines the phase rotation angle based on the outputs of the delay circuits 90, 91, and 99, outputs the determination result in the form of a received signal phase rotation angle signal R (3), and outputs an averaging circuit 95. Are averaged for four frames and output as a received signal phase rotation angle signal AR (3). If the received signal phase rotation angle の indicated by AR (3) is the same as before, the phase rotation angle of the remapper 7 does not change, and the phase error table selected by the selector 16B does not change. If the angle Θ changes, the remapper 7 rotates by −Θ with respect to the new Θ. The selector 16B changes the selected phase error table in accordance with the change of Θ.

For example, during the period when the demodulation circuit 1B is demodulating the 8PSK modulation scheme, the symbol clock CL is used.
While K _SYB is rising, 8 regardless of the value of ８
Only the phase error table 13 for the PSK modulation method is enabled, and the phase error data Δφ (8) is read from the phase error table 13, but during the period when the demodulation circuit 1B is demodulating the QPSK modulation method part, the symbol clock While CLK _SYB is rising, Θ = 0, 2π / 4,
In the case of 4π / 4 and 6π / 4, the phase error table 14-1
Is enabled, the phase error data Δφ (8) is read from the phase error table 14-1, and Θ = π / 4,
In the case of 3π / 4, 5π / 4, 7π / 4, only the phase error table 14-2 is enabled, and the phase error data Δφ (8) is read from the phase error table 14-2. During the period when the demodulation circuit 1B is performing demodulation of the BPSK modulation method portion, while the symbol clock CLK _SYB is rising, if Θ = 0, 4π / 4, the phase error table 15
-1 is enabled and the phase error table 15-
The phase error data Δφ (8) is read from 1 and Θ = π /
In the case of 4, 5π / 4, only the phase error table 15-2 is enabled, the phase error data Δφ (8) is read from the phase error table 15-2, and Θ = 2π / 4, 6π
/ 4, only the phase error table 15-3 is enabled, the phase error data Δφ (8) is read from the phase error table 15-3, and if Θ = 3π / 4, 7π / 4, the phase error table 15-3 is enabled. -4 only enabled,
The phase error data Δφ is obtained from the phase error table 15-4.
Read (8).

According to this embodiment, the QP corresponding to the I and Q symbol stream data in the portion corresponding to bit (1) (bit (0)) of the demodulated frame synchronization signal
Of the phase error data according to the SK modulation phase error table 14-1, upper 3 bits for determining whether the absolute value of the phase error is larger or smaller than π / 8, and I, Q symbol stream data I (8), Q (8) sign bit data i
From (1) and q (1), the phase rotation angles of the I and Q symbol stream data I (8) and Q (8) corresponding to bit (1) (bit (0)) of the frame synchronization signal are obtained. Since the determination is made, the phase rotation angle of the received signal can be determined by a simple calculation. Therefore, it is not necessary to use a dedicated large-scale ROM for determining the phase rotation angle, and the circuit scale can be reduced.

In the above embodiment, the phase error data Δφ (3) is read from the phase error table 14-1. However, the phase error data Δφ (3) is read from the phase error table 14-2. You may do it. This change can be made by appropriately changing C (3) added by the adder 100 and D (4) and E (4) selected by the selector 103. Further, the phase rotation angle is determined for both the bit (1) and the bit (0) of the frame synchronization signal in the I and Q symbol stream data I (8) and Q (8). You may do it. Also,
Various changes can be made in the averaging method. For example, averaging may be performed for one frame or two frames, or one bit or a plurality of bits at a specific position of the frame synchronization signal may be averaged over a plurality of frames. May be.

Next, a third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a block diagram of a main part of a PSK modulated wave receiver according to the present invention, and the same components as those in FIG. 1 are denoted by the same reference numerals. In the embodiment shown in FIG. 1, the phase error tables 13, 14-
1, 14-2, and 15-1 to 15-4, and I and Q symbol stream data I (8) and Q (8) output from the demodulation circuit are input. 7, the phase error tables 13, 14-1, 15
−1, and the I and Q symbol stream data I ′ output from the remapper 7.
(8), Q '(8) is input. In addition,
Until the reception signal phase rotation angle detection circuit detects the reception signal phase rotation angle, the remapper 7 outputs the I and Q symbol stream data I (8), Q output from the demodulation circuit 1C.
The input data is output as it is without performing the phase rotation for (8).

The selector 16C of the carrier recovery circuit 10C
After the start of reception, the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame, and the reception signal phase rotation angle detection circuit 8C
While BUSY until detects the reception signal phase rotation angle, while the rise of the symbol clock CLK _SYB, only the phase error table 13 for 8PSK and enable, from the phase error table 13, the rise of the symbol clock CLK _SYB And the phase error data Δφ (8) corresponding to the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 and read from the D / A converter 1
7 is output. In parallel with this, while the symbol clock CLK _SYB falls, only the phase error table 15-1 for BPSK is enabled, and the symbol clock CLK _{SYB is output} from the phase error table 15-1.
I output from the remapper 7 while falling,
From the phase error data Δφ (8) corresponding to the Q symbol stream data I ′ (8) and Q ′ (8), the upper 3 bits (referred to as phase error data Δφ (3)) are read out, and the received signal phase Delay circuit 9 of rotation angle detection circuit 8C
Output to 0. From the phase error data Δφ (3), the absolute value of the phase error is (π / 8) + s · (π / 8) (s is 0,
1, 2) It is clear whether it is larger or smaller.

After the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame and the reception signal phase rotation angle detection circuit 8C detects the reception signal phase rotation angle Θ, while the symbol clock CLK _SYB rises, Only one of the phase error tables 13 or 14-1 or 15-1 corresponding to the modulation scheme of the received signal demodulated by the demodulation circuit 1C is enabled, and the remapper 7 is _activated while the symbol clock CLK _SYB rises. , The phase error data Δφ (8) corresponding to the I and Q symbol stream data I ′ (8) and Q ′ (8) output to the D / A converter 17, while the symbol clock CLK _{SYB rises.} During the fall, only the phase error table 15-1 for BPSK is enabled, and the symbol clock CLK is output from the phase error table 15-1. _Among the phase error data Δφ (8) corresponding to the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 during the fall of _SYB, the phase error of the upper 3 bits Data Δφ
(3) is read out and output to the delay circuit 90.

Reference numeral 90 denotes a delay circuit.
The phase error data Δφ (3) read by C is output after a predetermined time delay. The delay circuit 90 captures a frame synchronization signal from the I and Q symbol stream data I '(8) and Q' (8) output from the remapper 7 by the frame synchronization detection / reproduction circuit 2, and outputs a reproduction frame synchronization signal. , The phase error data Δφ (3) corresponding to the first part of the frame synchronization signal of the I and Q symbol stream data I ′ (8) and Q ′ (8) is output. Reference numeral 91 denotes a delay circuit, which outputs the sign bit data q '(1), which is the MSB of the Q symbol stream data Q' (8), with a predetermined delay. When the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal from the I and Q symbol stream data I '(8) and Q' (8) and starts outputting the reproduction frame synchronization signal, the delay circuit 91 , Q symbol stream data Q ′
The code bit data q '(1) of the first part of the frame synchronization signal in (8) is output.

Reference numeral 92 denotes a phase rotation angle discrimination circuit, which outputs I and Q symbol streams I '(8) and Q' (Q) output from the remapper 7 from a portion corresponding to the frame synchronization signal output from the delay circuits 90 and 91. 8), the phase rotation angle with respect to the transmission side is determined for the symbol portion corresponding to bit (1) of the frame synchronization signal, and the phase rotation angle with respect to the transmission side is determined for the symbol portion corresponding to bit (0) of the frame synchronization signal. The angle is determined, and the determination result is sequentially output as a received signal phase rotation angle signal R (3).

Reference numeral 95 denotes an averaging circuit for averaging the received signal phase rotation angle signal R (3). Here, as an example, the frame synchronization signal is averaged over four frames to obtain the received signal phase rotation angle signal AR (3). ). 110
The averaging circuit 95 determines whether the received signal phase rotation angle signal AR (3)
Is output, the previous received signal phase rotation angle signal OR (3) held in the register 111 is added to the current received signal phase rotation angle signal AR (3), and the result is added to the new received signal phase rotation angle. It is a 3-bit adder that outputs the signal OR (3) to the remapper 7, the selector 16C, etc.
No carry to the bit). 111 is an adder 11
This register holds the received signal phase rotation angle signal OR (3) output as 0. The functions of the adder 110 and the register 111 will be described later. The other components are configured exactly the same as in FIG.

Next, the operation of the above embodiment will be described. It is assumed that the register 111 has been cleared to (000) in advance. (1) Start of reception At the start of reception, the remapper 7 does not rotate the phase, and the demodulation circuit 1
I and Q symbol streams I (8), Q input from C
(8) is directly output as I '(8) and Q' (8). The selector 16C of the carrier recovery circuit 10C keeps the symbol until the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame after the start of reception and the reception signal phase rotation angle detection circuit 8C detects the reception signal phase rotation angle. Clock CLK
_{While the SYB} is rising, only the phase error table 13 for 8PSK is enabled. From the phase error table 13, the I and Q symbol stream data output from the remapper 7 while the symbol clock CLK _SYB rises. The phase error data Δφ (8) corresponding to I ′ (8) and Q ′ (8) is read out, and the D / A converter 17
Output to In parallel with this, while the symbol clock CLK _SYB falls, only the BPSK phase error table 15-1 is enabled, and the symbol clock CLK _{SYB falls} from the phase error table 15-1. I and Q symbol stream data I '(8), Q' output from the remapper 7 while the
Of the phase error data Δφ (8) corresponding to (8), phase error data Δφ (3) of the upper 3 bits is read out and output to the delay circuit 90.

The selector 16C reads out the phase error data Δφ (8) from the phase error table 13 for 8PSK,
By outputting to the D / A converter 17, the demodulation circuit 1C
Are the phases 0, π / 4, 2π / 4, 3π / 4 on the transmitting side,
4π / 4, 5π / 4, 6π / 4, and 7π / 4 signal point arrangements “0” to “7” are respectively converted to digital signals on the receiving side by I
Correction to a position rotated by Θ = m × π / 4 (where m is an arbitrary integer from 0 to 7) on the −Q phase plane.

On the other hand, in the phase error table 15-1, the I and Q symbol stream data I '(8), Q'
The upper three bits Δφ (3) of the phase error data Δφ (8) corresponding to (8) have an absolute value of the phase error of (π / 8) +
This is the number of bits for determining whether it is larger or smaller than s · (π / 8) (s is 0, 1, 2). This phase error data Δφ
(3) and MS of Q symbol stream data Q '(8)
B is combined with the sign bit data q ′ (1),
By performing simple arithmetic processing, it is possible to determine which of the eight signal constellations “0” to “7” the received signal point viewed on the output side of the remapper 7 corresponds to. Bit (0) of frame synchronization signal
(Or bit (1)), the signal arrangement on the transmitting side is determined to be "0" (or "4"). The phase rotation angle of the received signal viewed from the side is uniquely determined.

In the received signal phase rotation angle detection circuit 8C, first, the delay circuits 90 and 91 output the phase error data Δφ (3) output from the selector 16C and the Q symbol stream data Q ′ ( 8)
, The frame synchronization detection / reproduction circuit 2 captures a frame synchronization signal from the I and Q symbol stream data I ′ (8) and Q ′ (8), and When the signal output starts, the delay circuit 90 outputs the I and Q symbol stream data I ′.
(8) The phase error data Δφ (3) corresponding to the head of the frame synchronization signal portion of Q ′ (8) is output, and the delay circuit 91 outputs the frame synchronization signal of Q symbol stream data Q ′ (8). The timing is adjusted so that the code bit data q '(1) corresponding to the head of the part is output. The outputs of the delay circuits 91 and 90 are input as upper bits and lower bits on one input side of the adder 93.

A short time after the start of reception, the frame synchronization detecting / reproducing circuit 2 outputs the I and Q symbol streams I '(8),
The frame synchronization signal of Q '(8) is captured, and a reproduced frame synchronization signal is output. Then, the selector 94 determines that A (4) = A (4) = bit (0) of the reproduced frame synchronization signal.
(0001) is selected and output, and in the part of bit (1), B (4) = (1001) is selected and output. The adder 93 performs an addition operation of one input and the other input at each bit position of the 20-bit reproduced frame synchronization signal,
Outputs the upper 3 bits. Then, from the adder 93,
FIG. 2 shows the received signal phase rotation angle た viewed from the output side of the remapper 7.
As shown in (1), 0, π / 4, 2π / 4, 3π / 4,
4π / 4, 5π / 4, 6π / 4, 7π / 4
A received signal phase rotation angle signal R (3) in which R is represented by a 3-bit natural binary number in correspondence with R = 0 to 7 in hexadecimal notation is output (see FIG. 2 (2)).

The averaging circuit 95 takes in the output of the adder 93 while the frame synchronization signal section signal is being input from the frame synchronization detection / reproduction circuit 2, and averages the data over four frames as in the case of FIG. , And outputs the result as a reception signal phase rotation angle signal AR (3). AR (3) is added to the value held in the register 111 by the adder 110, but since the held value is (000) at first, the received signal for the transmitting side when AR (3) is viewed as it is at the output point of the demodulation circuit 1C. The signal is output to the remapper 7 as the phase rotation angle signal OR (3), and is output to the register 111 and held. For example, O
If the received signal phase rotation angle の indicated by R (3) is 3π / 4, the remapper 7 rotates the phase by −3π / 4 to perform absoluteization. The register 111 holds (011).

(2) Normal Reception Operation As soon as the frame synchronization detection / reproduction circuit 2 captures the frame synchronization signal, the transmission configuration identification circuit 9 identifies the multiplex configuration and the current I, Q output from the demodulation circuit 1C. A modulation scheme identification signal DM indicating which modulation scheme part the symbol streams I (8) and Q (8) is output to the selector 16C and the like.

When the received signal phase rotation angle signal OR (3) is output from the adder 110 and the absolute phase is converted by the remapper 7, the selector 16C outputs the modulation scheme identification signal DM input from the transmission configuration identification circuit 9 to the selector 16C. Using the demodulation circuit 1C
During the demodulation of the 8PSK modulation method, only the phase error table 13 is enabled while the symbol clock CLK _SYB is rising, and the I and Q symbol stream data I '
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read and output to the D / A converter 17. As a result, considering that I ′ (8) and Q ′ (8) are rotated by η = −Θ = −3π / 4 compared to I (8) and Q (8), Signal point arrangement “0”, “1”,
8 for “2”, “3”, “4”, “5”, “6”, “7”
The received signal points of the PSK-mapped digital signal (abc) are signal point arrangements “3”, “4”, “5”,
The phases of the reference carriers f _C1 and f _C2 are corrected so as to appear in “6”, “7”, “0”, “1”, and “2”. At this time, the I and Q symbol stream data I (8) and Q (8) of the 8PSK modulation scheme output from the demodulation circuit 1C.
Has been rotated by η = −Θ = −3π / 4 by the remapper 7 to be absolutely phased, so that the I and Q symbol stream data I ′ (8) output from the remapper 7
The reception signal point of Q ′ (8) matches the transmission side.

During the period when the demodulation circuit 1C is performing demodulation of the QPSK modulation system, the selector 16A enables only the phase error table 14-1 while the symbol clock CLK _SYB is rising, and the phase error table 14- 1 to I, Q symbol stream data I '
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read and output to the D / A converter 17. As a result, I ′ (8) and Q ′ (8) become I (8) and Q (8)
Considering that the phase is rotated by η = −Θ = −3π / 4 as compared with, the signal point constellations “1”, “3”,
The digital signals (de) QPSK-mapped to “5” and “7” appear at signal point constellations “4”, “6”, “0”, and “2” when viewed at the input of the remapper 7, respectively. Since the phases of the reference carriers f _C1 and f _C2 are corrected, 8PSK
At the same phase rotation angle as the reception signal phase rotation angle の. I and Q symbol stream data I (8), Q (8) of the QPSK modulation scheme output from demodulation circuit 1C
Is rotated by −Θ = −3π / 4 by the remapper 7, so that the received signal points of the I and Q symbol stream data I ′ (8) and Q ′ (8) output from the remapper 7 are Matches.

During the period in which the demodulation circuit 1C is demodulating the BPSK modulation portion, the selector 16A enables only the phase error table 15-1 while the symbol clock CLK _SYB rises, 1 to I, Q symbol stream data I '
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read and output to the D / A converter 17. As a result, I ′ (8) and Q ′ (8) become I (8) and Q (8).
Considering that the phase is rotated by −Θ = −3π / 4 in comparison with
The phases of the reference carriers f _C1 and f _C2 are corrected so that the K-mapped digital signal (f) appears at the signal point arrangements “3” and “7” when viewed at the input side of the remapper 7, respectively. It is kept at the same phase rotation angle as the reception signal phase rotation angle の at 8PSK. BPSK output from demodulation circuit 1C
I, Q symbol stream data I of modulation scheme part
(8), Q (8) is determined by the remapper 7 as η = −Θ = −3.
Since the phase is rotated by π / 4, the I and Q symbol stream data I ′ (8), Q ′ output from the remapper 7 are output.
The reception signal point of (8) coincides with the transmission side.

It should be noted that also during the normal reception operation, the selector 16C
While the symbol clock CLK _SYB is falling
Only the phase error table 15-1 is enabled, and the symbol clock CLK
I and Q symbol stream data I (8) ', Q (8) output from remapper 7 while _SYB is falling
'And reads out the phase error data Δφ (3) corresponding to'. Then, the phase rotation angle determination circuit 92 determines the phase rotation angle based on the outputs of the delay circuits 90 and 91, and outputs the determination result as the received signal phase rotation angle signal R.
The signal is output in the form of (3), and the averaging circuit 95 averages the data for four frames and outputs the result as the received signal phase rotation angle signal AR (3).

When the phase rotation angle discriminating circuit 92 and the averaging circuit 95 of the reception signal phase rotation angle detection circuit 8C detect the second phase rotation angle and output the reception signal phase rotation angle signal AR (3), The received signal phase rotation angle signal AR (3) indicates the phase rotation angle with respect to the transmission side as seen from I '(8) and Q' (8) after the absolute phase conversion by the remapper 7. Therefore, the previous received signal phase rotation angle signal O held in the register 111
By adding the received signal phase rotation angle signal OR (3) to the transmission side as viewed from the input side of the remapper 7 by adding the signal R (3), the reception signal phase rotation angle signal OR (3) is output to the remapper 7. To perform the second phase rotation (OR (3)
If the received signal phase rotation angle indicated by is Θ, the phase is rotated by −Θ), and the register 110 holds the phase rotation angle. Hereinafter, the same processing is repeated each time the phase rotation angle determination circuit 92 and the averaging circuit 95 of the reception signal phase rotation angle detection circuit 8C detect a new phase rotation angle.

According to this embodiment, the I and Q symbol stream data I '(8), Q' after the absolute phase conversion by the remapper 7 are stored in the phase error table of the carrier recovery circuit 10C.
Since (8) is input, during normal reception, regardless of the value of the received signal phase rotation angle, the I and Q symbol stream data I 'input to the phase error table are output.
(8), the reception signal point of Q '(8) becomes the same as that of the transmission side. Therefore, only one phase error table is provided for the carrier recovery circuit 10C for each modulation method, and the number of phase error tables provided for the carrier recovery circuit 10C can be reduced, and the circuit configuration can be greatly simplified. FIG.
In the embodiment, the Q symbol stream data Q ′
The code bit data q ′ (1) of (8) is used, but the MSB of the I symbol stream data I ′ (8) is used instead.
May be used.

FIG. 7 can be modified as shown in FIG. That is, the carrier recovery circuit 1 of the demodulation circuit 1D of FIG.
0D is 3 of the phase error tables 13, 14-1, and 15-1.
The selector 16D includes a symbol clock CLK
_{While SYB} is falling, the phase error table 14-1
To I, Q symbol stream data I '(8), Q'
The phase error data Δφ (3) corresponding to (8) is read. The reception signal phase rotation angle detection circuit 8D
The delay circuits 90 and 91 and the phase rotation angle determination circuit 92 of the reception signal phase rotation angle detection circuit 8C in FIG.
Are replaced by delay circuits 90, 91, 99 and a phase rotation angle discrimination circuit 92B. The selector 16D outputs the phase error data Δ read from the phase error table 14-1 while the symbol clock CLK _SYB falls.
φ (3) is input to the delay circuit 90. Also, the Q symbol stream data Q ′ output from the remapper 7
The MSB of (8) is input to the delay circuit 91, and the I symbol stream data I 'output from the remapper 7 is output.
The MSB of (8) is input to the delay circuit 99, and FIG.
As in the case of the above, the phase error table for QPSK 14-
1 and the phase error data Δφ (3)
From the sign bit data i '(1) and q' (1) of the symbol stream data I '(8) and Q' (8), delay circuits 90, 91 and 99, a phase rotation angle discriminating circuit 92B, and an averaging circuit 95 Thus, the phase rotation angle with respect to the transmitting side as seen from the output side of the remapper 7 can be detected, and the adder 11
From 0, it is possible to output the reception signal phase rotation angle signal OR (3) to the transmission side as seen from the input side of the rimmer 7.

FIG. 7 can be modified as shown in FIG. In FIG. 9, the reception signal phase rotation angle detection circuit 8C in FIG. 7 is replaced with the reception signal phase rotation angle detection circuit 8A in FIG. The demodulation circuit 1C shown in FIG.
E, the phase error tables 13, 1
4-1 and 15-1 I and Q symbol stream data I
A selector 19 is provided on the input side of '(8) and Q' (8), and I and Q symbol stream data I '(8) output from the remapper 7 while the symbol clock CLK _SYB is rising. Q ′ (8) is input to each of the phase error tables 13, 14-1, and 15-1, and I and Q symbol stream data I output from the demodulation circuit 1 E while the symbol clock CLK _SYB falls.
(8) and Q (8) are converted into phase error tables 13 and 14−
1, 15-1.

After the start of the reception, the selector 16C of the carrier recovery circuit 10C determines that the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame, and the reception signal phase rotation angle detection circuit 8A detects the reception signal phase rotation angle. Until the symbol clock CLK _SYB rises, 8PSK
Of the symbol clock CLK _SYB from the phase error table 13.
While the I and Q symbol stream data I 'input from the remapper 7 through the selector 19
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read out and output to the D / A converter 17. Also,
In parallel with this, while the symbol clock CLK _SYB falls, the phase error table 15-1 for BPSK is used.
From the phase error table 15-1, corresponding to the I and Q symbol stream data I (8) and Q (8) input via the selector 19 while the symbol clock CLK _SYB is falling. Out of the phase error data Δφ (8)
φ (3) is read and output to the delay circuit 90.

On the other hand, the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame, and the reception signal phase rotation angle detection circuit 8
After A detects the received signal phase rotation angle Θ, while the symbol clock CLK _SYB rises, the phase error table 13 or 14-1 or 15-1 of the received signal demodulated by the demodulation circuit 1E in the phase error table 13 or 14-1 or 15-1. Only one phase error table corresponding to the modulation method is enabled, and the selector 19 is _activated while the symbol clock CLK _SYB rises.
, The phase error data Δφ (8) corresponding to the I and Q symbol stream data I ′ (8) and Q ′ (8) input from the remapper 7 and output to the D / A converter 17, While the clock CLK _SYB is falling, only the phase error table 15-1 for BPSK is enabled, and input from the phase error table 15-1 via the selector 19 while the symbol clock CLK _SYB is falling. Phase error data Δ corresponding to the obtained I and Q symbol stream data I (8) and Q (8)
of φ (8), phase error data Δφ of upper 3 bits
(3) is read. If you do this,
From the averaging circuit 95, as in the case of FIG.
Can output the received signal phase rotation angle signal AR (3) to the transmission side as viewed from the input side of FIG.

The configuration shown in FIG. 8 can be modified as shown in FIG. 10, the received signal phase rotation angle detection circuit 8D in FIG. 8 is replaced by the received signal phase rotation angle detection circuit 8B in FIG. The demodulation circuit 1D of FIG.
F, the phase error tables 13, 1
4-1 and 15-1 I and Q symbol stream data I
A selector 19 is provided on the input side of '(8) and Q' (8), and I and Q symbol stream data I '(8) output from the remapper 7 while the symbol clock CLK _SYB is rising. Q ′ (8) is input to each of the phase error tables 13, 14-1, and 15-1, and I and Q symbol stream data I output from the demodulation circuit 1F while the symbol clock CLK _SYB falls.
(8) and Q (8) are converted into phase error tables 13 and 14−
1, 15-1.

After the start of the reception, the selector 16D of the carrier recovery circuit 10D determines that the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame, and the reception signal phase rotation angle detection circuit 8B detects the reception signal phase rotation angle. Until the symbol clock CLK _SYB rises, 8PSK
Of the symbol clock CLK _SYB from the phase error table 13.
While the I and Q symbol stream data I 'input from the remapper 7 through the selector 19
(8), phase error data Δφ corresponding to Q ′ (8)
(8) is read out and output to the D / A converter 17. Also,
In parallel with this, while the symbol clock CLK _SYB falls, the phase error table 14-1 for QPSK is used.
From the phase error table 14-1, corresponding to the I and Q symbol stream data I (8) and Q (8) input via the selector 19 while the symbol clock CLK _SYB is falling. Out of the phase error data Δφ (8)
φ (3) is read and output to the delay circuit 90.

On the other hand, the transmission configuration identification circuit 9 identifies the multiplex configuration of the frame, and the reception signal phase rotation angle detection circuit 8
After B detects the received signal phase rotation angle Θ, the selector 1
6D is the phase error table 13 or 14-1 or 15- while the symbol clock CLK _SYB is rising.
1, only one phase error table corresponding to the modulation scheme of the received signal demodulated by the demodulation circuit 1F is enabled, and is input from the remapper 7 via the selector 19 while the symbol clock CLK _SYB is rising. I, Q symbol stream data I '(8), Q'
The phase error data Δφ (8) corresponding to (8) is read out and output to the D / A converter 17, while the symbol clock C
While the LK _SYB is falling, only the QPSK phase error table 14-1 is enabled. From the phase error table 14-1, the _signal is input via the selector 19 while the symbol clock CLK _SYB is falling. Among the phase error data Δφ (8) corresponding to the I and Q symbol stream data I (8) and Q (8), the phase error data Δφ (3) of the upper 3 bits is read. In this manner, the averaging circuit 95 can output the reception signal phase rotation angle signal AR (3) to the transmission side as seen from the input side of the remapper 7 as in the case of FIG. 8, the adder 110 and the register 111 can be omitted.

In each of the above-described embodiments and modifications, after reception is started, the multiplex configuration is identified by the transmission configuration identification circuit, and the reception signal phase rotation angle detection circuit detects the reception signal phase rotation angle. In the meantime, the selector of the carrier recovery circuit outputs the phase error data read from the phase error table for 8PSK to the D / A converter. A value may be output.

In each of the above-described embodiments and modifications, in addition to the BPSK-modulated frame synchronization signal,
A PSK modulated signal (PSK) in which digital signals by three modulation schemes of SK, QPSK and BPSK are time-multiplexed.
(Modulated wave), but a frame synchronization signal modulated by BPSK, a digital signal modulated by 8PSK and Q
The present invention is similarly applicable to the case of receiving and demodulating a PSK modulated signal in which any one or two of a PSK-modulated digital signal and a BPSK-modulated digital signal are time-multiplexed. May be prepared according to the multiplexed modulation method. For example, B
If the PSK-modulated frame synchronization signal and the 8PSK-modulated digital signal are time-multiplexed PSK-modulated signals, BPSK-modulation and 8PSK-modulation may be prepared. QP
PSK with time-multiplexed SK-modulated digital signal
For a signal to be modulated, BPSK modulation and QPSK modulation may be prepared. Also, a BPSK-modulated frame synchronization signal, an 8PSK-modulated digital signal and Q
PS with time-multiplexed PSK-modulated digital signal
For a K modulated signal, BPSK modulation, 8PSK modulation, and QPSK modulation may be prepared. A BPSK-modulated frame synchronization signal, a QPSK-modulated digital signal, and a BPSK-modulated digital signal For a multiplexed PSK modulated signal, BPSK modulation and QPSK modulation may be prepared). Further, the present invention can be similarly applied to a case where the demodulation circuit performs the demodulation operation by the quasi-synchronous detection instead of the demodulation operation by the synchronous detection.

[0122]

According to the present invention, the phase rotation angle of the received signal is determined by the upper bits of the phase error data according to the phase error table for BPSK (QPSK) modulation corresponding to the demodulated I and Q symbol stream data and the frame. It is uniquely determined by the sign bit data of the Q or I (Q and I) symbol stream data corresponding to bit (0) (or bit (1)) of the synchronization signal, and the received signal phase rotation angle can be determined by a simple operation. Can be determined. Therefore, it is not necessary to use a dedicated large-scale ROM for determining the phase rotation angle, and the circuit scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a relationship between a received signal phase rotation angle signal output from a phase rotation angle discrimination circuit in FIG. 1 and a received signal phase rotation angle.

FIG. 3 is a block diagram illustrating a configuration example of an averaging circuit in FIG. 1;

FIG. 4 is an explanatory diagram showing the correspondence between binary codes and Gray codes.

FIG. 5 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram showing the correspondence between input and output of the binary converter in FIG. 5;

FIG. 7 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a modification of FIG. 7;

FIG. 9 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to another modification of FIG. 7;

FIG. 10 is a block diagram showing a configuration of a main part of a PSK modulated wave receiver according to a modified example of FIG. 8;

FIG. 11 is an explanatory diagram showing an example of a frame configuration in the hierarchical transmission scheme.

FIG. 12 is a block diagram illustrating a configuration around a demodulation circuit of a PSK modulated wave receiver using a conventional hierarchical transmission scheme.

FIG. 13 is an explanatory diagram showing a signal point arrangement in PSK mapping.

FIG. 14 is a block diagram in which a part of the carrier wave recovery circuit in FIG. 12 is omitted.

FIG. 15 is an explanatory diagram of how to measure the phase of a received signal point.

FIG. 16 is an explanatory diagram of how to measure a received signal phase rotation angle.

FIG. 17 is an explanatory diagram of a phase error table for 8PSK.

FIG. 18 is an explanatory diagram of a phase error table for QPSK.

FIG. 19 is an explanatory diagram of a phase error table for QPSK.

FIG. 20 is an explanatory diagram of a phase error table for BPSK.

FIG. 21 is an explanatory diagram of a phase error table for BPSK.

FIG. 22 is an explanatory diagram of a phase error table for BPSK.

FIG. 23 is an explanatory diagram of a phase error table for BPSK.

24 is a block diagram of the synchronization detection / reproduction circuit in FIG.

FIG. 25 is an explanatory diagram for explaining BPSK demapping;

26 is a circuit diagram showing a configuration of a synchronization detection circuit in FIG.

FIG. 27 is a circuit diagram showing a configuration of a BPSK demapper in FIG. 24;

FIG. 28 is a signal point arrangement diagram of a frame synchronization signal before and after passing through a 0 ° / 180 ° phase rotation circuit in FIG. 12;

29 is an explanatory diagram of a reception signal phase rotation angle determination table used by the phase determination circuit in FIG.

[Explanation of symbols]

1A, 1B, 1C, 1D, 1E, 1F Demodulation circuit 2 Frame synchronization detection / reproduction circuit 7 Remapper 8A, 8B, 8C, 8D Received signal phase rotation angle detection circuit 9 Transmission configuration identification circuit 10A, 10B, 10C, 10D Carrier wave reproduction Circuit 11 VCO 12 90 ° phase shifter 13, 14-1, 14-2, 15-1, 15-2, 15
-3, 15-4 Phase error table 16A, 16B, 16C, 16D, 19, 94, 103
Selector 90, 91, 99 Delay circuit 92, 92B Phase rotation angle discriminating circuit 93, 100, 102, 110 Adder 95 Averaging circuit 101 Binary converter 111 Register

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[Procedure amendment]

[Submission date] December 31, 1998

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 6

FIG.

FIG. 3

FIG. 4

FIG. 5

FIG. 16

FIG. 25

FIG. 26

FIG. 7

FIG. 8

FIG. 29

FIG. 9

FIG. 10

FIG. 11

FIG.

FIG. 13

FIG. 14

FIG.

FIG.

FIG.

FIG.

FIG. 28

FIG. 21

FIG.

FIG. 23

FIG. 24

FIG. 27

Claims (4)

[Claims] 1. A BPSK-modulated frame synchronization signal, an 8PSK-modulated digital signal, a QPSK-modulated digital signal, and at least an 8PSK-modulated digital signal of the BPSK-modulated digital signal are time-multiplexed. A demodulating means for demodulating the PSK modulated signal using the carrier reproduced by the carrier reproducing means and outputting I and Q symbol stream data, and a frame for acquiring a frame synchronization signal from the demodulated I and Q symbol stream data A synchronization signal acquisition unit, a reception signal phase rotation angle detection unit that detects a phase rotation angle of the I and Q symbol stream data output from the demodulation unit with respect to the transmission side, and an I / Q symbol stream data output from the demodulation unit. The phase is adjusted by the phase rotation angle detected by the received signal phase rotation angle detection means. A carrier recovery means of the demodulation means, wherein the carrier error recovery means of the demodulation means stores carrier phase error data for various demodulated I and Q symbol stream data sets for each modulation method. It has a table and, during normal reception, reads out phase error data corresponding to the demodulated I and Q symbol stream data from the phase error table of the corresponding modulation method while the demodulation means is demodulating a certain modulation method part. In the receiver for correcting the phase of the carrier wave, the reception signal phase rotation angle detection means obtains a phase corresponding to the demodulated I and Q symbol stream data from a phase error table for BPSK modulation of the carrier recovery means. Of the error data, the absolute value of the phase error is (π /
8) A phase error data reading means for reading out upper bits that are known to be larger or smaller than + s · (π / 8) (s is 0, 1, 2), and a frame synchronization among demodulated I and Q symbol stream data. Reading out the sign bit data of the I (or Q) symbol stream data corresponding to the bit (0) (or (1)) of the frame synchronization signal captured by the signal capturing means and the phase error data corresponding to the portion; From the phase error data read by the means, a symbol part corresponding to the bit (0) (or (1)) of the frame synchronization signal in the I and Q symbol stream data output from the demodulation means is transmitted to the transmitting side. Determine the phase rotation angle,
A determination unit that outputs a determination result. 2. A BPSK-modulated frame synchronization signal, at least an 8PSK-modulated digital signal, a QPSK-modulated digital signal, and a BPSK-modulated digital signal. A demodulating means for demodulating the PSK modulated signal in which the signal is time-multiplexed with the carrier reproduced by the carrier reproducing means and outputting I and Q symbol stream data; Frame synchronization signal acquisition means for acquiring a frame synchronization signal, reception signal phase rotation angle detection means for detecting a phase rotation angle of the I and Q symbol stream data output from the demodulation means with respect to the transmitting side, and output from the demodulation means The phase of the I and Q symbol stream data is
Anti-phase rotation means for rotating the phase by an amount corresponding to the phase rotation angle detected by the reception signal phase rotation angle detection means, and outputting the same. And a phase error table storing carrier phase error data for the Q symbol stream data set. During normal reception, while the demodulation means is demodulating a certain modulation scheme part, refer to the phase error table of the corresponding modulation scheme. A receiver for reading out phase error data corresponding to the demodulated I and Q symbol stream data and correcting the phase of the carrier wave, wherein the reception signal phase rotation angle detection means comprises a carrier wave recovery means for QPSK modulation. Of the phase error data corresponding to the demodulated I and Q symbol stream data, the absolute value of the phase error is larger than π / 8. A phase error data reading means for reading out an upper bit which is known to be smaller or smaller; a bit (0) (or (1) of a frame synchronization signal captured by the frame synchronization signal capturing means in the demodulated I and Q symbol stream data; ), The I and Q symbols output from the demodulating means from the sign bit data of the I and Q symbol stream data corresponding to the part and the phase error data read by the phase error data reading means corresponding to the part. Discriminating means for discriminating a phase rotation angle of the symbol portion corresponding to the bit (0) (or (1)) of the frame synchronization signal with respect to the transmitting side in the stream data, and outputting a discrimination result. Signal absolute phase shifter of the receiver. 3. A PSK signal obtained by time-multiplexing a BPSK-modulated frame synchronization signal, an 8PSK-modulated digital signal, a QPSK-modulated digital signal, and at least one digital signal among BPSK-modulated digital signals. Demodulation means for demodulating the modulated signal using the carrier reproduced by the carrier reproduction means and outputting I and Q symbol stream data; and a frame synchronization signal for acquiring a frame synchronization signal from the demodulated I and Q symbol stream data. Capturing means, I output from the demodulating means,
The received signal phase rotation angle detecting means for detecting the phase rotation angle of the Q symbol stream data with respect to the transmitting side, and the phases of the I and Q symbol stream data output from the demodulating means are detected by the received signal phase rotation angle detecting means. An anti-phase rotation means for outputting a phase-rotated anti-phase signal by an amount corresponding to the phase rotation angle. During normal reception, while the demodulation means is demodulating a certain modulation scheme part, it corresponds to the demodulated I, Q symbol stream data from the phase error table of the corresponding modulation scheme. In a receiver configured to read phase error data and correct a phase of a carrier, the reception signal phase rotation angle detection unit may include a carrier re-evaluator. From the phase error table for BPSK modulation means, I after demodulation, of the phase error data corresponding to the Q symbol stream data, the absolute value of the phase error, ([pi /
8) phase error data reading means for reading out upper bits that are known to be larger or smaller than + s · (π / 8) (s is 0, 1, 2); and frame synchronization among demodulated I and Q symbol stream data. Reading out the sign bit data of the I (or Q) symbol stream data corresponding to the bit (0) (or (1)) of the frame synchronization signal captured by the signal capturing means and the phase error data corresponding to the portion; From the phase error data read by the means, the symbol part corresponding to the bit (0) (or (1)) of the frame synchronization signal in the I and Q symbol stream data output from the demodulation means is transmitted to the transmitting side. Determine the phase rotation angle,
A determination unit that outputs a determination result. 4. A time-division multiplexing of a BPSK-modulated frame synchronization signal, an 8PSK-modulated digital signal, a QPSK-modulated digital signal, and at least a QPSK-modulated digital signal of the BPSK-modulated digital signal. A demodulating means for demodulating the PSK modulated signal using the carrier reproduced by the carrier reproducing means and outputting I and Q symbol stream data, and a frame for acquiring a frame synchronization signal from the demodulated I and Q symbol stream data A synchronization signal acquisition unit, a reception signal phase rotation angle detection unit that detects a phase rotation angle of the I and Q symbol stream data output from the demodulation unit with respect to the transmission side, and an I / Q symbol stream data output from the demodulation unit. The phase is adjusted by the phase rotation angle detected by the received signal phase rotation angle detection means. An anti-phase rotation means for outputting an anti-phase rotation, wherein the carrier recovery means of the demodulation means stores carrier phase error data for various demodulated I and Q symbol stream data sets for each modulation method. A phase error table corresponding to the demodulated I and Q symbol stream data by referring to the phase error table of the corresponding modulation scheme while the demodulation means is demodulating a certain modulation scheme during normal reception. In a receiver that reads data and corrects the phase of a carrier wave, the reception signal phase rotation angle detection means converts the phase error table for QPSK modulation of the carrier recovery means into I and Q symbol stream data after demodulation. Phase error data reading for reading out upper bits of the corresponding phase error data that indicate whether the absolute value of the phase error is larger or smaller than π / 8 Output means; and I and Q symbol stream data corresponding to bit (0) (or (1)) of the frame synchronization signal captured by the frame synchronization signal capture means in the demodulated I and Q symbol stream data. Of the I / Q symbol stream data output from the demodulation means, based on the sign bit data of (1) and the phase error data read by the phase error data reading means corresponding to the relevant part. And (1) determining a phase rotation angle of the symbol portion corresponding to the transmitting side with respect to the transmission side, and outputting a determination result.