JPH11317493A - Integrated circuit element mounting structure - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an integrated circuit element mounting structure which is able to minimize thermal stresses to semiconductor elements, having different materials at the mounting of the elements on an identical substrate. SOLUTION: In this integrated circuit element, mounting structure having a plurality of integrated circuit elements 2 and 3 which have different materials mounted in parallel on a substrate 1 having a wiring pattern formed thereon, the different materials of the integrated circuit elements have mutually different thermal conductivities, and a wiring density of the integrated circuit element of the material having a larger thermal conductivity is made higher than the wiring density of the integrated circuit element of the material having a smaller thermal conductivity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of an integrated circuit element, and more particularly, to mounting two or more types of integrated circuit elements having different materials on the same substrate, and having a high reliability and an inexpensive cooling method for each element. Related to a mounting structure capable of realizing

[0002]

2. Description of the Related Art In order to improve the calculation speed of a large computer, not only large-scale integration and high-speed integration of integrated circuit elements, but also
A comprehensive approach from all directions is becoming important, such as shortening the wiring length with high reliability and high density mounting. In order to realize these, it is necessary to solve various problems associated with an increase in the size of the integrated circuit element, an increase in the number of connection points, an increase in the amount of heat generated, and the like. A module structure, a cooling method, and the like are being studied. On the other hand, in response to the demand for higher speed of integrated circuit devices, research and development of GaAs devices, superconducting devices, and the like have been active in addition to the improvement of conventional Si semiconductor devices. It is known to have characteristics superior to semiconductor devices. However, at present, these devices have not reached the level of Si devices in terms of production technology and cost, and thus have not yet been put to practical use. At present, most devices use Si semiconductor devices.

Japanese Patent Application Laid-Open No. 62-93961 discloses mounting a Si element and a GaAs element on a mullite substrate, and Japanese Patent Application Laid-Open No. 61-292383 discloses a method of mounting a GaAs element on a Si element.
It is described that mounting density is improved by mounting an s element.

[0004]

In order to further improve the performance of large computers, electronic devices, etc., for which higher speeds are required in the future, not only the improvement of Si semiconductor devices, but also the various It is important technology to actively introduce integrated circuit elements capable of high-speed operation, combine the advantages of various elements, and make the most of them. However,
If the element materials are different, the thermal conductivity, heat capacity, etc. of the materials are greatly different. Therefore, when trying to cool the heat generated in the element forming portion of an LSI chip through the chip by the same cooling method at present, An LSI chip made of a material having a low thermal conductivity is better than an LSI chip made of a material having a high thermal conductivity.
The cooling efficiency is lower than that of the SI chip. Also, in general, not all circuits are always operating in an integrated circuit element, and thus, the amount of heat generated differs between operating and non-operating parts. Therefore, when the thermal conductivity of the device is poor, the temperature variation in the device becomes large, and a large thermal strain is applied to the chip. In this way, simply replacing a part of the conventional Si element with another element as it is would cause the temperature of each element to be greatly different at the time of operation, and the temperature variation within each element would be large. Is a problem in terms of reliability. On the other hand, in order to reduce the wiring length by high-density mounting, it is essential to mount these various integrated circuit elements close to each other on the same substrate. As a result, the heat balance is deteriorated, which causes a problem in reliability of the entire mounting structure. As a way to deal with these, simply select the optimal cooling method for each type of element,
Although it is conceivable to use a high-performance cooling structure capable of coping with the element having the largest temperature rise, the cooling structure becomes complicated and expensive.

The above-mentioned Si element and Ga on the mullite substrate
In mounting an As element, the thermal expansion coefficient of the substrate to be mounted is merely set to be in the middle of the GaAs coefficient of these elements, and thermal stress cannot be solved by this alone. Ga to Si element
Even in the case where the As element is mounted, there is a problem of stress due to the difference between the thermal expansion and the calorific value of both.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device mounting structure capable of minimizing thermal stress for each device when a plurality of semiconductor devices made of different materials are mounted on the same substrate.

It is another object of the present invention to provide an integrated circuit device mounting structure capable of reducing temperature variations among a plurality of semiconductor devices made of different materials.

[0008]

According to the present invention, there is provided a mounting structure in which a plurality of integrated circuit elements of different materials are mounted in parallel on a substrate on which wiring is formed, wherein the materials have different thermal conductivity. And the integrated circuit device has at least one requirement of different wiring density, different heating value per unit area and different size, and at least one of the following (a) to (d): An integrated circuit element mounting structure characterized by one of the requirements.

(A) The wiring of the integrated circuit element made of the material having a higher thermal conductivity than the material having the higher thermal conductivity, wherein the wiring density of the integrated circuit element is smaller than that of the material having the higher thermal conductivity. (B) an integrated circuit made of a material having a heat conductivity smaller than the heat conductivity of the material having a high thermal conductivity, wherein the integrated circuit element made of the material having a high heat conductivity has a lower calorific value per unit area; (C) the coefficient of thermal expansion of the substrate is closer to the coefficient of thermal expansion of the largest integrated circuit element than the coefficient of thermal expansion of the smallest integrated circuit element. And (d) the joint between the substrate and the integrated circuit element is stressed at the joint of the largest integrated circuit element as compared to the smallest integrated circuit element. Big means ability to mitigate, in particular preferably carried out in the flexible member. The one having the smallest size is directly joined by soldering.

According to the present invention, there is provided an integrated circuit mounting structure in which a plurality of integrated circuit elements made of different materials are mounted on a carrier substrate and a plurality of the carrier substrates are mounted in parallel on a multilayer circuit board. The integrated circuit element has a different wiring density,
A package in which a plurality of integrated circuit elements having different materials are mounted on a carrier substrate, and the elements are hermetically sealed with a cap; In an integrated circuit mounting structure in which a plurality of layers are mounted in parallel on a multilayer circuit board, the materials have different thermal conductivity and different thermal expansion coefficients, and the integrated circuit elements have different sizes and the package and the multilayer. A cooling means for directly cooling the circuit board with a gas or liquid refrigerant;
Wherein the integrated circuit element mounting structure has at least one of the following requirements.

(A) Wiring of an integrated circuit element made of the material having a higher thermal conductivity than that of the material having the higher thermal conductivity, wherein the wiring density of the integrated circuit element is smaller than that of the material having the higher thermal conductivity. (B) an integrated circuit made of a material having a heat conductivity smaller than the heat conductivity of the material having a high thermal conductivity, wherein the integrated circuit element made of the material having a high heat conductivity has a lower calorific value per unit area; (C) The coefficient of thermal expansion of the multilayer circuit board is closer to the coefficient of thermal expansion of the largest integrated circuit element than the coefficient of thermal expansion of the smallest integrated circuit element. And (d) bonding the multi-layer circuit board and the carrier board to the carrier board on which the largest integrated circuit element is mounted. Smallest integrated circuit large means of elements capable of relaxing the stress of the joints compared to the carrier substrate which is mounted, in particular preferably carried out at a flexible member. In the smallest size, they are directly joined by solder.

According to the present invention, the S
i, and a memory element made of GaAs are mounted in parallel, the size of the logic element is larger than the size of the memory element, and the coefficient of thermal expansion of the substrate is made of GaAs.
An integrated circuit element mounting structure characterized in that the coefficient of thermal expansion is closer to the coefficient of thermal expansion of Si than to the coefficient of thermal expansion of s.

According to the present invention, high-speed arithmetic processing can be performed with a higher degree of integration.

The amount of heat generated per unit area of the LSI chip is
It is proportional to the number of circuits formed per unit area or the wiring density. Conversely, by controlling the number of circuits formed per unit area of the LSI chip,
The amount of heat generated per unit area of the LSI chip can be easily controlled. Therefore, if the number of circuits formed per unit area of an LSI chip made of a material having a high thermal conductivity is made larger than that of an LSI chip made of a material having a low thermal conductivity, the temperature between elements having different materials can be increased. Variation can be easily reduced. In addition, temperature variation in an element, which is a particular problem in an LSI chip made of a material having a low thermal conductivity, can also be reduced by reducing the number of circuits formed per unit area because the amount of heat generated in each portion is reduced. Can be reduced. In this way, if the number of circuits per unit area that is optimal for each element is selected in accordance with the type of element used in combination, the operation frequency of each element, arrangement, cooling structure, etc.,
Without using a complicated and expensive cooling structure as described above,
Even if the conventional cooling structure is used as it is, high reliability of operation of each integrated circuit element can be relatively easily secured.

The integrated circuit element mounting structure of the present invention has a size of 5 mm square or more as an integrated circuit element, and reduces the wiring density of an element having a high thermal conductivity by lowering the wiring density of the element and the element having a lower thermal conductivity than the element. The difference in thermal conductivity from the element is 0.5 per 1 W / m · ° K.
２．０2.0 circuits / mm ² It is desirable to make it higher than that of the low thermal conductivity element. Especially 0.7 to 1.5 circuits / mm
² should be higher.

Further, the mounting structure of the present invention has a size of 5 mm square or more as an integrated circuit element, and the heat generation of an element having a large thermal conductivity is smaller than that of the element and the thermal conductivity of the element. Thermal conductivity difference 1W / m · ° K from element having thermal conductivity
0.001 to 0.02 W / mm ² per unit. Especially 0.
It is preferably 002 to 0.01 W / mm ² .

Further, by changing the dimensions of the LSI chips made of different materials for each material, it is possible to easily cope with other different performance requirements of various systems using the mounting structure of the present invention. For example, when the degree of integration per chip, that is, the total number of circuits formed on one chip is desired to be the same between elements having different materials, an LSI chip made of a material having a low thermal conductivity, that is, It is sufficient to increase the size of the LSI chip with the smaller number of circuits formed therein. Also, the characteristics of the LSI circuit to be formed and L
Due to problems such as the strength of the materials that make up the SI chip, LS
When it is particularly important to reduce the temperature distribution in the I chip and to reduce the thermal strain generated in the chip, a circuit formed per unit area of an LSI chip made of a material having a low thermal conductivity can be used. In addition to reducing the number, the size of the chip may be further reduced.

Further, when two or more kinds of LSI chips made of different materials are mounted on the same substrate, various LSI chips have different coefficients of thermal expansion. It is also important to control the stress in a well-balanced manner to ensure the reliability of the connection between the element and the substrate. To ensure this connection reliability,
The method of changing the dimensions (maximum length) of the element for each material is the simplest method, and is a very effective method compatible with solving the above-mentioned problem. That is, by selecting the thermal expansion coefficient of the substrate on which a plurality of LSI chips of different materials are mounted closer to the chip having the larger size, the stress generated inside the element and / or at the junction between the element and the substrate can be reduced for each element. Can be suppressed. In the case of an integrated circuit element mounting structure in which two or more types of LSI chips of different materials are mounted on the same large substrate via a small substrate or a package structure on which the LSI chip is mounted, the large substrate has a maximum size. A small substrate or package structure having a thermal expansion coefficient closer to the thermal expansion coefficient of the larger (length) LSI chip should be selected to have a thermal expansion coefficient closer to the thermal expansion coefficient of the larger LSI chip of the largest dimension (length). Inside the device, the device and the substrate and / or the large substrate by choosing to have one, or by choosing a large substrate to have a smaller thermal expansion coefficient closer to the thermal expansion coefficient of the package structure or the smaller substrate with the larger maximum dimension (length) Stress generated at the joint between the substrate and the small substrate or the package structure can be reduced.

The mounting structure of the present invention has a size of 5 mm square or more as an integrated circuit element, and when the size difference between the largest and the smallest is 1 mm square,
The difference between the coefficient of thermal expansion of the substrate to be mounted and that of the element having the largest size is 10%.
× 10 ^-7 / ° K or less and the largest one is smaller than that, or larger than the average of the coefficient of thermal expansion of the element, and the above-mentioned difference in size is increased by 1 mm square every time. The value indicating the difference in thermal expansion coefficient is 1 /
It is preferable to reduce the size by 2 or less. For example, the size difference is 5 × 10 ⁻⁷ / ° K or less for a 2 mm square, 2.5 × 10 ⁻⁷ / ° K or less for a 3 mm square, and 1.25 × for a 4 mm square. It is preferable to use a substrate having a coefficient of thermal expansion of 10 ^-7 / ° K or less. More preferably, the difference is 8 × 10 ⁻⁷ / ° K or less for a difference of 1 mm square.

The above-described method is used for a method for mounting a device and a substrate on which the device is mounted, or between the device and a small substrate or a package structure on which the device is mounted, and between a small substrate or a package structure and a large substrate on which the device is mounted. As connection method, C4 (Controlled Collapse Chip Connection),
It is effective when any of TAB (Tape Automated Bonding), wire bonding, solder ball, micro lead and / or pin method is used. Furthermore, two or more types of LSI chips of different materials are connected on the same substrate by the C4 method, or LSI chips of different materials are connected to the small substrate or the package structure on which they are mounted by the C4 method, and these are connected to the same large-sized one. In the integrated circuit element mounting structure connected on the substrate, the same dimensional effect as described above is obtained by using the maximum (longest) distance between the solder bumps formed at the connection portion on each element instead of the size of the LSI chip. By taking into account the above, it is relatively easy to put the stress generated at each LSI chip itself and / or the solder bump joint between the LSI chip and the substrate within a certain range where the connection reliability can be ensured. Similarly, the connection between the small substrate or package structure on which the LSI chip is mounted and the large substrate on which the LSI chip is mounted and / or the connection between the LSI chip and the substrate on which the LSI chip is directly mounted is performed by a solder ball, a micro lead, and / or a pin method. Integrated circuit element mounting structure
The same concept can be applied using the maximum (longest) distance between solder balls, small leads, and / or connection pins formed on each small substrate, package structure or LSI chip, and the stress generated at each joint. , And high connection reliability can be relatively easily secured.

Further, when it is necessary to ensure higher operation and connection reliability due to extremely severe use conditions, mounting restrictions, and the like, these are directly mounted for each LSI chip made of a different material. The mounting method (connection method) on the substrate is changed, or for each small substrate or package structure on which an LSI chip made of a different material is mounted, the method for mounting the small substrate or package structure on a large substrate (connection method) Changing is also a very effective means. Generally, cooling of the LSI chip is mainly performed from the side opposite to the surface on which the elements are formed. However, electrical connection such as a wire in a wire bonding method, a tape in which a wiring in a TAB method is formed, a solder bump in a C4 method, and the like. Naturally, heat can also be removed from the portion where the is formed.
Therefore, C4, TAB,
By selecting various different methods such as a wire bond, a solder ball, a micro lead, and a pin method, it is possible to control the heat directly removed from the element forming surface of the LSI chip. That is, when an extremely high-performance device is to be realized using the mounting structure of the present invention, a more stable L
Controlling the number of circuits formed per unit area of the above-mentioned LSI chip and controlling the heat generation per unit area itself while controlling the SI temperature or satisfying the requirements for mounting the LSI. However, in such a case, the connection of the LSI chip made of a material having a small thermal conductivity is made more difficult than the connection of the LSI chip made of another material having a large heat conductivity. If a method having a large capacity is used, more heat can be directly removed from the element formation surface, and a good heat balance between the elements can be maintained. Furthermore, this method is also effective for the purpose of relaxing the stress generated due to the difference in thermal expansion coefficient between the LSI chip and the substrate when two or more types of LSI chips made of different materials are mounted on the same substrate. Moreover, this method is compatible with the solution of the above-mentioned problem. To change the mounting method (connection method),
4. Includes methods such as changing the type of solder when using the method of mainly connecting with solder such as solder balls, and changing the type of metal when connecting using TAB, wire bond, micro lead, pin method, etc. It is. In particular,
Materials used for connection between an LSI chip and a substrate on which the LSI chip is directly mounted, or between a small substrate or a package structure on which the LSI chip is mounted and a large substrate on which these are mounted,
If a connection with large stress relaxation is desired depending on the use of the integrated circuit element mounting structure, it is preferable to use a material having low rigidity.

The integrated circuit mounting structure of the present invention has a size of 5 mm square or more as an integrated circuit element, and the size is 5 mm.
In the case of mm square, the difference between the coefficient of thermal expansion of the substrate on which the element is mounted and the coefficient of thermal expansion of the integrated circuit element is 20 × 10 ^-7 / °
When the element size is equal to or larger than K, the element is mounted on a substrate by a flexible member.
It is preferable to adopt a structure in which the element is mounted and bonded to the substrate by a flexible member at a value equal to or more than the value obtained by subtracting × 10 ^-7 / ° K, and the element having a lower thermal expansion difference is directly joined by soldering. For example, for a chip size of 10 mm square, when the thermal expansion difference is 10 × 10 ⁻⁷ / ° K or more, bonding is performed by a flexible member such as a pin, and when the thermal expansion difference is 9 × 10 ⁻⁷ / ° K or less. Is preferably joined by C4. As the flexible member, a metal pin, a metal coil spring, or the like is preferable.

In the present invention, the integrated circuit element is S
Various elements such as i, GaAs, InP, HEMT, and other compound semiconductors, Josephson, and optical elements can be used. Also, these integrated circuit elements are formed on a substrate of the same material as the basic material constituting the integrated circuit element,
It may be formed on a substrate made of a different material. That is, the configuration of the LSI chip in the present invention is Si
Si semiconductor device formed on a substrate, GaAs semiconductor device formed on a GaAs substrate, HEMT device, InP
In addition to InP semiconductor elements formed on the substrate,
A GaAs semiconductor device formed on a substrate, a HEMT device, a Josephson junction device, an optical device, an InP semiconductor device formed on a GaAs substrate, a Josephson device, an optical device, a GaAs semiconductor device formed on a sapphire substrate, Any of a HEMT device, a Josephson junction device, and an optical device may be used. The integrated circuit element in the present invention may be either a logic LSI or a memory LSI, and may be divided into a logic LSI and a memory LSI for each LSI chip having a different material, or may be used without distinction. Further, a device having a logic unit and a memory unit in one LSI chip may be used. For example, when a plurality of Si and GaAs are mounted on the same substrate and used, each Si is a logic or memory LSI, and
aAs may be a memory or a logic LSI.
Both i and GaAs may be equipped with a logic LSI and a memory LSI, respectively.

Examples of the substrate on which the LSI chip is directly mounted and / or the small substrate on which the LSI chip is mounted or the large substrate on which the package structure is mounted include Si, alumina, sapphire, mullite, glass, crystallized glass, and ceramic-glass. Composite, silica, SiC, AlN,
Various substrates such as inorganic material substrates such as BN, BeO, ZrO ₂ , and MεO, resin substrates such as an epoxy / Kepler composite material and an epoxy / glass composite material, and enamel substrates, or multilayer circuit substrates can be used. Furthermore, it is also effective to use a substrate having a built-in capacitor or a substrate having a capacitor formed on the surface thereof as required for reducing various noises. Further, when the device mounting structure of the present invention is used, a drive power supply voltage specific to each integrated circuit device made of a different material is applied to a substrate on which these LSI chips are directly mounted and / or a small substrate on which the LSI chips are mounted or It is effective to supply through a wiring formed inside and / or on the surface of a large substrate on which the package structure is mounted.

The element implementation structure of the present invention can be used by using various cooling methods such as natural air cooling, forced air cooling, indirect liquid cooling, and direct liquid cooling. In particular, high-speed processing capability is required,
Therefore, when the calorific value is very large, it is effective to immerse the element mounting structure of the present invention in a liquid refrigerant such as Freon or liquid nitrogen. Further, the element mounting structure of the present invention is used by being immersed in a very low temperature liquid refrigerant such as liquid nitrogen. In this case, an element mounting structure according to the present invention is to use an element whose operating speed is increased at a lower temperature than room temperature, for example, an element such as CMOS, Bj-CMOS, GaAs, and HEMT of Si, particularly as an integrated circuit element. It is preferable to improve the performance of a large computer using a body and various electronic control devices. Further, it is preferable to select an indium-based solder which is soft and hard to be brittle even at a low temperature.

[0026]

(Embodiment 1) Cu on the surface and inside
The number of circuits formed per unit area is about 200 circuits / mm ² , 5 mm □ on a glass ceramic multilayer wiring board (thermal expansion coefficient: 40 × 10 ⁻⁷ / K) on which a conductor wiring is formed.
(Integration per chip: 5000 gates) LSI chip made of Si on which a Si semiconductor integrated circuit element is formed (thermal conductivity: 150 W / m · K, coefficient of thermal expansion: 26 × 1)
0 ^-7 / K) and the number of circuits formed per unit area is about 100 circuits / mm ² , 5 mm square (integration degree: 2500 gates)
An LSI chip (thermal conductivity: 58 W / m · K, thermal expansion coefficient: 57 × 10 ⁻⁷ / K) made of GaAs on which a GaAs semiconductor integrated circuit element of the above-described type is formed by using a Pb-
The connection was made by a C4 method using 5% Sn solder bumps. On the other hand, as a comparative example, both a 5000-integrated Si-LSI chip and a GaAs-LS
The I chip was connected on a glass ceramic multilayer wiring board by the same method. The maximum distance between bumps is Si-
The size of both the LSI chip and the GaAs-LSI chip was 6.3 mm.

The difference in thermal conductivity between the Si and GaAs devices in this embodiment is 92 W / m · ° K, and the difference in the number of circuits is 1
The number of circuits is 00 circuits / mm ² , and a circuit having an increase of about 1.1 circuits / mm ² per 1 W / mK difference in thermal conductivity can be formed in the Si element.

Using these mounting structures, an operation test of each LSI was performed under the same indirect liquid cooling conditions, simulating actual use conditions, and the junction temperature distribution (temperature variation) in the chip and the steady state were evaluated. The average temperature of each device was measured. When the number of circuits formed per unit area of the comparative example is the same, it is clear that a GaAs element having a small thermal conductivity has a larger temperature distribution (temperature variation) in the element. Was. On the other hand, it was confirmed that the temperature distribution in the GaAs element was considerably reduced in the mounting structure according to the present embodiment in which the integration degree of the GaAs element was smaller than that of the Si element. Furthermore, the average temperature of both elements in the steady state was also higher in the comparative example than in the Si element.
While the As element was higher, the temperature was almost the same in this embodiment.

In this embodiment, the ceramic multilayer board is further mounted on an organic multilayer circuit board, connected to a platter via a connector, arranged three-dimensionally, and used for a large-scale computer or the like.

The cooling may be forced blast cooling or direct liquid cooling. In this embodiment, the logic element, Si, and memory are made of GaAs, and the former has a higher degree of integration than the former.

Example 2 Alumina multilayer wiring board I having conductor wirings formed on the surface and inside (coefficient of thermal expansion: 55 × 1)
0 ⁻⁷ / K), the number of circuits formed per unit area is about 200 circuits / mm ² , and a 7 mm square (integration: 10,000 gates) is formed on the Si-LSI chip 2 and the unit area. A GaAs-LSI chip 3 having a number of circuits of about 100 circuits / mm ² and 10 mm square (integration degree: 10000 gates) is soldered to a Pb-5% Sn solder bump 4 having a height of about 150 μm.
And connected by C4 method. On the surface of the alumina multilayer wiring board 1 to which the LSI chip is not connected, I / O
O pin 5 is connected. FIG. 1 shows a part of a cross section perpendicular to the substrate. On the other hand, as comparative examples, the chip size and the number of circuits formed per unit area are 7 mm □, respectively.
200 circuits / mm ² Si-LSI chip and GaAs
-The LSI chip was connected on the alumina multilayer wiring board by the same method. The maximum distance between bumps is 9 mm for a 7 mm square LSI chip and 13.000 mm for a 10 mm square LSI chip.
It was 5 mm.

In this embodiment, the difference between the chip sizes of the Si and GaAs devices is 3 mm square and the size is large.
The thermal expansion difference between the GaAs device and the alumina substrate is 2 × 10 ^-7
/ ° K, and the thermal stress of both Si and GaAs can be remarkably reduced.

The back surface of each LSI of the mounting structure is brought into contact with the same indirect liquid cooling heat sink to cool the LSI.
An operation test of I was performed. In order to make the total number of circuits per chip the same, the number of circuits per unit area of the GaAs element having a small thermal conductivity was made smaller than that of Si, and the chip size was made larger than that of Si in this embodiment. Compared to the comparative example in which the number of circuits per unit area and the chip size were both equal, the temperature distribution (temperature variation) in the GaAs device and the average temperature difference between both devices in the steady state were both reduced. On the other hand, when the number of circuits per unit area was the same as in Example 1, it was also confirmed that the temperature variation in the GaAs element became larger as the element size became larger.

In this embodiment, three-dimensional mounting can be performed in the same manner as in the first embodiment.

In this embodiment, Si is a logic and Ga
A configuration in which As is used as a memory, or the reverse configuration is also implemented. Cooling can be performed in the same manner as described above.

(Example 3) A mullite multilayer wiring board having conductor wirings formed on the surface and inside (coefficient of thermal expansion: 30 × 10
^-7 / K), the number of circuits formed per unit area is approximately 200 circuits / mm ² , and the number of circuits formed per unit area is 7 mm □ (integration: 10,000 gates). Is about 100 circuits / mm ² , 5mm □ (integration degree: 2
GaAs-LSI chip of about 500 gates
C4 using a 0 μm Pb-5% Sn solder bump
Connected by method. On the other hand, as a comparative example, an Si-LSI chip having a chip size of 7 mm □ and a number of circuits formed per unit area of 200 circuits / mm ² and a GaAs-LSI chip having 100 circuits / mm ² were used in the same manner. Thus, the mullite multilayer was connected on the wire substrate. In addition,
The maximum distance between bumps is 6.3m for a 5mm □ LSI chip.
m, 9 mm for a 7 mm square LSI chip.

In this embodiment, the difference between the Si and GaAs element sizes is 2 mm square, and the difference between the large Si and the mullite substrate has a thermal expansion coefficient of 4 × 10 ⁻⁷ / ° K. Can be remarkably reduced.

The back surface of each LSI of the mounting structure is brought into contact with the same indirect cooling
An operation test of I was performed. Both the number of circuits per unit area and the chip size of a GaAs element having a small thermal conductivity are Si
In this embodiment, which is smaller than that of the comparative example, the number of circuits per unit area of the GaAs element is smaller than that of the comparative example in which only the number of circuits is smaller.
It was confirmed that the temperature distribution (temperature variation) in the GaAsS element was further reduced and could be reduced to about the same level as the Si element.

Next, these mounting structures were placed at -55 ° C to 1 ° C.
As a result of conducting a temperature cycle test under the conditions of 50 ° C. and 1 cycle / h, in the sample shown in the comparative example, after about 300 cycles, cracks due to fatigue fracture were observed in the solder portion connected to the 10 mm square GaAs element. In addition, when a similar temperature cycle test was performed at the same time as the energization test, the sample of the comparative example was 10 mm square after about 250 cycles.
It was found that cracks occurred at the ends of the GaAs device. On the other hand, in the mounting structure of the present example, no defect such as cracks occurred in the solder joints or the elements at all even after the lapse of 1000 cycles, and a good mounting structure could be realized in terms of the reliability of terminal connection. Became clear.

In addition, three-dimensional mounting can be performed as in the first embodiment.

Example 4 A glass ceramic multilayer wiring board 6 having conductor wirings formed on the surface and inside (coefficient of thermal expansion:
35 × 10 ⁻⁷ / K), and a Si-logic LSI chip 7 with a heat value per unit area of 0.7 W / mm ² and 10 mm □.
And the heat value per unit area is 0.3W / mm ² , 7mm □
GaAs-memory LSI chip 8 having a height of about 150 μm
Are connected by the C4 method using the Pb-5% Sn solder bump 9 described above. The maximum bump-to-bump distance is 13.1 mm for a 7 mm square LSI chip and 13 mm for a 10 mm square LSI chip.
It was 5 mm. Further, I / O pins 10 are connected to a surface of the glass ceramic multilayer wiring board 6 where no LSI chip is connected. The layout of each LSI chip on the plane was such that many GaAs-memory LSI chips exist around the Si-logic LSI chip. FIG. 2 shows a part of a cross section perpendicular to the substrate, and FIG. 3 shows a plan view seen from above the substrate.

The difference in thermal conductivity between Si and GaAs is 98 W /
m · K, the difference between these two calorific values is 0.4 W / mm ^2, and in this embodiment, the difference in thermal conductivity per 1 W / mK is:
The calorific value of Si can be made higher than that of GaAs by 0.004 W / mm ² . This makes it possible to make the calorific values of both elements equal, to eliminate a local rise in temperature, and to use the same cooling means.

The back surface of each LSI of the mounting structure is brought into contact with the same indirect liquid cooling heat sink to cool the LSI while cooling.
An operation test of I was performed. Temperature distribution (temperature variation) in a GaAs device having a small thermal conductivity and Si,
The average temperature difference between both GaAs devices was small, and was at a level that would not cause any problem in practical use.

In this embodiment, a memory element is regularly arranged around a logic element. As memories arranged around the logic element, there are high-speed large-capacity buffer storage, control storage, and large-capacity work storage, and high speed is required, and GaAs is used for at least one of them.

Embodiment 5 The number of circuits formed per unit area is about 200 circuits / mm ² , 10 mm square (integration degree 20
000-gate) Si-LSI chip 11 is a small mullite substrate 12 having an outer dimension of 12 mm □ and conductor wiring formed on its surface and / or inside (coefficient of thermal expansion: 30 × 10 ^−7).
/ K) and a GaAs-LSI chip 13 of about 100 circuits / mm ² and 7 mm □ (integration of 5000 gates) formed per unit area and having an outer dimension of 9 mm □.
On a small alumina substrate 14 (thermal expansion coefficient: 55 × 10 ⁻⁷ / K) having conductor wirings formed on the surface and / or inside thereof, solder bumps 15 each having a height of about 150 μm Pb-5% Sn are used. Connected in the C4 system. Further, in order to protect the semiconductor element and to improve the reliability of the solder connection, a spherical silica filler and rubber-like particles are compounded in the gap between these small substrates and the LSI chip to obtain a thermal expansion coefficient of Pb-.
An epoxy resin 87 having a coefficient of thermal expansion approximated to that of a solder material made of 5% Sn was filled and thermally cured to form a kind of package structure. Among these small substrates, Si-
The 12 mm square substrate 12 on which the LSI chip 11 is mounted is made of a large-sized glass ceramic multilayer wiring board 17 by a lead system 16 composed of a small number of turns of a coil spring made of metal.
(Coefficient of thermal expansion: 40 × 10 ⁻⁷ · K). Further, I / O pins 18 are connected to a surface of the multilayer wiring board 17 to which no LSI chip is connected. On the other hand, G
a 9 mm square substrate 14 on which an AS-LSI chip 13 is mounted
Was connected to the same large glass ceramic multilayer wiring board 17 as above using solder bumps 19 made of Pb-10% Sn to form an integrated circuit element mounting structure as shown in FIG. On the other hand, as comparative examples, a Si-LSI chip and Ga
An integrated circuit element mounting structure was configured in the same manner as in this example, except that both the small substrates on which the As-LSI chips were mounted were connected to a large glass-ceramic multilayer wiring substrate by the micro-lead method. Note that the maximum distance between bumps is 9 mm for a 7 mm
13.5mm for SI chip, 12mm for small board of 9mm □,
The longest lead-to-lead distances on small boards of 9 mm □ and 12 mm □ were 12 mm and 15.5 mm, respectively.

A cooling fin was connected to the back surface of each LSI of the mounting structure, and an LSI operation test was performed while the entire mounting structure was forcibly air-cooled. When both the small substrate and the large substrate of the comparative example are connected by the fine lead method, the contribution of removing the heat generated in the LSI from the substrate side is small because the leads are thin, and the heat is mainly transmitted from the back surface of the chip. Removed. Therefore, GaAs having low thermal conductivity
In the device, the temperature distribution (temperature variation) in the device was larger than that in the Si device, and the operation of the GaAs device was not stable. On the other hand, in the present embodiment, the connection of the small substrate on which the GaAs-LSI chip is mounted to the large substrate is performed using Pb-10% Sn solder bumps having better heat transfer characteristics than the fine leads. Can be removed through the solder bumps, so that the temperature distribution (temperature variation) in the device can be greatly improved as compared with the comparative example, and the stable operation of the GaAs-LSI can be secured.

In this embodiment, a larger Si chip of 10 mm square is mounted on a mullite substrate and
It is mounted on a glass substrate of 0 × 10 ⁻⁷ / ° K.
Thermal expansion difference between mullite substrate and glass substrate is 10 × 10 ^-7
/ ° K, and are joined by flexible minute leads 16. Thereby, the α difference between the two can be reduced.

(Embodiment 6) The number of circuits formed per unit area is about 200 circuits / mm ² and 10 mm square (integration degree 2
0000 gate) on a small glass ceramic substrate 21 (coefficient of thermal expansion: 35 × 10 ⁻⁷ / K) with an outer dimension of 12 mm □
b-5% Sn solder bumps 22 are connected by C4 method, and a high thermal conductive SiC cap 23 (thermal expansion coefficient: 37 × 10 ⁻⁷ / K) is put on the solder seals 24 to cover them.
And a small package. In addition, this package
b- Connected to a large glass ceramic multilayer wiring board 26 (coefficient of thermal expansion: 35 × 10 ⁻⁷ / K) by a solder ball method using a solder 25 made of 10% Sn. On the other hand, the number of circuits formed per unit area is about 100 circuits / mm.
² , GaAs of 10mm □ (integration 10,000 gates)
The LSI chip 27 is a small glass ceramic substrate 28 having an outer dimension of 12 mm □ (coefficient of thermal expansion: 45 × 10 ⁻⁷ / K).
The solder bumps 22 made of Pb-5% Sn having a height of about 150 μm are connected on the upper surface by a C4 method, and a cap 29 made of AlN (aluminum nitride) (thermal expansion coefficient: 37 × 10 ⁻⁷ / K) ) And solder sealing 3
0 and a small package. This package structure was connected on the large glass ceramic multilayer wiring board 26 by a pin method 31. However, the inner surfaces of the caps of these package structures, the Si-LSI chip 20 and the GaAs
The back surface of the s-LSI chip 27 is fixed with solders 32 and 33. In addition, these small glass ceramic substrates have conductor wiring and capacitors 3 on the surface and / or inside thereof.
4, 35 are formed. Further, I / O pins 36 are connected to a surface of the large-sized glass ceramic multilayer wiring board 26 where no LSI chip is connected. FIG. 5 shows a cross-sectional view of the integrated circuit element mounting structure of the present embodiment. On the other hand, as a comparative example, a Si-LSI chip having 200 circuits / mm ² and a GaAs
A mounting structure was formed using an s-LSI chip by the same method. Note that the maximum distance between bumps is 10 mm square L
13.5mm for SI chip, 15.5mm for small glass ceramic substrate with maximum solder ball or pin distance of 12mm □
mm.

In this embodiment, the difference in the thermal expansion coefficient between the substrate 29 on which the Si element is directly mounted and the multilayer board on which the substrate is mounted is 10 × 10 ⁻⁷ / ° K, and the joining is performed by pins, and the difference is 9 ×. In the portion where the temperature is 10 ^-7 / ° K or less, bonding by C4 can be performed.

An operation test of an LSI simulating actual use conditions was performed while the back surface of each small package of the mounting structure was connected to the same indirect liquid cooling heat sink and cooled.
The junction temperature distribution (temperature variation) in the chip and the average temperature of each element in a steady state were measured. When the number of circuits formed per unit area of the comparative example is the same, the GaAs element having a small thermal conductivity has a larger temperature distribution (temperature variation) in the element. In the mounting structure of this example, it was confirmed that the temperature distribution in the GaAs element was considerably reduced. Furthermore, the average temperature of both elements in the steady state was almost the same in this embodiment, and the temperature variation in the large substrate could be reduced.

(Embodiment 7) The number of circuits formed per unit area is about 200 circuits / mm ² , 15 mm square (integration degree 45
Small mullite substrate 38 (coefficient of thermal expansion: 30 × 10 ⁻⁷ ) having a Si-CMOS LSI chip 37 of 000 gates and an outer dimension of 17 mm □ and conductor wiring formed on the surface and inside.
/ K), using an In solder bump 39 having a height of about 150 μm and connecting with a C4 method,
The package was covered with a cap 40 and sealed with solder 41 to form a small package. In addition, this package is In-48%
A large mullite multilayer wiring board 43 (coefficient of thermal expansion: 30 × 10 3) is formed by a solder ball method using a solder 42 made of Sn.
^-7 / K). On the other hand, the number of circuits formed per unit area is about 100 circuits / mm ² ,
000-gate) GaAs-LSI chip 4 44a-
d is a small alumina substrate 45 (having a thermal expansion coefficient of 50 ×
10 ⁻⁷ / K), which are also connected by a C4 method using In solder bumps 39 having a height of about 150 μm, and further covered with a cap 46 made of AlN to form a solder seal 47.
And one compact package. This package structure was connected on the large-sized mullite multilayer wiring board 43 by a pin method 48. Here, the inner surfaces of the caps of these package structures, the Si-LSI chip 37 and the GaAs
-The back surface of the LSI chip 44 is in contact, and a He gas 49 is sealed inside the package structure. On these small substrates, conductor wiring and capacitors 50 are formed on the surface and / or inside, and several thin film wiring layers 51 and resistors 52 are formed on the surface of the substrate. . The surface of the large mullite multilayer wiring board 43 to which the LSI chip is not connected is provided with an I / O
Pin 53 is connected. The maximum distance between bumps is 7.5 mm for a 6 mm square LSI chip and LS for a 15 mm square LSI chip.
The size of the I-chip was 20.5 mm, and the maximum distance between solder balls or pins was 23 mm for a small board of 17 mm square.

The above mounting structure is immersed in circulating convection liquid nitrogen 88, and while the entire mounting structure is cooled, an operation test of an LSI simulating actual use conditions is performed. The distribution (temperature variation) and the average temperature of each element in a steady state were measured. as a result,
Both the temperature distribution (temperature variation) in the GaAs device having a small thermal conductivity and the average temperature difference between the Si and GaAs devices in a steady state were small, and were at a level that would not cause any practical problem.
FIG. 6 shows a partial cross-sectional view and a cooling state of the integrated circuit element mounting structure of this embodiment.

(Embodiment 8) The number of circuits formed per unit area is about 200 circuits / mm ² , 15 mm square (integration degree 45
000 gate) Si-LSI chip 54 is a small A with an outer dimension of 17 mm square and conductor wiring formed on the surface and inside.
On an 1N substrate 55 (coefficient of thermal expansion: 45 × 10 ⁻⁷ / K),
Connected by TAB method 56, and AN cap 57
To form a small package.
On the other hand, an HE having a number of circuits formed per unit area of 100 circuits / mm ² and 10 mm square (integration of 10,000 gates)
The MT-LSI chip 59 is also connected by a TAB method 61 on a small-sized AlN substrate 60 having an outer dimension of 12 mm square and having conductor wirings formed on the surface and inside thereof.
And a small package. These packages were connected to a large glass ceramic multilayer wiring board 65 (coefficient of thermal expansion: 40 × 10 ⁻⁷ / K) by a pin method 64. Here, the inner surfaces of the caps of these package structures and the back surfaces of the Si-LSI chip 54 and the HEMT-LSI chip 59 are fixed by solders 66 and 67, respectively. On these small substrates, conductor wiring is formed on the surface and / or inside, and several thin film wiring layers 68 are formed on the surface.
And a resistor 69 are formed. On the large glass ceramic multilayer wiring board 65, several layers of organic thin film multilayer wiring sections 70 are formed on the upper surface thereof. Also, I / O pins 71 are connected to the lower surface where no LSI chip is connected. The maximum distance between pins was 15.5 mm for a small board of 12 mm □ and 23 mm for a small board of 17 mm □.

The above mounting structure was immersed in circulating convection liquid nitrogen 88, and while cooling the entire mounting structure, an operation test of an LSI simulating actual use conditions was performed to determine the junction temperature in the chip. The distribution (temperature variation) and the average temperature of each element in a steady state were measured. as a result,
Both the temperature distribution (temperature variation) in the GaAs device having a small thermal conductivity and the average temperature difference between the Si and GaAs devices in a steady state were small, and were at a level that would not cause any practical problem.
FIG. 7 shows a partial cross-sectional view and a cooling state of the integrated circuit element mounting structure of this embodiment.

(Embodiment 9) The number of circuits formed per unit area is about 100 circuits / mm ² , 5 mm square (integration degree 250
0-gate) Si-LSI chip 72 with external dimensions of 8 mm
□ Small AlN with conductor wiring formed on the surface and inside
(Aluminum nitride) substrate 73 (coefficient of thermal expansion: 45 × 1)
0 ⁻⁷ / K), using a solder bump 74 made of Pb-5% Sn having a height of about 150 μm and connecting them in a C4 system, and covering this with a cap 75 made of AlN and sealing with solder 76.
Small package. On the other hand, the number of circuits formed per unit area is about 50 circuits / mm ² , 7 mm square (integration degree 25
A GaAs-LSI chip 77 having a thickness of about 150 μm is also formed on a small AlN substrate 78 having external dimensions of 10 mm square and conductor wiring formed on the surface and inside.
5% Sn solder bumps 74 were used for connection in the C4 mode, and a cap 79 made of AlN was put on the solder bumps 74 to seal them with solder 80 to form a small package. A large glass fiber-epoxy composite multilayer wiring board 82 (coefficient of thermal expansion: 65 ×
10 ⁻⁷ / K). Here, the inner surfaces of the caps of these package structures and the Si-LSI chip 72 and G
The aAs-LSI chip 77 is fixed by solders 83 and 84 on the back surface. The maximum distance between bumps is 5mm □ LS
6.3mm for I chip, 9mm for LSI chip of 7mm □, 8mm
The longest lead-to-lead distances on small boards of mm □ and 10 mm □ were 10 mm and 13 mm, respectively.

An Al fin 85, 86 for cooling was connected to the back surface of each small package of the mounting structure, and an LSI operation test was performed while the mounting structure was forcibly air-cooled. As a result, the temperature distribution (temperature variation) in the GaAs element having a small thermal conductivity and Si, GaAs in a steady state
The average temperature difference between the two elements was small, and was at a level that would not cause any problem in practical use. FIG. 8 is a cross-sectional view of the integrated circuit element mounting structure and the cooling structure of the present embodiment.

(Embodiment 10) FIGS. 9 and 10 are sectional views of an integrated circuit element mounting structure showing another embodiment of the present invention.

As in the previous embodiment, FIG.
A 0 mm square Si element 92 and a 7 mm square GaAs element 93 are metal-bonded to a CuW alloy or AlN sintered body substrate 90,
It is mounted on an alumina plate 95 by TAB 96.
Sealing is provided by metal cap 98 and C4 connection 9
At 1, it is mounted on the alumina multilayer substrate 94. On this alumina multilayer substrate 94, five or more polyimide multilayer thin films (Cu, Au thin films) are formed. This embodiment is another embodiment 4.
Is the same as

In FIG. 10, a 10 mm square Si element 102 and a Ga
The As elements 103 are each metal-bonded with solder, mounted on the AlN substrate 105 with TAB, and sealed with a metal cap 108. The AlN substrate 105 is provided with a through-hole conductor, and is connected to an alumina-dispersed glass multilayer substrate made of a Cu conductor by pins 107. A
A polyimide layer having a multilayer metal thin film is formed on the 1N substrate 105, and a polyimide layer is similarly formed on the glass multilayer substrate. This embodiment is the same as the other embodiment 6.

[0060]

According to the present invention, different L values of various materials are used.
When using the SI chip mounted on the same substrate, or mounted and used on the same large substrate via a small substrate or package structure, a complicated or expensive cooling structure is not required, and a general It is possible to easily satisfy conditions such as a temperature distribution in a chip and a balance of heat of the entire module substrate, which are essential for forming a highly reliable integrated circuit element mounting structure by a cooling method.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same substrate.

FIG. 2 is a cross-sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same substrate.

FIG. 3 is a plan view showing an example of the structure of the integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same substrate.

FIG. 4 is a cross-sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same large substrate via a small substrate.

FIG. 5 is a cross-sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same large substrate via a small package structure.

FIG. 6 is a cross-sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same large substrate via a small package structure.

FIG. 7 is a cross-sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same large substrate via a small package structure.

FIG. 8 is a sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same large substrate via a small package structure.

FIG. 9 is a cross-sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same large substrate via a small package structure.

FIG. 10 is a sectional view showing an example of the structure of an integrated circuit element mounting structure of the present invention in which two types of LSI chips are mounted on the same large substrate via a small package structure.

[Explanation of symbols]

1, 6, 17, 26, 43, 65, 82 ... large multilayer wiring board, 2, 7, 11, 16, 20, 37, 54, 72,
92, 102 ... Si-LSI chip, 3, 8, 13, 2
3,27,44,59,77,98,103 ... GaAs
-LSI chip, 4, 15, 18, 39, 74 ... solder bump, 5, 18, 36, 53, 71 ... I / O pin, 1
2,14,17,24,38,45,55,60,7
3, 78: small substrate 16: minute lead, 19, 35, 42, 91: solder ball, 19, 25, 40, 46, 57, 62, 75, 7
9, 98, 108 ... caps 20, 26, 28, 29, 41, 47, 58, 63, 6
6, 67, 76, 80, 83, 84 ... solder for joining, 2
7, 48, 64, 81, 97, 107 ... pins, 30, 3
1,50 ... condenser, 49 ... He gas, 51,70 ...
Thin film multilayer wiring section, 52: resistor, 85, 86: cooling fin, 87: epoxy resin, 88: liquid nitrogen.

Continuing from the front page (72) Inventor Koichi Inoue 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Within Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Yoshiyuki Yasuto 4026 Kuji-machi, Hitachi City, Hitachi, Ltd. (72) Inventor Tadahiko Miyoshi 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd.

Claims (2)

[Claims] 1. An integrated circuit device mounting structure comprising a plurality of integrated circuit devices of different materials mounted in parallel on a substrate on which wiring is formed, wherein the different materials of the integrated circuit devices have different thermal conductivities. Wherein the wiring density of an integrated circuit element made of the material having a high thermal conductivity is higher than the wiring density of an integrated circuit element made of the material having a low thermal conductivity. Structure. 2. An integrated circuit device mounting structure comprising a plurality of integrated circuit devices of different materials mounted in parallel on a substrate on which wiring is formed, wherein the different materials of the integrated circuit devices have different thermal conductivity. The heat generation per unit area of the integrated circuit element made of a material having a high thermal conductivity is made larger than the heat generation per unit area of the integrated circuit element made of a material having a low heat conductivity. Characteristic integrated circuit element mounting structure.