JPH11317487A - Electronic device and mounting method therefor - Google Patents
Electronic device and mounting method thereforInfo
- Publication number
- JPH11317487A JPH11317487A JP10122205A JP12220598A JPH11317487A JP H11317487 A JPH11317487 A JP H11317487A JP 10122205 A JP10122205 A JP 10122205A JP 12220598 A JP12220598 A JP 12220598A JP H11317487 A JPH11317487 A JP H11317487A
- Authority
- JP
- Japan
- Prior art keywords
- alloy
- film
- bonding
- electronic device
- alloy film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Electroplating Methods And Accessories (AREA)
- Coating With Molten Metal (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は電子装置及び電子装
置の実装方法に関する。特に本発明は、実装基板の電極
に接合用合金膜を介して電気的かつ機械的に接続する外
部端子を有する電子装置及びこの電子装置の実装方法に
関する。The present invention relates to an electronic device and a method for mounting the electronic device. In particular, the present invention relates to an electronic device having an external terminal that is electrically and mechanically connected to an electrode of a mounting board via a bonding alloy film, and a method of mounting the electronic device.
【０００２】[0002]
【従来の技術】半導体装置、抵抗素子、容量素子等の電
子装置は、マザーボード、ドータボード、ベビーボード
等のプリント配線基板に電気的かつ機械的に接続され、
実装される。電気的かつ機械的な接続には接合用半田が
使用される。接合用半田は半田リフロー（熱接合処理）
により電子装置の外部端子とプリント配線基板の電極と
の間を接合する。2. Description of the Related Art Electronic devices such as semiconductor devices, resistance elements and capacitance elements are electrically and mechanically connected to printed wiring boards such as motherboards, daughter boards and baby boards.
Implemented. For electrical and mechanical connection, bonding solder is used. Solder for joining is solder reflow (thermal joining process)
Thereby, the external terminals of the electronic device and the electrodes of the printed wiring board are joined.
【０００３】電子装置、例えば半導体装置はパッケージ
から外部端子としてのアウターリードを引き出した構造
を有する。パッケージ内部にはトランジスタや集積回路
を形成した半導体チップが封止される。アウターリード
表面にはＳｎ−Ｐｂ（錫−鉛）合金めっき膜が形成され
る。このめっき膜は、半田リフローにより接合用半田の
溶融前に溶融して広がり、この後に接合用半田が溶融し
たときの広がりを高め、接合用半田の濡れ性を向上す
る。従って、めっき膜には、通常、接合用半田の融点温
度よりも若干低い融点温度を有する材料が選択される。
例えば、融点温度が約２００℃前後の接合用半田を使用
する場合、半田リフローは約２３０℃で行われ、めっき
膜には融点温度１８３℃のＳｎ−３７％Ｐｂ（共晶半
田）合金膜が使用される。An electronic device, for example, a semiconductor device has a structure in which outer leads as external terminals are drawn out of a package. A semiconductor chip on which a transistor or an integrated circuit is formed is sealed inside the package. An Sn-Pb (tin-lead) alloy plating film is formed on the outer lead surface. The plating film is melted and spread before the solder for joining is melted by the solder reflow, and thereafter, the spread when the solder for joining is melted is increased, and the wettability of the solder for joining is improved. Therefore, a material having a melting point slightly lower than the melting point of the bonding solder is usually selected for the plating film.
For example, when using a bonding solder having a melting point of about 200 ° C., solder reflow is performed at about 230 ° C., and an Sn-37% Pb (eutectic solder) alloy film having a melting point of 183 ° C. is used as a plating film. used.
【０００４】電子装置としての抵抗素子、容量素子はい
ずれも半導体装置の構造と同様にパッケージから引き出
された外部端子を有し、接合用半田を介してプリント配
線基板に実装される。外部端子表面には濡れ性を向上す
るめっき膜が形成される。[0004] Each of a resistance element and a capacitance element as an electronic device has an external terminal drawn out of a package similarly to the structure of a semiconductor device, and is mounted on a printed wiring board via bonding solder. A plating film for improving wettability is formed on the surface of the external terminal.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、電子装
置並びにこの電子装置の実装方法においては、以下の点
について配慮がなされていない。However, in the electronic device and the mounting method of the electronic device, the following points are not considered.
【０００６】（１）最近、環境保護等の問題から有害物
質であるＰｂの使用を制限する傾向にあり、めっき膜に
はＰｂの代用としてＳｎ又はＰｄが使用され、接合用半
田にはＰｂフリー半田としてＳｎ−Ａｇ−Ｂｉ（錫−銀
−ビスマス）合金が使用される。例えばＳｎ−３％Ａｇ
−４％Ｂｉ合金は約２１０℃の融点温度を有し、約２３
０℃の現状の半田リフローが行えるが、めっき膜である
Ｓｎ単独の融点温度は２３２℃、Ｐｄ単独の融点温度は
１５５４℃と融点温度が非常に高くなる。このため、半
田リフローにおいて接合用半田が先行溶融し、めっき膜
が後から溶融する又はＰｄにおいては溶融しないので、
接合用半田の濡れ性が劣化する。すなわち、プリント配
線基板と電子装置の外部端子との間の接続強度が充分に
確保されず、接合不良が発生する可能性がある。(1) Recently, there has been a tendency to limit the use of Pb, which is a harmful substance, due to problems such as environmental protection. Sn or Pd is used instead of Pb for a plating film, and Pb-free is used for solder for bonding. Sn-Ag-Bi (tin-silver-bismuth) alloy is used as the solder. For example, Sn-3% Ag
-4% Bi alloy has a melting point temperature of about 210 ° C.,
Although the current solder reflow of 0 ° C. can be performed, the melting point temperature of Sn, which is a plating film alone, is 232 ° C., and the melting point temperature of Pd alone is 1554 ° C., which is extremely high. For this reason, since the solder for joining precedes in the solder reflow and the plating film melts later or does not melt in Pd,
The wettability of the solder for joining deteriorates. That is, the connection strength between the printed wiring board and the external terminals of the electronic device is not sufficiently secured, and there is a possibility that a bonding failure may occur.
【０００７】（２）この接合不良を防止するには半田リ
フロー温度を高めることが有効な方法である。例えば、
めっき膜としてＳｎを使用する場合、半田リフロー温度
を約２６０℃に設定すると濡れ性の向上が図れ、この濡
れ性の向上に伴い、接合不良が防止できる。しかしなが
ら、電子装置のパッケージ材料、プリント配線基板の基
板材料には樹脂系材料が使用される場合が多く、高温度
の半田リフローに耐えられない。(2) To prevent this joint failure, it is effective to raise the solder reflow temperature. For example,
In the case of using Sn as the plating film, when the solder reflow temperature is set to about 260 ° C., the wettability can be improved, and with the improvement in the wettability, the bonding failure can be prevented. However, resin-based materials are often used as package materials for electronic devices and substrate materials for printed wiring boards, and cannot withstand high-temperature solder reflow.
【０００８】（３）前述のＰｂフリーの接合用半田であ
るＳｎ−Ａｇ−Ｂｉ合金は、融点温度を下げるために、
Ｓｎベースの合金にＢｉを添加する。現状の半田リフロ
ー温度においてＳｎ単独、Ｐｄ単独のめっき膜では充分
な濡れ性が確保できないので、めっき膜にＳｎ−Ｐｂ合
金を使用した場合、半田リフローによりＳｎ−Ｐｂ−Ｂ
ｉ合金が生成される。このＳｎ−Ｐｂ−Ｂｉ合金は約９
０〜１００℃の低い融点温度を有し、プリント配線基板
に実装された電子装置の動作温度で溶融する可能性があ
る。すなわち、電子装置の動作中に接合用半田が溶融
し、溶融した部分にクラックが発生することに起因し
て、プリント配線基板の電極と外部端子との間に接合不
良が発生する。このため、電気的信頼性が低下する。(3) The Sn—Ag—Bi alloy, which is the above-mentioned Pb-free solder for joining, is used to lower the melting point temperature.
Bi is added to the Sn-based alloy. At the current solder reflow temperature, a sufficient plating property cannot be ensured with a plating film of Sn alone or Pd alone. Therefore, when a Sn-Pb alloy is used for the plating film, Sn-Pb-B
An i-alloy is produced. This Sn-Pb-Bi alloy has about 9
It has a low melting point temperature of 0 to 100 ° C. and may melt at the operating temperature of an electronic device mounted on a printed wiring board. That is, the bonding solder is melted during the operation of the electronic device, and a crack is generated in the melted portion, so that a bonding failure occurs between the electrode of the printed wiring board and the external terminal. For this reason, the electrical reliability decreases.
【０００９】本発明は上記課題を解決するためになされ
たものである。従って、本発明の目的は、Ｐｂの使用を
制限し環境保護を図りつつ、実装基板の電極との間で接
合不良や短絡による不良が防止できる電子装置を提供す
ることである。The present invention has been made to solve the above problems. Accordingly, an object of the present invention is to provide an electronic device capable of preventing a failure due to a bonding failure or a short circuit with an electrode of a mounting board while limiting the use of Pb and protecting the environment.
【００１０】さらに、本発明の目的は、上記目的を達成
しつつ、リフロー温度の低温化が実施できる電子装置の
実装方法を提供することである。特に、本発明の目的
は、リフロー温度の低温化においても接合用合金膜の濡
れ性を充分に確保し、接合不良を防止して歩留まりが向
上できる電子装置の実装方法を提供することである。It is a further object of the present invention to provide a method of mounting an electronic device capable of achieving a lower reflow temperature while achieving the above object. In particular, an object of the present invention is to provide a mounting method of an electronic device capable of ensuring sufficient wettability of a bonding alloy film even at a low reflow temperature, preventing bonding defects, and improving the yield.
【００１１】[0011]
【課題を解決するための手段】上記課題を解決するため
に、この発明の第１の特徴は、電子装置において、外部
端子表面にＰｂを含まないめっき膜を備えたことであ
る。Means for Solving the Problems In order to solve the above problems, a first feature of the present invention is that an electronic device is provided with a plating film containing no Pb on a surface of an external terminal.
【００１２】電子装置には、ＩＣ、ＬＳＩ、パワートラ
ンジスタのいずれかをパッケージ内部に封止した半導体
装置、抵抗素子、容量素子、コイル素子、リレー素子が
いずれも含まれる。外部端子は実装基板の電極に接合用
合金膜により電気的かつ機械的に接続される。外部端子
は例えばアウターリードである。実装基板には、マザー
ボード、ドータボード、ベビーボード、フレキシブル基
板の各種プリント配線基板が含まれる。基本的には、接
合用合金膜のリフローにより電子装置を実装する配線基
板はすべて含まれる。The electronic device includes a semiconductor device in which one of an IC, an LSI, and a power transistor is sealed in a package, a resistor, a capacitor, a coil, and a relay. The external terminals are electrically and mechanically connected to the electrodes of the mounting board by a bonding alloy film. The external terminal is, for example, an outer lead. The mounting board includes various printed wiring boards such as a motherboard, a daughter board, a baby board, and a flexible board. Basically, all wiring boards on which electronic devices are mounted by reflow of the bonding alloy film are included.
【００１３】めっき膜は接合用合金膜の融点温度並びに
再凝固温度よりも低い融点温度を有する。プロセス的表
現をすれば、めっき膜は、接合用合金膜のリフロー前に
おいて接合用合金膜の融点温度よりも低い融点温度を有
する合金膜で形成される。接合用合金膜のリフロー後に
は、めっき膜は合金膜よりも高い再凝固温度を有する接
合用合金膜を形成する（リフローによりめっき膜の合金
成分が含まれても接合用合金膜の融点温度は高い状態で
維持される）。The plating film has a melting point lower than the melting temperature and resolidification temperature of the bonding alloy film. In terms of process expression, the plating film is formed of an alloy film having a melting point lower than that of the bonding alloy film before the reflow of the bonding alloy film. After the reflow of the bonding alloy film, the plating film forms a bonding alloy film having a higher resolidification temperature than the alloy film. (Even if the alloy component of the plating film is included by the reflow, the melting temperature of the bonding alloy film is Maintained high).
【００１４】めっき膜はＳｎとこのＳｎが固溶できる金
属との合金で形成される。好ましくは、めっき膜はＳｎ
と４０〜６０％の範囲内の組成比に設定されたＢｉ、又
は同範囲内の組成比に設定されたＩｎ（インジウム）と
の合金で形成される。Ｂｉ、ＩｎはいずれもＳｎとの合
金膜を生成した時に合金膜の融点温度を下げる働きをす
る。めっき膜に比べて接合用合金膜は体積が大きいの
で、めっき膜が溶融しその合金成分であるＢｉ又はＩｎ
が接合用合金膜に溶け込んでもめっき膜から供給される
Ｂｉ又はＩｎは接合用合金膜においては微量である。従
って、Ｂｉ又はＩｎによる融点温度の低下は極めて小さ
く、接合用合金膜の再凝固温度は合金膜よりも高くな
る。さらに好ましくは、Ｓｎ−４０％Ｂｉ合金、Ｓｎ−
５８％Ｂｉ合金、又はＳｎ−５２％Ｉｎ合金でめっき膜
が形成される。接合用合金膜は、リフロー前において、
例えばＳｎ−３％Ａｇ−４％Ｂｉ合金で形成される。リ
フロー後にはめっき膜の合金成分例えばＢｉが含まれ、
接合用合金膜はＳｎ−３％Ａｇ−５％Ｂｉ合金で形成さ
れる。The plating film is formed of an alloy of Sn and a metal capable of forming a solid solution with Sn. Preferably, the plating film is Sn
And Bi (Indium) set to a composition ratio in the range of 40 to 60% or In (indium) set to a composition ratio in the same range. Both Bi and In function to lower the melting temperature of the alloy film when an alloy film with Sn is formed. Since the volume of the bonding alloy film is larger than that of the plating film, the plating film is melted and the alloy component Bi or In
Is dissolved in the bonding alloy film, but the amount of Bi or In supplied from the plating film is very small in the bonding alloy film. Therefore, the decrease in melting point temperature due to Bi or In is extremely small, and the resolidification temperature of the bonding alloy film is higher than that of the alloy film. More preferably, Sn-40% Bi alloy, Sn-
A plating film is formed of a 58% Bi alloy or a Sn-52% In alloy. Before joining the alloy film for reflow,
For example, it is formed of a Sn-3% Ag-4% Bi alloy. After the reflow, an alloy component of the plating film, for example, Bi is contained,
The bonding alloy film is formed of a Sn-3% Ag-5% Bi alloy.
【００１５】このように構成される電子装置において
は、接合用合金膜のリフローの際に、接合用合金膜の溶
融に先行して外部端子表面のめっき膜が溶融する。接合
用合金膜が溶融し広がる領域にめっき膜が予め溶融し広
がるので、接合用合金膜の濡れ性が向上できる。めっき
膜が溶融することによりこのめっき膜の合金成分が接合
用合金膜に取り込まれるが、接合用合金膜に比べてめっ
き膜の体積は小さいので、接合用合金膜の再凝固温度は
高い状態で維持できる。従って、電子装置においては、
実装基板との間で充分な濡れ性が確保できるので、接合
不良が防止できる。さらに、電子装置において、接合用
合金膜の再凝固温度が高くなるので、電子装置の動作で
発生する熱による接合用合金膜の溶融が防止でき、接合
不良や隣接外部端子間の短絡を防止して電気的信頼性が
向上できる。さらに、接合用合金膜の濡れ性を確保しつ
つ、電子装置の動作で発生する熱に起因する不良の防止
にはＳｎ、Ｂｉ、Ｉｎ、Ａｇのいずかが使用され、有害
物質であるＰｂが使用されない。すなわち、有害物質の
使用が制限でき、環境保護に寄与できる電子装置が実現
できる。In the electronic device configured as described above, when the bonding alloy film is reflowed, the plating film on the surface of the external terminal melts prior to the melting of the bonding alloy film. Since the plating film is melted and spread in advance in the region where the bonding alloy film melts and spreads, the wettability of the bonding alloy film can be improved. When the plating film is melted, the alloy components of the plating film are taken into the bonding alloy film.However, since the volume of the plating film is smaller than that of the bonding alloy film, the re-solidification temperature of the bonding alloy film is high. Can be maintained. Therefore, in an electronic device,
Since sufficient wettability with the mounting substrate can be ensured, bonding failure can be prevented. Further, in the electronic device, the resolidification temperature of the bonding alloy film is increased, so that the bonding alloy film can be prevented from being melted by heat generated by the operation of the electronic device, thereby preventing bonding defects and short circuits between adjacent external terminals. And electrical reliability can be improved. Further, any of Sn, Bi, In, and Ag is used to prevent defects due to heat generated during operation of the electronic device while ensuring the wettability of the bonding alloy film, and Pb which is a harmful substance is used. Is not used. That is, an electronic device that can restrict use of harmful substances and contribute to environmental protection can be realized.
【００１６】この発明の第２の特徴は、電子装置の実装
方法において、下記工程を備えたことである。A second feature of the present invention is that the method for mounting an electronic device includes the following steps.
【００１７】（１）Ｐｂを含まない第１接合用合金膜の
融点温度よりも低い融点温度を有しＰｂを含まない合金
膜で形成されためっき膜を電子装置の外部端子表面に形
成する工程。(1) A step of forming a plating film made of an alloy film not containing Pb and having a melting point lower than that of the first bonding alloy film not containing Pb on the external terminal surface of the electronic device. .
【００１８】（２）実装基板の電極と電子装置の外部端
子との間に第１接合用合金膜を形成する工程。(2) A step of forming a first bonding alloy film between the electrodes of the mounting board and the external terminals of the electronic device.
【００１９】（３）リフローを行い、外部端子表面のめ
っき膜を先行溶融させ、引き続き第２接合用合金膜を溶
融し、めっき膜の合金膜成分によりめっき膜の融点温度
よりも高い再凝固温度を有する第２接合用合金膜を形成
する工程。(3) Reflow is performed to pre-melt the plating film on the surface of the external terminal, and subsequently melt the second bonding alloy film, and the re-solidification temperature higher than the melting point temperature of the plating film due to the alloy film component of the plating film. Forming a second bonding alloy film having the following.
【００２０】Ｐｂを含まないめっき膜は、好ましくはＳ
ｎ−４０％Ｂｉ合金、Ｓｎ−５８％Ｂｉ合金、又はＳｎ
−５２％Ｉｎ合金である。第１接合用合金膜は好ましく
はＳｎ−３％Ａｇ−４％Ｂｉ合金で形成され、第２接合
用合金膜はＳｎ−３％Ａｇ−５％Ｂｉ合金である。The plating film containing no Pb is preferably S
n-40% Bi alloy, Sn-58% Bi alloy, or Sn
-52% In alloy. The first bonding alloy film is preferably formed of a Sn-3% Ag-4% Bi alloy, and the second bonding alloy film is a Sn-3% Ag-5% Bi alloy.
【００２１】このような電子装置の実装方法において
は、有害物質であるＰｂを使用せずに、接合不良が防止
できるので、実装上の歩留まりが向上できる。さらに、
前述のように、めっき膜にはＳｎ−Ｂｉ合金、Ｓｎ−Ｉ
ｎ合金のいずれかが使用され、接合用金属膜にはＳｎ−
Ａｇ−Ｂｉ合金が使用されるので、リフロー温度の低温
化例えば２３０℃以下の低温化が実現できる。リフロー
温度の低温化により樹脂系材料で形成される電子装置や
実装基板に熱的損傷を与えることがなくなるので、実装
上の歩留まりが向上できる。In such an electronic device mounting method, the bonding failure can be prevented without using Pb which is a harmful substance, so that the yield in mounting can be improved. further,
As described above, Sn-Bi alloy, Sn-I
n alloy is used, and the bonding metal film is made of Sn-
Since the Ag-Bi alloy is used, a lower reflow temperature, for example, a lower temperature of 230 ° C. or less can be realized. Since the lowering of the reflow temperature does not cause thermal damage to an electronic device or a mounting substrate formed of a resin-based material, the yield in mounting can be improved.
【００２２】[0022]
【発明の効果】本発明は、Ｐｂの使用を制限し環境保護
を図りつつ、実装基板の電極との間で接合不良や短絡に
よる不良が防止できる電子装置を提供できる。According to the present invention, it is possible to provide an electronic device in which the use of Pb is restricted to protect the environment and prevent a failure due to a bonding failure or a short circuit with an electrode of a mounting substrate.
【００２３】さらに、本発明は、リフロー温度の低温化
が実施できる電子装置の実装方法を提供できる。特に、
本発明は、リフロー温度の低温化においても接合用合金
膜の濡れ性を充分に確保し、接合不良を防止して歩留ま
りが向上できる電子装置の実装方法を提供できる。Further, the present invention can provide a mounting method of an electronic device that can reduce the reflow temperature. Especially,
The present invention can provide a method of mounting an electronic device that can sufficiently secure the wettability of a bonding alloy film even at a low reflow temperature, prevent bonding defects, and improve the yield.
【００２４】[0024]
【発明の実施の形態】（第１の実施の形態）以下、本発
明の実施の形態について説明する。図１は本発明の第１
の実施の形態に係る実装基板に実装した状態（実装後）
の電子装置の断面構造図である。本実施の形態に係る電
子装置はＩＣ、ＬＳＩ、トランジスタのいずれかを搭載
する半導体装置である。図１に示すように、電子装置と
しての半導体装置１は実装基板１０に実装される。DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) An embodiment of the present invention will be described below. FIG. 1 shows the first embodiment of the present invention.
Mounted on the mounting board according to the embodiment (after mounting)
FIG. 2 is a sectional structural view of the electronic device of FIG. The electronic device according to the present embodiment is a semiconductor device on which one of an IC, an LSI, and a transistor is mounted. As shown in FIG. 1, a semiconductor device 1 as an electronic device is mounted on a mounting board 10.
【００２５】半導体装置１は、単結晶珪素からなる半導
体チップ２、半導体チップ２を搭載するタブ部３Ａ、半
導体チップ２と外部機器との間で信号や電源の授受を行
うリード３Ｂ、ボンディングワイヤ４、封止部５を備え
て構成される。The semiconductor device 1 includes a semiconductor chip 2 made of single-crystal silicon, a tab 3A for mounting the semiconductor chip 2, leads 3B for transmitting and receiving signals and power between the semiconductor chip 2 and an external device, and bonding wires 4. And a sealing portion 5.
【００２６】半導体チップ２には、ＩＣ、ＬＳＩ等を構
築する集積回路が、又パワートランジスタが形成され
る。半導体チップ２の表面上にはボンディングパッド２
Ａが配設される。ボンディングパッド２Ａにはボンディ
ングワイヤ４の一端側がボンディングされ、ボンディン
グパッド２Ａとボンディングワイヤ４との間は電気的に
接続される。ボンディングワイヤ４にはＡｕ（金）ワイ
ヤ、Ａｌ（アルミニウム）ワイヤ、Ｃｕ（銅）ワイヤが
実用的に使用できる。On the semiconductor chip 2, an integrated circuit for constructing an IC, an LSI, etc., and a power transistor are formed. Bonding pads 2 on the surface of the semiconductor chip 2
A is provided. One end of the bonding wire 4 is bonded to the bonding pad 2A, and the bonding pad 2A and the bonding wire 4 are electrically connected. As the bonding wire 4, an Au (gold) wire, an Al (aluminum) wire, and a Cu (copper) wire can be practically used.
【００２７】タブ部３Ａ、リード３Ｂは同一のリードフ
レームから切断され、リード３Ｂは切断後に成型され
る。タブ部３Ａ、リード３ＢにはＦｅ−４２％Ｎｉ（鉄
−ニッケル）合金、Ｆｅ−５０％Ｎｉ合金又はＣｕ合金
が実用的に使用できる。リード３Ｂのインナーリード
（リード３Ｂの封止部５内部に配設された部分）にはボ
ンディングワイヤ４の他端側がボンディングされ、イン
ナーリードとボンディングワイヤ４との間は電気的に接
続される。The tab 3A and the lead 3B are cut from the same lead frame, and the lead 3B is molded after cutting. For the tab portion 3A and the lead 3B, a Fe-42% Ni (iron-nickel) alloy, a Fe-50% Ni alloy or a Cu alloy can be practically used. The other end of the bonding wire 4 is bonded to the inner lead of the lead 3B (the portion provided inside the sealing portion 5 of the lead 3B), and the inner lead and the bonding wire 4 are electrically connected.
【００２８】リード３Ｂのアウターリード（リード３Ｂ
の封止部５外部に引き出された部分）はガルウイング形
状で形成され外部端子として使用される。このアウター
リードの表面にはめっき膜６が形成される。めっき膜６
は、リフロー前において接合用合金膜（２０Ａ）の融点
温度よりも低い融点温度を有する合金膜で形成される。
リフロー後には、めっき膜６はこのめっき膜６よりも高
い再凝固温度を有する接合用合金膜（２０）を形成す
る。The outer lead of the lead 3B (lead 3B
The portion drawn out of the sealing portion 5) is formed in a gull wing shape and used as an external terminal. A plating film 6 is formed on the surface of the outer lead. Plating film 6
Is formed of an alloy film having a melting point lower than the melting point of the bonding alloy film (20A) before reflow.
After the reflow, the plating film 6 forms a bonding alloy film (20) having a higher resolidification temperature than the plating film 6.
【００２９】図２はめっき膜６を形成する合金の融点温
度と合金の組成比との関係を示す図である。横軸はＳｎ
が固溶する金属の組成比（％）を示す。縦軸は合金の融
点温度を示す。めっき膜６はＳｎとこのＳｎが固溶でき
る金属との合金で形成され、このめっき膜６にはＰｂが
含まれない。本実施の形態において、Ｓｎが固溶できる
金属はＢｉ又はＩｎである。Ｂｉ、ＩｎはいずれもＳｎ
との合金膜を生成した時に合金膜の融点温度を下げる働
きをする。FIG. 2 is a diagram showing the relationship between the melting point temperature of the alloy forming the plating film 6 and the composition ratio of the alloy. The horizontal axis is Sn
Indicates the composition ratio (%) of the solid solution metal. The vertical axis indicates the melting point temperature of the alloy. The plating film 6 is formed of an alloy of Sn and a metal capable of forming a solid solution with Sn, and the plating film 6 does not include Pb. In the present embodiment, the metal in which Sn can form a solid solution is Bi or In. Bi and In are both Sn
When the alloy film is formed, it functions to lower the melting point temperature of the alloy film.
【００３０】Ｓｎ−Ｂｉ合金においては、Ｂｉの組成比
が３５％を超えると、従来使用されていたＳｎ−３７％
Ｐｂ共晶半田の融点温度よりも低い融点温度が得られ
る。Ｓｎ−Ｉｎ合金においては、Ｉｎの組成比が２５％
を超えると、Ｓｎ−３７％Ｐｂ共晶半田の融点温度より
も低い融点温度が得られる。In the Sn—Bi alloy, if the Bi composition ratio exceeds 35%, the conventionally used Sn—37%
A melting point temperature lower than the melting point temperature of the Pb eutectic solder is obtained. In the Sn-In alloy, the composition ratio of In is 25%.
Is exceeded, a melting point temperature lower than the melting point temperature of the Sn-37% Pb eutectic solder is obtained.
【００３１】本実施の形態において、めっき膜６の融点
温度は、半導体装置１の半導体チップ２に形成された集
積回路やトランジスタの動作で発生する熱では溶融せ
ず、かつリフローにおいては接合用合金膜に先行して溶
融する温度範囲内、具体的には１１０〜１８０℃の温度
範囲内に設定される。従って、めっき膜６はＳｎと４０
〜６０％の範囲内の組成比に設定されたＢｉ、又は同範
囲内の組成比に設定されたＩｎとの合金膜で形成される
ことが実用的である。特に本実施の形態において、めっ
き膜６は、Ｓｎ−４０％Ｂｉ合金膜（融点温度１３９〜
１６５℃）、Ｓｎ−５８％Ｂｉ合金膜（融点温度１３９
℃）、又はＳｎ−５２％Ｉｎ合金膜（融点温度１１７
℃）のいずれかを使用する。In the present embodiment, the melting point temperature of the plating film 6 is not melted by heat generated by the operation of the integrated circuit or transistor formed on the semiconductor chip 2 of the semiconductor device 1, and the bonding alloy is not reflowed. The temperature is set within a temperature range in which the film melts prior to the film, specifically, within a temperature range of 110 to 180 ° C. Therefore, the plating film 6 is composed of Sn and 40
It is practical to be formed of an alloy film with Bi set to a composition ratio in the range of ６０60% or In set to a composition ratio in the same range. In particular, in the present embodiment, the plating film 6 is formed of a Sn-40% Bi alloy film (melting point temperature of 139 to
165 ° C.), Sn-58% Bi alloy film (melting point temperature 139)
° C) or Sn-52% In alloy film (melting point temperature 117
° C).
【００３２】めっき膜６は先付けで形成され、封止部５
を形成する前にリードフレームの状態においてリード３
Ｂのアウターリードの表面に形成される。めっき膜６は
電解めっき法、無電解めっき法又はディプ法で形成さ
れ、例えば１〜２０μｍ程度の薄い膜厚で形成される。
なお、めっき膜６は封止部５を形成した後に行う後付け
で形成してもよい。The plating film 6 is formed in advance, and the sealing portion 5 is formed.
Before forming the lead 3 in the state of the lead frame.
B is formed on the surface of the outer lead. The plating film 6 is formed by an electrolytic plating method, an electroless plating method, or a dip method, and is formed with a thin film thickness of, for example, about 1 to 20 μm.
In addition, the plating film 6 may be formed by post-installation performed after forming the sealing portion 5.
【００３３】封止部５は本実施の形態においてトランス
ファーモールド法で形成された樹脂パッケージで形成さ
れる。樹脂パッケージにはエポキシ系樹脂が実用的に使
用できる。In the present embodiment, the sealing portion 5 is formed by a resin package formed by the transfer molding method. An epoxy resin can be practically used for the resin package.
【００３４】一方、実装基板１０は基板本体１１上に電
極１２及び図示しない配線を配設する。実装基板１０に
は、マザーボード、ドータボード、ベビーボード、フレ
キシブル基板の各種プリント配線基板が含まれる。基本
的には、接合用合金膜のリフローにより半導体装置１を
実装する配線基板はすべて含まれる。On the other hand, the mounting substrate 10 has electrodes 12 and wiring (not shown) disposed on a substrate main body 11. The mounting board 10 includes various printed wiring boards such as a motherboard, a daughter board, a baby board, and a flexible board. Basically, all wiring boards on which the semiconductor device 1 is mounted by reflow of the bonding alloy film are included.
【００３５】実装基板１０の基板本体１１は本実施の形
態においてエポキシ系樹脂で形成される。フレキシブル
基板の場合にはポリイミド系樹脂が実用的に使用され
る。電極１２（及び図示しない配線）は例えばＣｕ薄膜
で形成される。The board main body 11 of the mounting board 10 is formed of an epoxy resin in the present embodiment. In the case of a flexible substrate, a polyimide resin is practically used. The electrode 12 (and the wiring (not shown)) is formed of, for example, a Cu thin film.
【００３６】前述の半導体装置１のアウターリード（リ
ード３Ｂ）と実装基板１０の電極１２との間は接合用合
金膜２０により電気的に接続されかつ機械的に接合され
る。本実施の形態において、接合用合金膜２０はＰｂを
含まないＳｎ−３％Ａｇ−５％Ｂｉ合金膜（Ｂｉの組成
比はリフロー後の値であり、リフロー前のＢｉの組成比
は４％に設定される。）で形成される。このＳｎ−３％
Ａｇ−５％Ｂｉ合金膜は図２に示すように約２１０℃の
融点温度（再凝固温度）を有し、この融点温度は現状使
用されている２３０℃のリフロー温度よりも低く、Ｓｎ
−３７％Ｐｂ共晶半田の融点温度よりも高い。接合用合
金膜２０は、めっき膜６のリフローで溶融される部分の
体積に比べて大きな体積で形成され、体積で数十倍程度
の膜厚で形成される。接合用合金膜２０は例えばスクリ
ーン印刷により実装基板１０の電極１２上に形成され
る。The outer leads (leads 3B) of the semiconductor device 1 and the electrodes 12 of the mounting substrate 10 are electrically connected and mechanically bonded by the bonding alloy film 20. In this embodiment, the bonding alloy film 20 is a Sn-3% Ag-5% Bi alloy film containing no Pb (the composition ratio of Bi is a value after reflow, and the composition ratio of Bi before reflow is 4%). Is set to.). This Sn-3%
As shown in FIG. 2, the Ag-5% Bi alloy film has a melting point temperature (resolidification temperature) of about 210 ° C., which is lower than the currently used reflow temperature of 230 ° C.
It is higher than the melting point temperature of -37% Pb eutectic solder. The bonding alloy film 20 is formed with a larger volume than the volume of a portion of the plating film 6 that is melted by reflow, and is formed with a thickness of about several tens times in volume. The bonding alloy film 20 is formed on the electrode 12 of the mounting substrate 10 by, for example, screen printing.
【００３７】次に、前述の半導体装置１の実装方法につ
いて説明する。図３乃至図５は実装方法を説明するため
の工程図である。Next, a method of mounting the above-described semiconductor device 1 will be described. 3 to 5 are process diagrams for explaining a mounting method.
【００３８】（１）まず、図３に示すように、リード３
Ｂのアウターリード表面にめっき膜６が形成された半導
体装置１を準備する。この実装方法の説明において、め
っき膜６にはＰｂを含まないＳｎ−５８％Ｂｉ合金膜が
使用される。このＳｎ−５８％Ｂｉ合金膜の融点温度は
１３９℃である。(1) First, as shown in FIG.
The semiconductor device 1 having the plating film 6 formed on the outer lead surface of B is prepared. In the description of this mounting method, an Sn-58% Bi alloy film containing no Pb is used for the plating film 6. The melting point temperature of this Sn-58% Bi alloy film is 139 ° C.
【００３９】（２）一方、図４に示すように、実装基板
１０の電極１２の表面上に接合用合金膜２０Ａを形成す
る。接合用合金膜２０ＡはＰｂを含まないＳｎ−３％Ａ
ｇ−４％Ｂｉ合金膜で形成される。このＳｎ−３％Ａｇ
−４％Ｂｉ合金膜の融点温度は２１０℃である。(2) On the other hand, as shown in FIG. 4, a bonding alloy film 20A is formed on the surface of the electrode 12 of the mounting substrate 10. The bonding alloy film 20A is composed of Sn-3% A containing no Pb.
g-4% Bi alloy film. This Sn-3% Ag
The melting point temperature of the −4% Bi alloy film is 210 ° C.
【００４０】（３）図５に示すように、実装基板１０上
に半導体装置１を積載し、位置合わせを行う。実装基板
１０の電極１２上に半導体装置１のアウターリードが配
置され、この電極１２とアウターリードとの間に接合用
合金膜２０Ａ及びめっき膜６が介在する。(3) As shown in FIG. 5, the semiconductor device 1 is mounted on the mounting substrate 10 and the alignment is performed. The outer leads of the semiconductor device 1 are arranged on the electrodes 12 of the mounting substrate 10, and the bonding alloy film 20A and the plating film 6 are interposed between the electrodes 12 and the outer leads.
【００４１】（４）リフローを行い、前述の図１に示す
ように、めっき膜６及び接合用合金膜２０Ａを溶融し、
これを再凝固させることにより接合用合金膜２０を形成
する。この接合用合金膜２０の形成により電極１２とア
ウターリードとの間が電気的に接続されかつ機械的に接
合される。(4) Reflow is performed to melt the plating film 6 and the bonding alloy film 20A as shown in FIG.
This is re-solidified to form the bonding alloy film 20. By forming the bonding alloy film 20, the electrode 12 and the outer lead are electrically connected and mechanically bonded.
【００４２】図６はリフロー時間とリフロー温度との関
係を示す図である。横軸はリフロー時間を示す。縦軸は
リフロー温度を示す。図６に示すように、リフローが開
始されると徐々に温度が上昇し、１３９℃の温度に達し
た時点でアウターリード表面に形成しためっき膜６が先
行して溶融される。めっき膜６の溶融物は接合領域に広
がる。FIG. 6 is a diagram showing the relationship between the reflow time and the reflow temperature. The horizontal axis indicates the reflow time. The vertical axis indicates the reflow temperature. As shown in FIG. 6, when the reflow starts, the temperature gradually rises, and when the temperature reaches 139 ° C., the plating film 6 formed on the outer lead surface is melted in advance. The molten material of the plating film 6 spreads to the bonding area.
【００４３】さらに温度が上昇し、２１０℃の温度に達
した時点で接合用合金膜２０Ａが溶融される。予めめっ
き膜６が溶融されているので、接合用合金膜２０Ａの溶
融物は容易に広がり、この溶融物の濡れ性は極めて良好
である。When the temperature further rises and reaches a temperature of 210 ° C., the bonding alloy film 20A is melted. Since the plating film 6 is previously melted, the melt of the bonding alloy film 20A spreads easily, and the wettability of the melt is extremely good.
【００４４】そして、一旦、リフローの最高温度２３０
℃まで達した後、徐々に温度を下げる。２１０℃まで温
度が下がると、接合用合金膜２０Ａの溶融物が再凝固
し、めっき膜６の合金成分が吸収された（混合された）
接合用合金膜２０が形成される。接合用合金膜２０はめ
っき膜６の体積に比べて大きい体積を有するので、めっ
き膜６が溶融しその合金成分であるＢｉが接合用合金膜
２０に溶け込んでもめっき膜６から供給されるＢｉ量は
接合用合金膜２０において微量である。具体的には、接
合用合金膜２０はＳｎ−３％Ａｇ−５％Ｂｉ合金膜で形
成され、温度降下を促進するＢｉ量は約１％しか増加し
ない。従って、Ｂｉによる融点温度の低下は極めて小さ
く、接合用合金膜２０の再凝固温度は約２１０℃の温度
で維持されめっき膜６の融点温度に比べて高くなる。Then, once the maximum reflow temperature 230
After reaching ℃, gradually lower the temperature. When the temperature was lowered to 210 ° C., the melt of the bonding alloy film 20A was re-solidified, and the alloy component of the plating film 6 was absorbed (mixed).
The bonding alloy film 20 is formed. Since the bonding alloy film 20 has a larger volume than the plating film 6, the amount of Bi supplied from the plating film 6 even when the plating film 6 is melted and Bi as an alloy component dissolves in the bonding alloy film 20. Is very small in the bonding alloy film 20. Specifically, the bonding alloy film 20 is formed of a Sn-3% Ag-5% Bi alloy film, and the amount of Bi that promotes the temperature drop increases by only about 1%. Accordingly, the decrease in the melting point temperature due to Bi is extremely small, and the resolidification temperature of the bonding alloy film 20 is maintained at a temperature of about 210 ° C., which is higher than the melting point temperature of the plating film 6.
【００４５】再凝固により接合用合金膜２０が形成さ
れ、所定温度まで降下した時点でリフローが終了し、半
導体装置１の実装基板１０への実装が終了する。The alloy film 20 for bonding is formed by the re-solidification. When the temperature reaches a predetermined temperature, the reflow is completed, and the mounting of the semiconductor device 1 on the mounting substrate 10 is completed.
【００４６】このように構成される半導体装置１におい
ては、接合用合金膜２０Ａのリフローの際に、接合用合
金膜２０Ａの溶融に先行してアウターリード表面のめっ
き膜６が溶融する。接合用合金膜２０Ａが溶融し広がる
領域にめっき膜６が予め溶融し広がるので、接合用合金
膜２０Ａの濡れ性が向上できる。めっき膜６が溶融する
ことによりこのめっき膜６の合金成分が凝固後の接合用
合金膜２０に取り込まれるが、接合用合金膜２０Ａの体
積に比べてめっき膜６の体積は小さいので、接合用合金
膜２０の再凝固温度は高い状態で維持できる。従って、
半導体装置１においては、実装基板１０との間で充分な
濡れ性が確保できるので、接合不良が防止できる。さら
に、半導体装置１において、接合用合金膜２０の再凝固
温度が高くなるので、半導体装置１の動作で発生する熱
による接合用合金膜２０の溶融が防止でき、接合不良や
隣接アウターリード間の短絡を防止して電気的信頼性が
向上できる。さらに、接合用合金膜２０Ａの濡れ性を確
保しつつ、半導体装置１の動作で発生する熱に起因する
不良の防止にはＳｎ、Ｂｉ、Ｉｎ、Ａｇのいずれかが使
用され、有害物質であるＰｂが使用されない。すなわ
ち、有害物質の使用が制限でき、環境保護に寄与できる
半導体装置１が実現できる。In the semiconductor device 1 thus configured, when the bonding alloy film 20A is reflowed, the plating film 6 on the outer lead surface melts before the bonding alloy film 20A melts. Since the plating film 6 is melted and spread in advance in the region where the bonding alloy film 20A melts and spreads, the wettability of the bonding alloy film 20A can be improved. When the plating film 6 is melted, the alloy component of the plating film 6 is taken into the solidified bonding alloy film 20. However, since the volume of the plating film 6 is smaller than the volume of the bonding alloy film 20 </ b> A, The resolidification temperature of the alloy film 20 can be maintained at a high state. Therefore,
In the semiconductor device 1, since sufficient wettability with the mounting substrate 10 can be ensured, poor bonding can be prevented. Furthermore, in the semiconductor device 1, since the resolidification temperature of the bonding alloy film 20 is increased, the melting of the bonding alloy film 20 due to heat generated by the operation of the semiconductor device 1 can be prevented, resulting in poor bonding and a gap between adjacent outer leads. Short circuit can be prevented and electrical reliability can be improved. Further, any one of Sn, Bi, In, and Ag is used to prevent defects caused by heat generated during operation of the semiconductor device 1 while ensuring the wettability of the bonding alloy film 20A, and is a harmful substance. Pb is not used. That is, the semiconductor device 1 which can restrict use of harmful substances and contribute to environmental protection can be realized.
【００４７】さらに、半導体装置１の実装方法において
は、有害物質であるＰｂを使用せずに、接合不良が防止
できるので、実装上の歩留まりが向上できる。さらに、
前述のように、めっき膜にはＳｎ−Ｂｉ合金、Ｓｎ−Ｉ
ｎ合金のいずれかが使用され、接合用金属膜２０Ａには
Ｓｎ−Ａｇ−Ｂｉ合金が使用されるので、リフロー温度
の低温化例えば２３０℃以下の低温化が実現できる。リ
フロー温度の低温化により樹脂系材料で形成される半導
体装置１の封止部５や実装基板１０の基板本体１１に熱
的損傷を与えることがなくなるので、実装上の歩留まり
が向上できる。Further, in the method of mounting the semiconductor device 1, the bonding failure can be prevented without using Pb which is a harmful substance, so that the yield in mounting can be improved. further,
As described above, Sn-Bi alloy, Sn-I
Since one of the n alloys is used and the Sn—Ag—Bi alloy is used for the bonding metal film 20A, the reflow temperature can be lowered, for example, 230 ° C. or lower. Since the sealing portion 5 of the semiconductor device 1 formed of a resin material and the substrate main body 11 of the mounting substrate 10 are not thermally damaged by lowering the reflow temperature, the yield in mounting can be improved.
【００４８】（第２の実施の形態）本実施の形態は、他
の外部端子構造を有する半導体装置、抵抗素子、容量素
子、コイル素子、リレー素子のそれぞれに本発明を適用
した例を説明するものである。図７は本発明の第２の実
施の形態に係る半導体装置の構成図、図８は抵抗素子等
の電子装置の構成図である。(Second Embodiment) In this embodiment, an example in which the present invention is applied to a semiconductor device having another external terminal structure, a resistor, a capacitor, a coil, and a relay will be described. Things. FIG. 7 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention, and FIG. 8 is a configuration diagram of an electronic device such as a resistance element.
【００４９】図７に示す半導体装置１においては、リー
ド３Ｂのアウターリードが封止部５の表面に沿って引き
出される。前述の第１の実施の形態に係る半導体装置１
と同様に、アウターリード表面にはめっき膜６が形成さ
れる。In the semiconductor device 1 shown in FIG. 7, the outer leads of the leads 3B are drawn out along the surface of the sealing portion 5. Semiconductor device 1 according to the above-described first embodiment
Similarly, the plating film 6 is formed on the outer lead surface.
【００５０】図８に示す電子装置３０においては、封止
部３１の外部に外部端子３２が配設される。封止部３１
の内部には、図示しないが、抵抗素子、容量素子、コイ
ル素子、又はリレー素子が封止される。外部端子３２の
表面には、前述の第１の実施の形態に係る半導体装置１
と同様に、めっき膜３３が形成される。In the electronic device 30 shown in FIG. 8, an external terminal 32 is provided outside the sealing portion 31. Sealing part 31
Although not shown, a resistance element, a capacitance element, a coil element, or a relay element is sealed inside. On the surface of the external terminal 32, the semiconductor device 1 according to the first embodiment described above is provided.
Similarly, a plating film 33 is formed.
【００５１】このように構成される図７に示す半導体装
置１、図８に示す電子装置３０においては、いずれも前
述の第１の実施の形態に係る半導体装置１で得られる効
果と同様の効果が得られる。In the semiconductor device 1 shown in FIG. 7 and the electronic device 30 shown in FIG. 8, the same effects as those obtained by the semiconductor device 1 according to the first embodiment are obtained. Is obtained.
【００５２】（応用例）本発明は前述の実施の形態に限
定されない。例えば、本発明は、実装基板に突起電極
（バンプ電極）を介してフリップチップ方式で実装され
る半導体装置に適用できる。すなわち、前述の図１に示
す半導体チップ２のボンディングパッド（外部端子）２
Ｂにめっき膜６が形成する。めっき膜６にはＰｂを含ま
ないＳｎ−Ｂｉ合金膜又はＳｎ−Ｉｎ合金膜が使用され
る。突起電極にはＰｂを含まないＳｎ−Ａｇ−Ｂｉ合金
が使用される。リフローにより突起電極が溶融するが、
これに先行してめっき膜６が溶融し、突起電極の濡れ性
が向上できる。(Application Example) The present invention is not limited to the above embodiment. For example, the present invention can be applied to a semiconductor device which is mounted on a mounting substrate by a flip-chip method via bump electrodes (bump electrodes). That is, the bonding pads (external terminals) 2 of the semiconductor chip 2 shown in FIG.
The plating film 6 is formed on B. As the plating film 6, a Sn—Bi alloy film or a Sn—In alloy film containing no Pb is used. An Sn-Ag-Bi alloy containing no Pb is used for the protruding electrodes. The protruding electrode melts due to reflow,
Prior to this, the plating film 6 is melted, and the wettability of the protruding electrodes can be improved.
【図１】本発明の第１の実施の形態に係る実装基板に実
装した状態の電子装置の断面構造図である。FIG. 1 is a sectional structural view of an electronic device mounted on a mounting board according to a first embodiment of the present invention.
【図２】第１の実施の形態に係るめっき膜を形成する合
金の融点温度と合金の組成比との関係を示す図である。FIG. 2 is a diagram illustrating a relationship between a melting point temperature of an alloy forming a plating film and a composition ratio of the alloy according to the first embodiment.
【図３】第１の実施の形態に係る実装方法を説明するた
めの工程図である。FIG. 3 is a process diagram for explaining the mounting method according to the first embodiment.
【図４】第１の実施の形態に係る実装方法を説明するた
めの工程図である。FIG. 4 is a process chart for explaining the mounting method according to the first embodiment.
【図５】第１の実施の形態に係る実装方法を説明するた
めの工程図である。FIG. 5 is a process diagram for describing the mounting method according to the first embodiment.
【図６】第１の実施の形態に係るリフロー時間とリフロ
ー温度との関係を示す図である。FIG. 6 is a diagram showing a relationship between a reflow time and a reflow temperature according to the first embodiment.
【図７】本発明の第２の実施の形態に係る半導体装置の
構成図である。FIG. 7 is a configuration diagram of a semiconductor device according to a second embodiment of the present invention.
【図８】本発明の第２の実施の形態に係る電子装置の構
成図である。FIG. 8 is a configuration diagram of an electronic device according to a second embodiment of the present invention.
１ 半導体装置 ２ 半導体チップ ３Ｂ リード ５，３１ 封止部 ６，３３ めっき膜 １０ 実装基板 １２ 電極 ２０，２０Ａ 接合用合金膜 ３０ 電子装置 ３２ 外部端子 DESCRIPTION OF SYMBOLS 1 Semiconductor device 2 Semiconductor chip 3B Lead 5,31 Sealing part 6,33 Plating film 10 Mounting substrate 12 Electrode 20,20A Bonding alloy film 30 Electronic device 32 External terminal
フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０５Ｋ 3/24 Ｈ０５Ｋ 3/24 Ｂ Continued on the front page (51) Int.Cl. 6 Identification code FI H05K 3/24 H05K 3/24 B
Claims (5)
気的かつ機械的に接続される外部端子と、 前記外部端子表面に形成され、前記接合用合金膜の融点
温度並びに再凝固温度よりも低い融点温度を有し、Ｐｂ
を含まない合金膜で形成されためっき膜と、 を備えたことを特徴とする電子装置。1. An external terminal electrically and mechanically connected to an electrode of a mounting board by a bonding alloy film, wherein the external terminal is formed on a surface of the external terminal, and has a melting point temperature and a re-solidification temperature of the bonding alloy film lower than the melting temperature and the resolidification temperature of the bonding alloy film. Pb with low melting point temperature
An electronic device comprising: a plating film formed of an alloy film containing no.
温度よりも低い融点温度を有しかつＰｂを含まない合金
膜で形成されためっき膜を電子装置の外部端子表面に形
成する工程と、 実装基板の電極と前記電子装置の外部端子との間に前記
第１接合用合金膜を形成する工程と、 リフローを行い、前記外部端子表面のめっき膜を先行溶
融させ、引き続き前記第１接合用合金膜を溶融し、前記
めっき膜の合金成分によりめっき膜の融点温度よりも高
い再凝固温度を有する第２接合用合金膜を形成する工程
と、 を備えたことを特徴とする電子装置の実装方法。2. A step of forming, on an external terminal surface of an electronic device, a plating film having a melting point lower than that of a first bonding alloy film not containing Pb and formed of an alloy film not containing Pb. Forming the first bonding alloy film between the electrode of the mounting board and the external terminal of the electronic device; performing reflow to pre-melt the plating film on the surface of the external terminal; Melting the bonding alloy film and forming a second bonding alloy film having a re-solidification temperature higher than the melting temperature of the plating film by the alloy component of the plating film. How to implement.
ことを特徴とする請求項１記載の電子装置。3. The electronic device according to claim 1, wherein the plating film is formed of an alloy of Sn and a metal capable of forming a solid solution with Sn.
ｉ、又は同範囲内の組成比に設定されたＩｎとの合金で
形成されたことを特徴とする請求項３に記載の電子装
置。4. The plating film according to claim 1, wherein the composition ratio of Sn and B is set to a composition ratio in a range of 40 to 60%.
4. The electronic device according to claim 3, wherein the electronic device is formed of i or an alloy with In set to a composition ratio in the same range.
金、Ｓｎ−５８％Ｂｉ合金、又はＳｎ−５２％Ｉｎ合金
で形成され、 前記第１接合用合金膜は、Ｓｎ−３％Ａｇ−４％Ｂｉ合
金で形成され、 前記第２接合用合金膜は、Ｓｎ−３％Ａｇ−５％Ｂｉ合
金で形成されたことを特徴とする請求項４に記載の電子
装置。5. The plating film is formed of a Sn-40% Bi alloy, a Sn-58% Bi alloy, or a Sn-52% In alloy, and the first bonding alloy film is formed of a Sn-3% Ag- 5. The electronic device according to claim 4, wherein the second bonding alloy film is formed of a 4% Bi alloy, and the second bonding alloy film is formed of a Sn-3% Ag-5% Bi alloy. 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10122205A JPH11317487A (en) | 1998-05-01 | 1998-05-01 | Electronic device and mounting method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10122205A JPH11317487A (en) | 1998-05-01 | 1998-05-01 | Electronic device and mounting method therefor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11317487A true JPH11317487A (en) | 1999-11-16 |
Family
ID=14830161
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10122205A Pending JPH11317487A (en) | 1998-05-01 | 1998-05-01 | Electronic device and mounting method therefor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11317487A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005116300A1 (en) * | 2004-05-25 | 2005-12-08 | Shinko Electric Industries Co., Ltd. | External palladium plating structure of semiconductor component and semiconductor device manufacturing method |
| JP2006294600A (en) * | 2005-03-15 | 2006-10-26 | Matsushita Electric Ind Co Ltd | Conductive adhesive |
| EP2521429A4 (en) * | 2009-12-28 | 2016-08-31 | Senju Metal Industry Co | Method for soldering surface-mount component and surface-mount component |
-
1998
- 1998-05-01 JP JP10122205A patent/JPH11317487A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005116300A1 (en) * | 2004-05-25 | 2005-12-08 | Shinko Electric Industries Co., Ltd. | External palladium plating structure of semiconductor component and semiconductor device manufacturing method |
| JP2006294600A (en) * | 2005-03-15 | 2006-10-26 | Matsushita Electric Ind Co Ltd | Conductive adhesive |
| EP2521429A4 (en) * | 2009-12-28 | 2016-08-31 | Senju Metal Industry Co | Method for soldering surface-mount component and surface-mount component |
| US10297539B2 (en) | 2009-12-28 | 2019-05-21 | Senju Metal Industry Co., Ltd. | Electronic device including soldered surface-mount component |
| US10354944B2 (en) | 2009-12-28 | 2019-07-16 | Senju Metal Industry Co., Ltd. | Method for soldering surface-mount component and surface-mount component |
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