JPH11317473A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent mismatchings caused by the difference in the expansion coefficient of a materials for constituting a package by forming an area between a semiconductor chip and a cooling part and the entire surface of the semiconductor chip in a structure which is covered with a specific soft material. SOLUTION: Since a chip 1 and a wiring layer are connected by a soft material, such as elastomers 3, 5 and 8 for connecting members, a bonding wire 7 in a loop is used for absorbing the displacement of each rigid body. Also, since epoxy potting with strong stiffness cannot be used due to the similar reasons for sealing, recently potting is made by using silicon gel that has been highly regarded as a reliable sealing material as a coating gel 11. Also, for soft material, namely the elastomers 3, 5, and 8 and the coating gel 11, a materials with an coefficient of elasticity of 0.001-100 kg/mm<2> , preferably 0.01-10 kg/mm<2> , is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sealing technology for an LSI having a plastic pin grid array (PPGA) structure, and more particularly to a technology effective for performing air-cooled heat radiation without impairing signal propagation characteristics. It is about.

[0002]

2. Description of the Related Art In a semiconductor device, the number of pins (or leads) for connection to an external circuit increases as the mounting density increases. PGA has a package structure that enables multi-pins and can be mounted on a conventional printed circuit board.
(Pin grid array).

Conventionally, ceramics have been used for PGA packages, and sintered metals have been used for wiring materials. However, ceramics have a high cost and a high dielectric constant, and therefore have a capacitance between lines for wiring. In addition, since the sintered metal has a high electric resistance, a series resistance component is included in a power supply and a signal wiring. For this reason, in the power supply system, a loss occurs due to the resistance, and in the signal system, a signal delay occurs due to the capacitance of ceramic and the electric resistance of the wiring.

Therefore, Nikkei Electronics, “Separate Volume No.
2 Micro Devices, 1984.6.11, P160
-P168, attention has been paid to plastic PGA which can be reduced in cost in place of ceramic, and ASIC
(Apllication Specific IC)
Applications are expanding. The package base is made of a material having a low dielectric constant, such as glass fiber-containing epoxy, triazine, or polyimide, which is also a printed circuit board material, and copper having a low electric resistance is used for wiring.

[0005] It should be noted that techniques relating to such PPGA are disclosed in, for example, Japanese Patent Application Laid-Open Nos. 60-38841 and 60-8841.
No. -38842.

[0006]

However, in the packaging technology using plastic as described above, the thermal conductivity of plastic is lower than that of ceramic, so that the semiconductor chip is cooled against high heat generation due to high integration, and the signal is reduced. High speed propagation cannot be satisfied.

Japanese Patent Application Laid-Open No. 60-136348 discloses a technique for coping with the high heat generation of a semiconductor device. That is, a hole is formed in the LSI mounting portion of the organic printed board material, a board having good thermal conductivity is attached to the back surface of the printed board, and the LSI is attached to the good heat conducting board through the hole in the surface. However, in this structure, the difference in thermal expansion of each member is larger than that in the case of using ceramics, and if no measures are taken for joining, the members will be broken.

Further, a plastic pin grid grid for mounting an LSI on a substrate made of glass epoxy resin.
Japanese Patent Application Laid-Open No. 60-136345 discloses the use of an elastomer in an array package to eliminate a difference in thermal expansion between adhesives between joints. However, elastomers have poor thermal conductivity and have problems with heat dissipation measures.

[0009] Further, since the elastomer has a structure having many air bubbles, moisture easily penetrates compared to the epoxy-based adhesive.
There is a problem that the wiring in the cavity is corroded.

Further, in order to facilitate heat dissipation, it is desirable to be able to perform cooling by natural air cooling or a wind speed of several m / S. However, conventionally, when a semiconductor device has a power of several tens of watts, sufficient heat dissipation cannot be expected.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sealing technique capable of cooling a semiconductor device of several tens of watts while guaranteeing high-speed signal propagation characteristics.

Another object of the present invention is to provide a package structure having low cost, high reliability and high performance by combining a package made of a normal printed circuit board with a heat spreader made of a cheap material. It is in.

Still another object of the present invention is to bond or cover various inconsistencies resulting from the characteristics of the structural material with a soft material, thereby making it possible to freely combine materials by making the material characteristic relationships independent, and to achieve a low material combination. It is intended to provide a technology without sacrificing reliability and performance at a cost.

The above objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A semiconductor device comprising a semiconductor chip, a heat dissipating part for mounting the semiconductor chip, and at least one wiring layer, the end of which is disposed near the semiconductor chip, the semiconductor device comprising a plastic substrate. The elastic modulus between 0.001 and 100 kg / mm
^The structure is covered with a soft material.

(2) The heat radiating portion includes a heat diffusion plate to which a semiconductor chip is bonded and a heat sink bonded to the heat diffusion plate via an adhesive made of the soft material. ).

According to the above-mentioned means (1), by joining the semiconductor chip with a soft material, it is possible to prevent mismatching caused by a difference in expansion coefficient of the material constituting the package. Also, by coating the entire chip,
It is possible to prevent moisture from intruding into the chip and to prevent misalignment in the same manner as with the bonding agent described above. Therefore, the reliability of the plastic pin grid array package can be improved.

According to the above means (2), the semiconductor chip is mounted on the heat diffusion plate, a heat sink is mounted on the opposite surface, and a plastic substrate is provided around the semiconductor chip with the semiconductor chip exposed. This is joined to the heat diffusion plate. As a result, the heat generated in the semiconductor chip is quickly transmitted to the heat sink via the heat diffusion plate,
The plastic substrate containing each wiring layer minimizes the capacitance between lines, inductance and resistance on wiring, and prevents deterioration of signal propagation characteristics. Therefore, sufficient heat radiation can be performed using the plastic package without deteriorating the signal propagation characteristics.

[0020]

(Embodiment 1) FIG. 1 is a sectional view showing an example of a semiconductor device according to the present invention.

The LSI chip 1 is joined to a pedestal formed at the center of the heat diffusion plate 2 via a rubber-like elastic elastomer 3 containing a filler having good thermal conductivity. The heat diffusion plate 2 is formed in a square or rectangular shape using a copper material or the like, the pedestal portion is made thicker than other portions, and the opposite surface is made flat.

Around the chip 1, a wiring board 4 made of plastic, glass epoxy, or the like, and having a multi-layered wiring is provided via a soft material, for example, an elastomer 5 containing a filler having good thermal conductivity. Heat diffusion plate 2
Is joined to. The wiring board 4 has an opening in the center thereof, and the pedestal portions of the chip 1 and the heat diffusion plate 2 are located in the opening. The heat diffusion plate 2 has substantially the same external dimensions as the wiring board 4 and increases the heat radiation area of the chip 1. A large number of pins 6 (electrodes) are embedded in the wiring board 4 at regular intervals, and each is connected to a wiring in the wiring board 4. This pin 6 is erected by soldering or caulking, and its material is Be-C, which has a high elastic deformation limit.
u or the like is used. Incidentally, conventionally, 42 alloy, phosphor bronze, and the like have been used.

The inner end of the wiring board 4 is stepped, and the wiring is exposed on the surface of each step, and a bonding wire 7 made of gold, copper or aluminum is provided between the wiring and the wiring on the chip 1. Connected (TAB (tape automated bonding) may be used instead of the bonding wire 7).

Fins 9 (heat sinks) are joined to the upper surface of the heat diffusion plate 2 (the surface on which the chip 1 is not provided) via a soft material, for example, an elastomer 8. The fins 9 are made of an aluminum material having excellent thermal conductivity, and are further formed with a plurality of deep grooves so as to increase a heat radiation area. If the elastomer 8 contains a filler having good thermal conductivity, which will be described later, the heat radiation effect is further improved.

Further, the cap 10 is made of a soft material such as an elastomer 12 to protect the exposed surface of the chip 1 and a part of the adjacent wiring board 4, that is, the electrode exposed from the inner end of the wiring board 4. 4. Any of the above-mentioned elastomers including the elastomer 12 is provided to absorb a difference in thermal expansion between members to be joined.

In order to prevent the chip 1, the electrodes exposed from the side ends of the wiring board 4 and the bonding wires 7 from being affected by moisture entering from an elastomer 12 joining the wiring board 4 and the cap 10, a coating gel 1 is formed.
Protected by 1. This coating gel 11
Is preferably a material that prevents wire breakage and moisture intrusion. Between the heat diffusion plate 2 and the wiring board 4 or between the wiring board 4 and the cap 1
In the case where the gaps are bonded by an elastomer, covering not only the surface of the chip 1 but also the side surface of the chip 1 with a moisture-resistant silicone gel can prevent Al corrosion of the bonding pad due to invasion of moisture. This is because bubbles may remain in the elastomer when the elastomer is cured, and this may be a path for water to enter.

The coating gel 11 is made of, for example, a material having an elastic modulus of 100 kgf / mm ² or less, silicone, polyurethane, or another gel-like material having a coefficient of thermal expansion of 20 × 10
A material filled with fused silica or alumina at a temperature of ^-6 / ° C or lower, or a silicon-modified phenol-curable epoxy resin can be used.

Table 1 shows the thermal expansion coefficient and the thermal conductivity of the materials used in the above-mentioned parts.

[0029]

[Table 1]

As is clear from Table 1, copper, which is a material considered as the thermal diffusion plate 2 as compared with silicon, has a larger coefficient of thermal expansion. Aluminum, which is the main structural material of the fin 9, is even larger. Also, glass-filled epoxy, glass-filled polyimide, glass-filled bismaleid triazine, etc., which are considered low dielectric constant materials,
Similarly, the thermal expansion coefficient is larger than that of silicon. If AlN or Cu / Mo / Cu clad material is used for the heat diffusion plate 2, the matching with silicon is good, but the problem with matching with other constituent materials remains.

However, in the present invention, since the easily deformable elastomer is used for the mutual joining between the mismatched materials, the above-mentioned problem of the alignment is solved. However, soft materials,
For example, since the thermal conductivity of an elastomer is poor, it is desirable to form the layer as thin as possible, or to mix a filler having a good thermal conductivity as shown in Table 1.

When a methylphenylphenylsiloxane rubber containing alumina filler (for example, trade name “Toray SE-4400”) is used as the elastomer, the elongation of the tensile breaking limit value is 100%, and it is estimated that the safety factor is 50%. A design distortion of 50% is obtained. Further, there is a methylphenylphenylsiloxane gel (for example, trade name “Toray JCR6110”) having a large breaking elongation, and its breaking elongation is 200%, so that 100% is obtained as a design strain. Tables 2 and 3 show the preferred package materials designed based on this premise. Here, the configuration shown in FIG. 1 was used, and a package having a chip size of 14.5 mm square was used, the fin size was 60 mm square, and the thickness of the heat diffusion plate 2 was 1 mm. Fin shape, height 18mm, fin spacing 4mm,
Air cooling was performed at a wind speed of 1 m / sec. Also, the displacement is
The value at 150 ° C. (ΔT = 205 ° C.).

[0033]

[Table 2]

[0034]

[Table 3]

Table 2 shows the case where the copper heat diffusion plate 2 is used. The displacement at the maximum temperature difference of 205 ° C. in the temperature cycle between the silicon chip and the 14.5 mm square silicon chip is 21 μm. Assuming that the design distortion is 100% of the gel, the adhesive thickness is 2
The thickness was set to 1 μm or more, and set to 25 μm in the first embodiment. On the other hand, the displacement of the copper heat diffusion plate of 60 mm square and the aluminum fin at 205 ° C. was 40 μm, and the displacement of rubber was 50 μm.
The rubber thickness becomes 100 μm from the% design distortion amount. Under these conditions, when the respective thermal resistances are calculated, the total is 2.24 ° C./W, as shown in Table 2, and a good value is obtained.

Table 3 shows a case where aluminum nitride (AlN) was used as the heat diffusion plate 2, and the silicon chip and A
The displacement of 1N is small, 2 μm, and a 25 μm gold-silicon alloy (8% by weight) can be used. Thereby, the first
Although the value can be set to 1/1000 or less of the gel part thermal resistance in the table, 250N
It requires the insertion of a thick rubber material having a thickness of μm, resulting in a heat resistance of 20 times. However, overall, it was 1.98 ° C / W, the first
The semiconductor chip of about 30 W which is smaller than the example shown in the table can be sufficiently cooled. In addition, Cu / Mo / Cu clad plate (for example, CLYMAX: manufactured by Climax),
Cu-impregnated sintered tungsten, Fe-Ni mesh-containing copper plate (for example, manufactured by Sumitomo Special Metals Co., Ltd.) aluminum and the like can be similarly treated as the heat diffusion plate.

FIGS. 2A and 3 are enlarged sectional views showing details of the wiring board 4 and the pins 6. FIG. 2 corresponds to a TTL (transistor-transistor-logic) interface. 2B is a perspective view showing the pin arrangement of FIG. 2A, and FIGS. 2C and 2D are partially enlarged perspective views of FIG. 2A. FIG. 3 corresponds to an ECL (emitter coupled logic) interface. FIG. 3 is characterized in that a ground layer 4a is provided between a power supply layer 4b and a signal layer 4c in order to perform impedance matching. In the first embodiment, for example, a layer interval of 10
50 Ω was obtained at 0 μm.

In the wiring board 4, a plurality of wiring layers (ground layer 4a, power supply layer 4b, signal layer 4c) are laminated at regular intervals in a plastic material. FIGS. 2A and 3 show an example in which the ground layer 4 a is connected to the pin 6.
Are fitted in through holes 4d formed in the wiring board 4 and are fixed by solders 4e. In this case, the wiring layer not connected to the pin 6 is insulated so as not to contact the through hole 4d. The pin 6 is made of a material having rigidity against bending. Further, as shown in FIG. 2B, a large number of pins 6 are formed on almost the entire surface of the wiring board 4.

The connection portion between the wiring substrate 4 and the chip 1 is formed in a stepped shape, and the wiring layer is exposed at each step. Ground layer 4a
2C, as shown in FIG. 2C, the side surface conductive portion 4f is extended to the substrate side end and the surface on which the power supply layer 4b is formed, and is connected to the chip by bonding wires on the surface of the power supply layer 4b. I have. Further, the side conductive portion 4f is formed as shown in FIG.
As shown in FIG. 8, the wiring board 4 may be formed on the entire side edge, and a part thereof may be extended to the surface on which the power supply layer 4b is formed. That is, the ground layer 4a may be formed such that the wiring width of the side surface conduction portion 4f formed on the side end surface of the wiring board 4 is larger than the wiring width of the portion formed on the same surface as the power supply layer 4b. Good. The connection between the chip 1 and the wiring layer is made by using a bonding wire 7 having a loop shape so as to be able to absorb the displacement of each rigid body because a soft material, for example, an elastomer is used for interconnecting the members. .

In addition, since a rigid epoxy potting cannot be used for sealing for the same reason, a silicone gel (for example,
Potting is performed using KJR9010 manufactured by Shin-Etsu Silicon Co., Ltd. or JCR6110 manufactured by Dow Corning Toray Silicone Co., Ltd.) as the coating gel 11.

Further, the cap 10 is sealed with an elastomer 12 for mechanical protection. However, the internal pressure rises due to heating during curing, and blowholes are generated, and the internal and external pressures become the same. High reliability can be obtained by using an elastomer capable of controlling the temperature and time of curing such that the elastomer 12 cures after the blowhole is closed again.

FIGS. 4A, 4B, and 4C show details of the signal layer 4c, the power supply layer 4b, and the ground layer 4a shown in FIG. 2, and show about 1/4 of the entire device. I have. here,
Conventionally, a plating conductive line used in a PGA package is eliminated, and the structure has a structure in which the parasitic capacitance of the wiring is reduced by 30 to 40%. This is facilitated by the fact that the mounting portion of the chip 1 is formed as a through hole. In addition, since all of the wiring layers use copper wiring, the electric resistance can be reduced. Therefore, when the resistance level is the same as that of the related art, it is possible to design a fine width of the wiring, particularly the signal wiring.

FIG. 4B shows a ground (Gnd) wiring 4 b ′ whose end extends to the inner end of the wiring board 4.
And the other power supply voltage wiring 4b ″. The grounding wiring 4b ′ is connected via the side conductive portion 4f at the inner end of the wiring board 4 as shown in FIG. 2 (c) or (d). Formation 4a
It is connected to the. With such a structure,
Since the power supply and ground wiring layers can be formed on the same plane, bonding is simplified and the ground potential can be stabilized.

Further, as shown in FIG. 4B, a large number of power supply layers 4b are provided in parallel, but these may be combined to form a wide wiring. Recent LSIs tend to require a large number of stable power lines of different voltages. Therefore, a structure in which the power supply layer 4b is disposed in the middle to meet the demand is adopted. Then, a counter electrode is provided so as to be the shortest distance to the mounting portion 13 of the chip 1, and connection points are connected by bonding wires. By providing a plurality of lines for one power supply, the inductance can be minimized.
The conduction from the chip 1 is connected to the power supply layer 4b by the bonding wire 7 via the side surface conduction portion 4f shown in FIGS.

QF with leads protruding radially around
In the case of the P (quad flat package) type, all wiring must be led to the outermost periphery of the package. However, the pin grid array package has a structure that eliminates the plating wires extending from the internal wiring. Because
The wiring at the pin installation part is only the termination, and it is possible to connect to an external circuit board via the pin 6 with a relatively short wiring, so that the average parasitic capacitance, inductance, and resistance can be reduced.

In some cases, a bypass capacitor connected between the power supply layer 4b and the ground layer 4a is required to be built in the package. For this purpose, as shown in FIG. 5, a mounting space 19 for the chip-type bypass capacitor 14 is secured on the power supply layer 4b or the signal layer 4c. The power supply layer 4b or the signal layer 4c facing the corner of the chip 1
Is a non-wiring area, a bypass capacitor 14 is provided,
Wiring layers for connecting the bonding wires 7 are concentrated on both sides in parallel. The tip of each wiring is opposed to the pad 1a of the chip 1 so that the bypass capacitor 14 does not hinder the bonding process. Both terminals of the bypass capacitor 14 installed in the non-wiring region are connected between the power supply layer 4b and the ground layer 4a. The bonding wire 7 is connected between the end of the wiring layer and the pad 1a of the chip 1.

Table 3 shows a comparison between the TTL interface structure shown in FIG. 2 and the conventional package structure.

[0048]

[Table 4]

As is apparent from Table 4, the capacitance has been improved to about 1/2 and the resistance has been improved to about 1/10. This improvement enables high-speed transmission of signals. Specifically, the present invention can be applied to an LSI having a clock frequency of about 150 MHz. In this method, a chip mounting portion has a through-hole structure, a copper wiring and a wiring substrate made of a low dielectric constant organic material are arranged in a multilayer structure around the chip mounting portion, and the layer structure is an LSI
Signal / power / ground, signal / ground / power,
The combination of grounding / signal / grounding / signal / grounding / power supply / power supply / grounding and the like enables high-speed pulse propagation.

The soft materials used in the present invention, that is, the elastomer and the coating gel, each have an elastic modulus in the range of 0.001 to 100 kg / mm ² , preferably 0.01.
Use a material at 10 kg / mm ² . Furthermore, a thickness capable of absorbing a thermal expansion mismatch between materials constituting the package,
That is, the strain amount is 5 to 1000%, preferably 50 to 1000%.
Preferably, the thickness is controlled to 200%. Here, a soft material having a modulus of elasticity of 0.001 to 100 kg / mm ² refers to a material having a modulus of 0.0
A silicone rubber having an elastic coefficient of from 0.5 to 0.5 kgf / mm ² , for example, a material obtained by adding a filler such as Al ₂ O ₃ to a methyl phenyl siloxane (reaction type with a platinum catalyst) or the like; For example, there are TSE322RTV (Toshiba Silicone Co., Ltd.), KJR9022 from Shin-Etsu Chemical Co., Ltd., CY52-223 from Dow Toray Silicone Co., Ltd., and the like. Further, silicone rubber is also made of KE110 (Shin-Etsu Chemical Co., Ltd.) or KJR901 using the same base material (eg, methyl phenyl siloxane).
0, Dow Toray Silicone JCR6110 and the like.

Rubber-modified epoxy XNR3508 (cured dicyandiamide containing carbon filler) having an elastic coefficient of 50 to 100 kgf / mm ² (manufactured by Ciba-Geigy), etc. Further, there are polyurethane rubber having a modulus of elasticity of 0.1 to 50 kgf / mm ² , UE539 and polyurethane gel. In short, any rubber-based or gel-based material can be used, and a filler can be added if necessary.

FIG. 7 shows the relationship between the size of the package for realizing the strain of 5 to 1000% and the rubber thickness of the joint.

The package size in FIG. 7 is the size of a heat diffusion plate (Cu) or a glass fiber-containing epoxy resin substrate. The rubber thickness indicates a case where silicone rubber (trade name “Toray SE4400”) is used as a bonding agent.

(Embodiment 2) FIG. 6 is a partially enlarged sectional view showing Embodiment 2 of the present invention.

The second embodiment is characterized in that a flexible multilayer board 15 is used for the wiring board 4. The flexible multilayer board 15 can be obtained by forming a thin film wiring layer on a film of polyimide, maleimide or the like. In the second embodiment, the ground layer 4
a, and the ground layer 4 a is soldered to the pin 16.

Further, in the second embodiment, the wiring board 4
Is flexible, so that the pins cannot be held by the wiring board 4 as in the first embodiment of FIG. Therefore, a flange is provided at the base of the pin 16, the flange is embedded in the heat diffusion plate 2, and is fixed by the solder 17 to secure the mounting strength. Here, the pin is provided with a flange, but the pin 6 shown in FIG. 1 having no flange may be embedded in the heat diffusion plate 2.

Since the wiring board 4 is thinner than the chip 1, a gap is formed on the wiring board 4 in the flat cap 10. Therefore, a dish-shaped cap 18 having a bulging portion provided in the periphery is used, and the peripheral surface thereof is made of an elastomer 12.
To join to the flexible multilayer board 15.

Further, in the second embodiment, similarly to the side surface conductive portion 4f of the first embodiment, an interlayer conductive portion 4g is provided at a necessary portion of the flexible multilayer board 15.

Although the invention made by the present invention has been specifically described based on the first and second embodiments, the present invention is not limited to the first and second embodiments, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

For example, in the structures of the first and second embodiments, the combination of each member can be as shown in Table 5.

[0061]

[Table 5]

In Table 5, the type 3-1 water pillow is a liquid heat sink using the trade name “Florinert” as a cooling medium, and encloses the cooling medium in a bag-like member.
This is used in place of the fin 9 shown in FIG.

[0063]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

That is, a semiconductor chip, a heat diffusion plate to which the semiconductor chip is bonded on one side, and at least one semiconductor chip which is bonded to the same surface of the heat diffusion plate so as to expose the semiconductor chip. Since there are provided a plurality of wiring layers, a plastic wiring board whose ends are exposed near the semiconductor chip, and bonding means for connecting pads of the semiconductor chip and ends of the wiring board are provided. Sufficient diffusion can be performed without impairing the signal propagation characteristics.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of a semiconductor device according to the present invention.

FIG. 2A is an enlarged sectional view showing details of a wiring board and pins corresponding to a TTL interface.

FIG. 2 (b) is a perspective view showing a pin arrangement of FIG. 2 (a).

FIG. 2 (c) is a partially enlarged perspective view of FIG. 2 (a).

FIG. 2 (d) is a partially enlarged perspective view of FIG. 2 (a).

FIG. 3 is an enlarged sectional view showing details of a wiring board and pins corresponding to an ECL interface.

FIG. 4 (a) is a plan view showing details of a signal layer in FIG. 2 (a).

FIG. 4 (b) is a plan view showing details of a power supply layer of FIG. 2 (a).

FIG. 4 (c) is a plan view showing details of a ground layer in FIG. 2 (a).

FIG. 5 is a plan view showing details of an installation portion of a bypass capacitor.

FIG. 6 is a partially enlarged sectional view showing Embodiment 2 of the present invention.

FIG. 7 shows a relationship between a package size and a thickness for realizing a strain amount of 5 to 1000%.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Chip, 1a ... Pad, 2 ... Thermal diffusion plate, 3, 5, 8, 12 ... Elastomer, 4 ... Wiring board, 4a ... Ground layer, 4b ... Power supply layer, 4c
.Signal layer, 4d ... through hole, 4e, 17 ...
Solder, 4f side conductive part, 4g interlayer conductive part, 6, 16 pin, 7 bonding wire, 9 fin, 10, 18 cap, 11
... Coating gel, 13 ... Mounting part, 14 ...
-Bypass capacitor, 15 ... Flexible multilayer board.

 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Tetsuo Nakano 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Kazuo Koide 2326, Imai, Ome-shi, Tokyo Device Development, Hitachi, Ltd. Inside the center (72) Inventor Akira Yamagiwa 1 Horiyamashita, Hadano-shi, Kanagawa Prefecture Inside the Kanagawa Plant, Hitachi, Ltd. ) Inventor Toshio Hatada 502, Kandate-cho, Tsuchiura-shi, Ibaraki Pref. Machinery Research Laboratory, Hitachi, Ltd. (72) Inventor Hitoshi Matsushima 502-Kartate-cho, Tsuchiura-city, Ibaraki Pref. Kunio 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Hitachi Research Laboratory, Hitachi, Ltd.

Claims (8)

[Claims] 1. A semiconductor device comprising: a semiconductor chip; a wiring board having side surfaces and a plane surrounding the semiconductor chip; and a plurality of wiring layers having a ground layer and a power supply layer formed on the plane of the wiring board. The ground layer or the power supply layer formed on the plane is formed continuously to the side surface, and the wiring width of the ground layer or the power supply layer formed on the side surface is the same as that of the wiring formed on the plane. A semiconductor device formed wider than a width. 2. The semiconductor device according to claim 1, wherein said plurality of wiring layers include a plurality of signal layers. 3. The semiconductor device according to claim 2, wherein the wiring substrate has a plurality of planes and side surfaces, and the plurality of signal layers are formed on the plurality of planes. 4. The plurality of signal layers are connected to the semiconductor chip by a plurality of connection means, and the plurality of connection means are formed so as to cross a part of a ground layer or a power supply layer formed on the side surface. 3. The semiconductor device according to claim 2, wherein: 5. A semiconductor chip, a wiring substrate having a side surface and a plane surrounding the semiconductor chip, and a wiring width selectively positioned on the plane of the wiring substrate, extending from the plane to the side surface, and further having a wiring width of the plane. A ground layer or a power supply layer having a wider wiring width on the side surface, a plurality of signal layers selectively located on a plane of the wiring board, and connecting the plurality of signal layers to the plurality of pads of the semiconductor chip; A semiconductor device having a plurality of connection means. 6. The semiconductor device according to claim 5, wherein the wiring board has a plurality of planes and side surfaces, and the plurality of signal layers are located on the plurality of planes. 7. The semiconductor device according to claim 5, wherein said plurality of connection means are configured to cross a ground layer or a power supply layer on said side surface. 8. The semiconductor device according to claim 1, wherein said wiring substrate is made of a plastic substrate.