JPH11317019A - Gain adjusting circuit for rf signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the area of a chip by incorporating a polarity switching function in RF signals different in polarity, enabling reduction of conventionally necessary polarity switching circuits thereby eliminating an operational amplifier. SOLUTION: This gain adjusting circuit is provided with first to fourth gain adjusting resistors R1 to R4, an operational amplifier 7 and a differential operational amplifier, and a linked changeover switch 8 is provided in a pre-stage. Thus, gain adjustment is performed by changing the resistance values of the respective resistors R1 to R4 while changing the differential operational amplifier to an inverting or non-inverting amplifier, and a gain adjusting circuit and a polarity switching circuit which are conventionally constituted of two operational amplifiers are composed of one operational amplifier. Thus, the area thereof is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an RF signal gain adjustment circuit for adjusting the gain of an RF signal generated by an optical pickup in an optical disk drive.

[0002]

2. Description of the Related Art An optical pickup and a head amplifier for an RF signal generated thereby will be described with reference to FIG. Generally, the RF signal output from the CD-type optical pickup 20 has a signal length of 3T to 11T.
(T = 1 / f, f = 4.3218 MHz at normal speed). Of the components, the signal length is 3
Signals of components from T to 5T have smaller amplitudes than other signal components due to intersymbol interference.

[0003] Such an RF signal is supplied to an adder circuit 21, R
The signal is amplified by a head amplifier including an F equalizer circuit 22, an AGC circuit 23, a polarity switching circuit 25, and an RF detection circuit 26. That is, after the RF signal of the optical pickup 20 is added by the adding circuit 21, the RF equalizer circuit 22
Are amplified so that the amplitude of each signal component becomes substantially equal. Then, through the AGC circuit 23, the LSI for CD servo
The data is sent to a reference signal 24, which is sliced by comparison with a reference signal to be subjected to digital signal processing. Further, the RF signal is sent to an RF detection circuit 26 via a polarity switching circuit 25, and a predetermined signal such as a BDO (black dropout) signal or O
FTR (off-track) signal, RFDET (RF detection)
A 3TENV (3T envelope) signal is generated and sent to the CD servo LSI 24.

Incidentally, various types of optical pickups 20 have been developed by various companies, and the amplitude of the RF signal of the optical pickup 20 varies. Further, the optical pickup 20 itself also has variations,
The amplitude of the signal is not constant. If the amplitude of the RF signal amplified by the RF equalizer circuit 22 is not constant, a problem may occur when data is sliced by the CD servo LSI 24. Therefore, in order to cope with the optical pickups of various companies, the head amplifier is provided with the AGC circuit 23 as a gain adjustment circuit for amplifying the RF signal so that the amplitude of the RF signal is always constant.

As a configuration of the AGC circuit 23, as shown in FIG. 9, a method is used in which a peak and a bottom of a gain of an RF signal amplified by the RF equalizer circuit 22 are obtained by an RF detection circuit 26 and fed back to the AGC circuit 23. General.

FIGS. 10A and 10B show an example of an AGC circuit for adjusting the gain of an RF signal of a conventionally used optical pickup. FIG. 10A shows the case where the gain adjustment of the RF signal of the optical pickup is performed by the input side resistor, and FIG. 10B shows the case where the negative feedback side resistor is used.

In the case of gain adjustment by the input side resistance, FIG.
As shown in FIG. 0 (a), N resistance values R /
2 ⁰ , R / 2 ¹ , R / 2 ² ,. . . , R / 2 ^N-1 are connected in parallel, and a resistor having a resistance value R / M is connected to the feedback side. ON this time the analog switch A ₁ to A _N as shown in Table 1, OF
When F is applied, the gain of the operational amplifier 27 changes in 2 ^N ways at gain steps of 1 / M. When the gain is adjusted by the negative feedback resistor, as shown in FIG.
A resistor having a resistance value R is connected to the input side, and N-1 resistors r are connected in series to the feedback side. At this time, the analog switches A ₁ to
When A _N is turned on and off as shown in Table 2, the gain of the operational amplifier 28 changes in N ways at gain steps of 1 / M.

[0008]

[Table 1]

[0009]

[Table 2]

As described above, the specifications of the optical pickup vary from company to company. Regarding the polarity of the RF signal, there are a type in which the bright side is output as a HIGH signal and a type in which the bright side is output as a LOW signal. Since the polarity of the RF signal is inverted by the adder circuit 21, the RF equalizer circuit 22, and the AGC circuit 23 as shown in FIG.
The polarity of the RF signal output from the GC circuit 23 is such that in the case of an optical pickup in which the light side is output as a HIGH signal, the light side is a LOW signal, and in the case of an optical pickup in which the light side is output as a LOW signal, the light side is HIGH.
Signal.

RF input to the CD servo LSI 24
There is no problem with the signal since the CD servo LSI 24 has a polarity switching function. However, since the RF detection circuit 26 is usually designed to be fixed to one of the polarities, the RF signal of the opposite polarity is used. If it is entered, it will not work properly and will cause a problem. Therefore, a polarity switching circuit 25 is built in between the AGC circuit 23 and the RF detection circuit 26 as shown in FIG.

[0012]

However, the RF signal is a high-frequency signal (for example, a 6T speed 3T component is 4.321.
8 MHz), and a high-speed and wide-band operational amplifier is required, and there is a problem in terms of chip area and cost to be used for polarity switching. Also, the RF signal of the optical pickup must pass through the operational amplifier in the adder circuit 21, the operational amplifier in the RF equalizer circuit 22, the operational amplifier in the AGC circuit 23, and the operational amplifier in the polarity switching circuit 25 four times. However, there is a concern that the S / N ratio deteriorates.

Further, in the conventional method, FIG.
(B), a, ON of the analog switch A ₁ to A _N
It can be seen that the circuit configuration is such that the resistor is connected in series to the input side resistor or the negative feedback side resistor and affects the gain of the operational amplifier. O of analog switches A _{1 to} A _N
Since the N resistance considerably depends on the temperature, the process, the power supply voltage, and the magnitude of the input signal, the analog switch A ₁ is used to prevent the gain of the operational amplifier from being affected by the ON resistance of the analog switches A _{1 to} A _N. to a _N constituting the transistor size of the (channel width W) was considerably large, there is a need to significantly reduce the ON resistance.

FIG. 11 shows an example of the result of examining the transistor size dependence of the ON resistance of the analog switches A _{1 to} A _N by simulation. When a current of 10 μA flows through the analog switch as shown in the simulation circuit (a), the ON resistance is almost inversely proportional to the transistor size as shown in (b). Generally, operational amplifier 2
Since the outer pickled resistance of 7,28 is several K~ number 10K [Omega], in order to eliminate the influence of the ON resistance of the analog switch A ₁ to A _N are to be below the ON resistance of at least 100 [Omega] No.

[0015] For this purpose, the transistor size of the analog switch A ₁ to A _N from FIG. 11 (b), it can be seen that in this example be at least 1500 [[mu] m] or more. The number of such large analog switches A _{1 to} A _N is one and the area of each of the operational amplifiers 27 and 28 is a problem. For example, if the number of gain switching is 3
Assuming that there are two stages, five (2 ⁵ = 32) analog switches A _{1 to} A ₅ are required in the case where the gain is adjusted by the input side resistance as shown in FIG. Further, when the gain is adjusted by the negative feedback side resistor as shown in FIG. 10B, 32 analog switches A _{1 to} A ₃₂ are required, and the analog switches alone take up a considerably large area.

In view of the above problems, the present invention reduces the number of operational amplifiers by constructing a gain adjusting circuit with a differential operational amplifier and incorporating a polarity switching function, and specifically reduces the number of operational amplifiers from two to one, and furthermore, It is an object of the present invention to provide an RF signal gain adjustment circuit that adjusts the amplitude of an RF signal of an optical pickup with a smaller chip area by changing the configuration of the adjustment resistor and with a smaller chip area than before.

[0017]

The present invention comprises a differential operational amplifier and switching means, wherein the differential operational amplifier comprises:
A first gain adjustment resistor between the first input terminal and the inverting input terminal of the operational amplifier; a second gain adjustment resistor between the inverting input terminal and the output terminal of the operational amplifier; A third terminal connected to the non-inverting input terminal of the operational amplifier;
A fourth gain adjusting resistor is connected between a non-inverting input terminal of the operational amplifier and a reference power supply, and the switching means generates an optical pickup at the first input terminal. Inputting an RF signal to be input and inputting a reference power supply to the second input terminal, inputting a reference power supply to the first input terminal, and inputting the RF power to the second input terminal. The differential operational amplifier is switched to an inverting amplifier or a non-inverting amplifier by switching the mode, and the change in the resistance value of each of the gain adjustment resistors is performed. The above-described problem is solved by an RF signal gain adjustment circuit characterized in that the RF signal gain can be adjusted.

[0018]

1 is a block diagram showing a configuration of a differential operational amplifier according to a first embodiment of the present invention;
A first gain adjustment resistor between the first input terminal and the inverting input terminal of the operational amplifier; a second gain adjustment resistor between the inverting input terminal and the output terminal of the operational amplifier; A third terminal connected to the non-inverting input terminal of the operational amplifier;
A fourth gain adjusting resistor is connected between a non-inverting input terminal of the operational amplifier and a reference power supply, and the switching means generates an optical pickup at the first input terminal. Inputting an RF signal to be input and inputting a reference power supply to the second input terminal, inputting a reference power supply to the first input terminal, and inputting the RF power to the second input terminal. The differential operational amplifier is switched to an inverting amplifier or a non-inverting amplifier by switching the mode, and the change in the resistance value of each of the gain adjustment resistors is performed. A gain adjustment circuit for an RF signal, wherein the gain of the RF signal is adjustable.

According to a second aspect of the present invention, the first and second gain adjusting resistors include a first fixed resistor, a first variable resistor, and a second fixed resistor connected in series,
The first fixed resistor is connected to the first input terminal, the variable contact of the first variable resistor is connected to the inverting input terminal of the operational amplifier, and the second fixed resistor is connected to the output terminal of the operational amplifier. A third fixed resistor, a second variable resistor, and a fourth fixed resistor connected in series as the third and fourth gain adjustment resistors, and the third fixed resistor is connected to the third fixed resistor. 2. The input terminal of claim 2, wherein a variable contact of the second variable resistor is connected to a non-inverting input terminal of the operational amplifier, and the fourth fixed resistor is connected to a reference power supply. It is a gain adjustment circuit for RF signal described.

According to a third aspect of the present invention, the first fixed resistor (resistance value R10) and the second fixed resistor (resistance value R2
0N) connected in series as a first variable resistor between
And a unitary resistor (resistance value r), and as a variable contact of the first variable resistor, 2N at both ends of the unit resistor.
+1 switch means (the switch number n is -N, -N + 1, -N + 1, -N + 1) from the first fixed resistor to the second fixed resistor.
.., 0,..., N−1, N) are connected individually, and all the output terminals of each of the switch means are connected to the inverting input terminal of the operational amplifier. A second variable resistor between the third fixed resistor (resistance R30) and the fourth fixed resistor (resistance R40) is composed of 2N unit resistors (resistance r) connected in series. In addition, 2N + 1 switch means (switch number n is -N, -N + 1 from the third fixed resistor toward the fourth fixed resistor) are provided at both ends of all of the unit resistors as variable contacts of the second variable resistor. , ..., 0, ..., N
-1, N), and each output terminal of each of the switch means is connected to a non-inverting input terminal of the operational amplifier, thereby inverting the operational amplifier. By turning on only one of the switch numbers n in each of the switch means on the input terminal side and each of the switch means on the non-inverting input terminal side, the resistance value of each of the gain adjustment resistors becomes
R1 is the resistance of the first gain adjustment resistor, R2 is the resistance of the second gain adjustment resistor, R3 is the resistance of the third gain adjustment resistor, and R4 is the resistance of the fourth gain adjustment resistor. 3. The RF signal gain adjustment circuit according to claim 2, wherein the value changes in parallel so as to satisfy the following relational expression.

R1 = R10 + (N + n) * r R2 = R20 + (N−n) * r R3 = R30 + (N + n) * r R4 = R40 + (N−n) * r The invention according to claim 4, wherein 4. The RF signal gain adjustment circuit according to claim 3, wherein each of the switch means is constituted by an analog switch, and a transistor constituting the analog switch has a channel width of 10 μm or less.

According to a fifth aspect of the present invention, the first and third fixed resistors have the same resistance value (R10
= R30) and the resistance values of the second and fourth fixed resistors are the same (R20 = R40), so that the gain adjustment when the switch number n of the switch means to be turned on changes. 4. The RF signal gain adjustment circuit according to claim 3, wherein the characteristics have the same characteristics in any of the modes.

According to a sixth aspect of the present invention, when the center gain of the differential operational amplifier when the variable contact points of the first and second variable resistors are at the middle point (n = 0) is A [dB], 6. The RF signal gain adjustment according to claim 5, wherein ± α [dB] is realized as a gain adjustment range by each of the resistance values of the first and second fixed resistors satisfying the following relational expression. Circuit.

[0024] ^{R10 = [2 * 10 (A} - α) / 2 0 -
^{10 A / 2 0 +1] /} [10 A / 2 0 -10 (A - α)
^{/ 2 0] * N * r} R20 = [10 (A - α) / 2 0 +10 - α / 2 0]
^{/ [1-10 - α / 2 0} ] * N * r The invention of claim 7, designated gain adjustment range ±
7. The RF signal gain adjustment according to claim 6, wherein a set value of a center gain A [dB] of the differential operational amplifier is limited to a range represented by the following relational expression in order to realize α [dB]. Circuit.

A <20 * log ₁₀ [1 / (1-2 * 10 ^{− α / 20} )] (where α> 20 * log ₁₀ 2 ≒ 6.02) Next, an embodiment of the present invention will be described in detail. I do.

(Embodiment 1) Referring to FIG. 1, an RF signal gain adjustment circuit according to Embodiment 1 of the present invention will be described. The first input terminal 1 and the inverting input terminal 5 of the operational amplifier 7 are connected to each other. Between the inverting input terminal 5 of the operational amplifier 7 and the output terminal 3 of the operational amplifier 7, between the second input terminal 2 and the non-inverting input terminal 6 of the operational amplifier 7, and between the non-inverting input terminal 6 of the operational amplifier 7 and the reference power supply. And first to fourth gain adjustment resistors R1 to R4 each having a variable resistance value between the first and fourth gain adjustment resistors R1 to R4.
To form a differential operational amplifier.

An interlocking switch 8 is connected as switching means to each of the first input terminal 1 and the second input terminal 2, and when the interlocking switch 8 is ON, as shown in FIG. 1 is connected to the output of the RF signal 9 and the second input terminal 2 is set to the mode connected to the reference power supply VREF. When the interlocking switch is OFF, FIG.
As shown in FIG. 1, the first input terminal 1 is connected to a reference power supply VREF.
In addition, it is assumed that the second input terminal 2 is in a mode in which it is connected to the output of the RF signal 9.

In the above configuration, the input R
The polarity of the F signal is HIGH on the bright side due to the optical pickup
Signal or a LOW signal.
Switching to the inverting amplifier of (a) or the non-inverting amplifier of FIG. 1B, the gain adjustment resistors R1, R2, R
By changing the resistance value of each of R3 and R4, R
The gain of the F signal can be adjusted, and the polarity of the output RF signal can be unified.

According to the gain adjustment, the number of operational amplifiers for polarity switching which has been conventionally required can be reduced, and the area can be reduced.

(Embodiment 2) In a gain adjustment circuit according to Embodiment 3, a specific configuration of each of the gain adjustment resistors R1, R2, R3, and R4 in Embodiment 1 is shown.

Referring to FIG. 2, as first and second gain adjusting resistors R1 and R2, a first fixed resistor R10, a first variable resistor VR1, and a second fixed resistor R20 are connected in series. , The first fixed resistor R10 is connected to the first input terminal 1, and the variable contact of the first variable resistor VR1 is connected to the operational amplifier 7
And the second fixed resistor R20 is connected to the output terminal 3 of the operational amplifier 7.

Similarly, as the third and fourth gain adjustment resistors R3 and R4, a third fixed resistor R30, a second variable resistor VR2, and a fourth fixed resistor R40 are connected in series.
The third fixed resistor R30 is connected to the second input terminal 2, the variable contact of the second variable resistor VR2 is connected to the non-inverting input terminal 6 of the operational amplifier 7, and the fourth fixed resistor R40 is connected to the reference power supply 4. Connecting.

In the above configuration, by moving the respective variable contacts of the first and second variable resistors VR1 and VR2, the four gain adjusting resistors R1, R2, R3 and R4 constituting the differential operational amplifier are formed. The resistance value can be changed, and gain adjustment can be realized.

(Embodiment 3) In the gain adjustment circuit of Embodiment 3, a variable resistor VR of a differential operational amplifier is used.
1 and VR2. FIG.
, The first fixed resistor R10 and the second fixed resistor R10
As the first variable resistor VR1 between the first resistor 20 and the second resistor 20, 2N unit resistors r are connected in series, and 2N + 1 analog switches (a switch number n, a first From the fixed resistor R10 to the second fixed resistor R20 in this order, n = −N, −N +
1,. . . , 0,. . . , N-1, N. ), And all the output terminals of the analog switch are connected to the inverting input terminal of the operational amplifier 7. Similarly, the third fixed resistor R30 and the fourth fixed resistor R
As the second variable resistor VR2 between 40 and 40, 2N unit resistors r are connected in series, and as a variable contact, a total of 2N + 1 analog switches are connected to both ends of the unit resistor r. , From the fixed resistor R30 to the fourth fixed resistor R40 in order, n = −N, −N + 1,.
0,. . . , N-1, N. ), And all the output terminals of the analog switch are connected to the non-inverting input terminal of the operational amplifier 7.

In the gain adjustment circuit having the above-described configuration, the resistance can be varied by switching one of the 2N + 1 analog switches on the inverting input terminal side and the non-inverting input terminal side of the operational amplifier 7 with the switch number n. Only ON
When the selector circuit 10 is connected, the four gain adjustment resistors R1, R2, R
3, when the resistance value of R4 changes n, change it in parallel so as to satisfy the following equation (1) (if R1 increases and R2 decreases, R3 increases and R4 decreases) And gain adjustment can be realized.

R1 = R10 + (N + n) * r R2 = R20 + (N−n) * r R3 = R30 + (N + n) * r R4 = R40 + (N−n) * r (1) where R1, R2, R3 and R4 are resistance values of the first to fourth gain adjustment resistors R1 to R4, respectively, and R10, R20, R30 and R40 are respectively the first to fourth fixed resistors R10, R20, R30 and R40. Where r is the unit resistance of the unit resistance r. Also, n is -N, -N + 1,. . . ,
0,. . . , N−1, N.

(Embodiment 4) The gain adjustment circuit of Embodiment 4 relates to the size of a transistor constituting an analog switch. Referring to FIG.
Generally, an analog switch has a configuration in which a p-channel transistor 12 and an n-channel transistor 13 are combined. In this circuit, the power supply voltage V is applied to the gate input terminal E of the n-channel transistor 13.
When DD is applied and the ground voltage VSS is applied to the gate input terminal NE of the p-channel transistor 12, no matter what signal is input to the input terminal IN of the analog switch, one of the transistors is always turned on (input The signal voltage Vin is 0 to about VREF (VDD / 2)
During this time, the n-channel transistor 13 is turned on, the p-channel transistor 12 is turned off, and the input signal V
While in is between VREF and VDD, the p-channel transistor 12 is on and the n-channel transistor 13 is off), and a signal is output to the output terminal OUT of the analog switch. Now, considering the n-channel transistor 13, the threshold voltage Vt is equal to the source (s)-
The following relational expression (2) is obtained in consideration of the back gate bias effect due to the voltage Vsb between the substrates (b).

[0038] Vt = Vt0 + γ * [( 2 * Φ f + Vsb) ** 0.5 - (2 * Φ f) ** 0.5] ...... (2) where Vt0 is no back-gate bias effect (Vsb
= 0), γ is a bulk threshold parameter, and Φ _f is given by the strong inversion surface potential, so that when the input signal Vin is applied to the source of the n-channel transistor 13, (S) and the substrate (b) generate a potential difference Vsb, and the threshold voltage Vt
Rises. Conversely, since the gate voltage Vg is constant (VDD), the voltage Vg between the gate (g) and the source (s)
s becomes smaller. As a result, when the value of the input signal Vin is small, Vgs> Vt, so that the n-channel transistor 13 is turned on. However, when the value of the input signal Vin becomes large, Vgs = Vgs = about a value slightly larger than VREF.
Vt, and the n-channel transistor 13 is turned off
I do.

Therefore, when the input signal Vin is 0 to about VR
Between the EFs, the n-channel transistor 13 is in the ON state, the input signal Vin and the output signal Vout are substantially equal, and the voltage between the drain (d) and the source (s) is Vds = | Vin-Vout | 0, which means that the transistor is in the non-saturation region, and the drain current Ids is given by the following equation (3).

Ids = (K ′ / 2) * (W / L) * [(Vgs−Vt) ** 2− (Vgd−Vt) ** 2] * (1 + λ * Vds) = K ′ * W / L * (Vgs-Vt-Vds / 2) * Vds * (1 + λ * Vds) (3) K ′: Gain factor of MOS transistor (gain factor) λ: Channel length modulation parameter Since Vds is sufficiently small, if the term of the short channel effect λ is ignored, the above equation (3) becomes the following equation (4).

Ids = K ′ * W / L * (Vgs−Vt−Vds / 2) * Vds (4) Thus, the following equation (5) is obtained.

DIds / dVds = K ′ * W / L * (Vgs−Vt−Vds) (5) Here, if Vds is ignored because it is sufficiently small, the ON resistance Ron of the n-channel transistor 13 becomes It is given by relational expression (6).

Ron = dVds / dIds = 1 / (dIds / dVds) = 1 / [K ′ * W / L * (Vgs−Vt)] (6) Therefore, as shown in FIG. With respect to 13, when the input signal Vin increases,
Since Vt increases while Vgs decreases, Vg
s-Vt decreases and the ON resistance increases. Then, when the input signal Vin becomes slightly larger than VREF, Vgs = Vt, so that the ON resistance becomes infinite and N
The channel transistor 13 turns off. However, when the input signal Vin approaches VREF, the P-channel transistor 12 which has been in the OFF state is turned ON, and
As in increases from VREF to VDD, N
Contrary to the case of the channel transistor 13, the ON resistance of the P-channel transistor 12 decreases.

As a result, as shown in FIG. 5, the ON resistance of the entire analog switch has a mountain shape having a peak value when the input signal Vin is at VREF. When the gate length L is fixed and the transistor size (channel width W) is increased to increase the W / L ratio, the analog switch O
The N resistance will decrease overall.

As described with reference to FIG. 10, in the conventional gain adjustment, the ON resistance of the analog switch affects the gain of the AGC circuit. The problem was that the gain of the circuit changed. To prevent this, the transistor size (channel width W) of the analog switch is extremely large, for example, W> 1500 [μm]
It is necessary to make the ON resistance negligible as a degree, and the configuration is inefficient in area.

On the other hand, the fourth embodiment shown in FIG.
In the configuration described above, the ON resistance of the analog switch does not ride on the signal line and is directly connected to the inverting input terminal and the non-inverting input terminal of the differential operational amplifier having high impedance. Therefore, there is no particular limitation on the size of the transistor constituting the analog switch, and the channel width W of 10 [μm] or less is sufficient, and the number of gain switching of the AGC circuit shown in FIG. But this is not a big problem in area.

(Fifth Embodiment) In the gain adjustment circuit of the fifth embodiment, an interlocking switch is turned on and off.
This is a description of conditions for obtaining the same gain switching characteristics even when the differential operational amplifier is switched to an inverting amplifier or a non-inverting amplifier. If the gain switching characteristics of the inverting amplifier and the non-inverting amplifier are different, the software for gain adjustment must be developed separately, and the guaranteed range of the gain adjustment range also changes, which is not preferable. Therefore,
It is necessary to design the gain switching characteristics when the analog switch number n turned on by the selector circuit changes and the values of the variable resistors VR1 and VR2 change, so that the gain switching characteristics are the same for both the inverting amplifier and the non-inverting amplifier. In the gain adjusting circuit of the present invention shown in FIG. 3, the first gain adjusting resistor R1 between the input terminal 1 and the inverting input terminal of the operational amplifier 7, and the first gain adjusting resistor R1 between the inverting input terminal of the operational amplifier 7 and the output terminal of the operational amplifier 7. A second gain adjustment resistor R2, a third gain adjustment resistor R between the input terminal 2 and the non-inverting input terminal of the operational amplifier 7;
3. Non-inverting input terminal of operational amplifier 7 and reference power supply VREF
The fourth gain adjustment resistor R4 is given by the following relational expression (7), where n is a changeover switch between the two variable resistors VR1 and VR2.

[0048] Where n = −N, −N + 1,. . . , 0,. . . , N-
The gain G ₋ on the inverting input side and the gain G ₊ on the non-inverting input side of the 1, N differential operational amplifier are given by the following equation (8).

[0049] _{G - = R2 / R1 G +} = (R1 + R2) / R1 * R4 / (R3 + R4) = (1 + G -) * R4 / (R3 + R4) ...... (8) Gain Switching Characteristics in the inverting amplifier and a non-inverting amplifier for but become identical, G for any n _- = must become G _+. Therefore, the following equation (9) is obtained from the relational equation (8).

[0050] _{G - = (1 + G -} ) * R4 / (R3 + R4) ∴ R4 = R3 * G - ...... (9) the following equation (10) is substituted into the formula (8) in the above equation (9) is obtained .

R40 + (N−n) * r = [R30 + (N + n) * r] * [R20 + (N−n) * r] / [R10 + (N + n) * r] ∴ (R40−R10) * n * r + (R10 + R40) * N * r + R10 * R40 = (R20-R30) * n * r + (R20 + R30) * N * r + R20 * R30 (10) In order for the above equation (10) to be an identity of n, R40 −R10 = R20−R30 (R10 + R40) * N * r + R10 * R40 = (R20 + R30) * N * r + R20 * R30 (11) R40 is erased according to the first and second equations of the above equation (11). Equation (12) below is obtained by simplifying the above.

R30 = R10 R40 = R20 (12) To summarize the above results, the third and fourth fixed resistors R
When the resistance values of R30 and R40 satisfy Expression (12), the inverting gain characteristic and the non-inverting gain characteristic of the differential operational amplifier become the same, and the gain can be adjusted without any problem even if the polarity is switched. In this case, the common gain G
_n is given by: G _n = [R20 + (N−n) * r] / [R10 + (N + n) * r] (13)

(Embodiment 6) In the invention of Embodiment 6, the conditions for realizing the gain adjustment range α of the designated gain adjustment circuit have been described.
When the center gain G ₀ (gain at n = 0) of the gain adjustment circuit is A [dB], G ₀ = (R20 + N * r) / (R1
0 + N * r) = 10 A / 2 0 ∴R20 = 10 A / 2 0 * R10 + (10 A / 2 0 -1) * N
* R (14) Here, when comparing the magnitudes of G _N and G _{- N} , G _N / G _-N = [R20 / (R10 + 2 * N * r)] / [(R20 + 2 * N * r) / R10] = R10 / (R10 + 2 * N * r) * R20 / (R20 + 2 * N * r) <1 ...... (15) Thus, G _N <G _- since the _N, designated gain adjustment range ± alpha In order to satisfy [dB], the smaller G
Designing with _{N, G N = R20 / (} R10 + 2 * N * r) = 10 (A - α) / 2 0 ...... than (16) Formula (14) (16), R10 = [2 * 10 (A ^{-α) / 20} −10 ^{A / 20} +1] / [10 ^{A / 20} −10 ^{(A-α) / 20} ] * N * r R20 = [10 ^{(A-α) / 20} +10 ^{-α / 20} ] / [1-10 ^{-α / 20} ] * N * r (17) From the above results, R10 and R20 are calculated by the above formula (17).
Is satisfied, and R30 and R40 are set so as to satisfy the expression (12), the specified gain adjustment range ± α [dB] can be realized.

(Embodiment 7) The invention of Embodiment 7 relates to a range that can be set as a center gain A of a gain adjustment differential operational amplifier in order to realize a specified gain adjustment range ± α [dB]. It is described.
In order for R10 to be positive from equation (17), the following equation (1)
8) must be satisfied.

[0055] ^{2 * 10 (A - α)} / 2 0 -10 A / 2 0 +1> 0 ∴A <20 * log 10 [1 / (1-2 * 10 - α / 2 0)] ...... (18 That is, in the gain adjustment circuit of the present invention shown in FIG. 3, in order to realize the gain adjustment range ± α [dB], the equation (1) is used as the center gain A of the differential operational amplifier for gain adjustment.
It is possible to set up to the range indicated by 8).

However, since the argument of the logarithmic function must always be positive, the gain adjustment range ± α is given by the following equation (19)
Becomes

Α> 20 * log ₁₀ 2 ≒ 6.02 (Embodiment 8) Next, the gain adjustment circuit of the present invention will be specifically described with reference to FIG. Since the contents of FIG. 3 have already been described, description thereof will be omitted.

Now, as the RF signal of the optical pickup, A
C gain INac is 0.2 [Vp-p], DC component IN
dc is 0.1 [V], and the gain adjustment range α is ± 10
[DB] Assume that it is necessary. Then, the expression (1)
8) From the center gain A [dB] of the differential operational amplifier
Becomes the following equation (20).

[0059] _{A <20 * log 10 [1} / (1-2 * 10 - 1 0/2 0)] = 8.69 ...... (20) and, this time from this relationship is set to A = 0. Since the unit resistance r can be arbitrarily selected, r = 0.2K [Ω],
As the gain adjustment switching step number 2N + 1, N = 31 (6
If the first fixed resistor R10 and the second fixed resistor R20 are determined by the above equation (17) of the first fixed resistor R10 and the second fixed resistor R20, the resistance values of the first fixed resistor R10 and the second fixed resistor R20 are as follows. Become.

[0060] ^{R10 = [2 * 10 -10/20 -10} 1/20 +1] / [10 1/20 -10 -10/20] * 31 * 0.2 = 5.735 [KΩ] R20 = [10 - [ ^10/20 +10 ^-10/20 ] / [1-10 ^-10/20 ] * 31 * 0.2 = 5.735 [KΩ] (21) The third fixed resistor R30 and the fourth fixed resistor R40, respectively. Is obtained from the above equation (12). That is, a gain adjustment circuit as shown in FIG. 6 is configured.

However, a 6-bit decoder was used as the selector circuit. Thereby, n = −31 to n =
Balance can be adjusted in 63 steps up to +31.

Assuming that the frequency of the RF signal output from the optical pickup is 720 [KHz], (VDD = 5
V, VREF = 2.5V) 7 and 8 show the results when "."

FIG. 7 shows the result of turning on the interlocking switch and operating as an inverting amplifier. FIG. 8 shows the result of turning off the interlocking switch and operating as a non-inverting amplifier. (A) is the waveform of the input signal, (b),
(C) shows switch numbers n = -31 and n = + 3, respectively.
6 is an output waveform of a gain adjustment circuit when one analog switch is turned on. When n = −31 is ON, the peak-to-peak gain of the AC component of the output signal is OUTac = 0.63 [Vp-p] in both the inverting amplifier and the non-inverting amplifier. 24).

[0064] _{α - 3 1 = 20 * log} 10 (OUTac / INac) = 10 [dB] ...... (24) when n = + 31 is ON, in a non-inverting amplifier in the inverting amplifier, OUTac = 0.063 [Vp −p], the gain adjustment range is obtained by the following equation (25).

[0065] _{α + 3 1 = 20 * log} 10 (OUTac / INac) = - 10 [dB] ...... (25) next, even in the non-inverting amplifier is also in the inverting amplifier, which satisfies the necessary specifications ± 10 [dB] .

[0066]

As described above, the use of the gain adjustment circuit of the present invention can reduce the number of operational amplifiers for switching the polarity, which has been conventionally required. Therefore, the gain adjustment circuit can be realized with a smaller area than the conventional one, and its practicality can be reduced. The effect is great. Also,
In the gain adjustment circuit of the present invention, the size of the analog switch can be made sufficiently small. Therefore, even when the number of gain switches is large and a large number of analog switches are required, there is no large area problem, and the practical effect is large.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a gain adjustment circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a gain adjustment circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram of a gain adjustment circuit according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of an analog switch according to a third embodiment of the present invention.

FIG. 5 is a diagram showing an input signal voltage dependence characteristic of an ON resistance of an analog switch.

FIG. 6 is a circuit diagram of a gain adjustment circuit according to an eighth embodiment of the present invention.

FIGS. 7A and 7B show HSPICE simulation results of gain adjustment in the case of the inverting amplifier according to the eighth embodiment of the present invention, wherein FIG. 7A shows a waveform of an input signal, FIG. 7B shows a waveform diagram of an output signal, and FIG. Is the output signal waveform

8A and 8B show HSPICE simulation results of gain adjustment in the case of a non-inverting amplifier according to the eighth embodiment of the present invention, wherein FIG. 8A shows a waveform of an input signal, FIG. 8B shows a waveform diagram of an output signal, and FIG. ) Indicates the waveform of the output signal

FIG. 9 is a configuration diagram of a head amplifier for an optical disk.

10A and 10B are circuit diagrams of a conventional gain adjustment circuit, wherein FIG. 10A is a circuit for performing gain adjustment using an input-side resistor, and FIG. 10B is a circuit diagram for performing gain adjustment using a negative feedback-side resistor.

11A and 11B are diagrams showing a transistor size dependence characteristic of an ON resistance of an analog switch, wherein FIG. 11A is a simulation circuit, and FIG. 11B is a diagram showing a simulation result;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 input terminal 2 input terminal 3 output terminal 4 reference power supply terminal 5 inverting input terminal 6 non-inverting input terminal 7 differential operational amplifier 8 interlocking changeover switch 9 RF signal 10 selector circuit 12 p-channel transistor for analog switch 13 n- for analog switch Channel transistor

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Maki Satate 1006 Kazuma Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (7)

[Claims] 1. A differential operational amplifier comprising: a differential operational amplifier; and a switching unit, wherein the differential operational amplifier includes a first gain adjustment resistor between a first input terminal and an inverting input terminal of the operational amplifier, and an inverting input of the operational amplifier. A second gain adjustment resistor between the second input terminal and the non-inverting input terminal of the operational amplifier; a third gain adjusting resistor between the second input terminal and the non-inverting input terminal of the operational amplifier; A switching means for connecting an RF signal generated by an optical pickup to the first input terminal; and a second input terminal. Switchable between a first mode for inputting a reference power supply to the first input terminal and a second mode for inputting the reference power supply to the first input terminal and inputting the RF signal to the second input terminal. In Wherein the switching of the mode switches the differential operational amplifier to an inverting amplifier or a non-inverting amplifier, and the gain of the RF signal can be adjusted by changing the resistance value of each of the gain adjustment resistors. Gain adjustment circuit. A first fixed resistor, a first variable resistor, and a second fixed resistor connected in series as the first and second gain adjustment resistors; Connecting the variable contact of the first variable resistor to the inverting input terminal of the operational amplifier, connecting the second fixed resistor to the output terminal of the operational amplifier, As a fourth gain adjustment resistor, a third fixed resistor, a second variable resistor, and a fourth fixed resistor are connected in series, and the third fixed resistor is connected to the second input terminal. 2. The RF signal gain according to claim 1, wherein a variable contact of the second variable resistor is connected to a non-inverting input terminal of the operational amplifier, and the fourth fixed resistor is connected to the reference power supply. Adjustment circuit. 3. A 2N unit resistor (resistance value) connected in series as the first variable resistor between the first fixed resistor (resistance value R10) and a second fixed resistor (resistance value R20). r), as variable contacts of the first variable resistor, 2N + 1 switch means (switch number n is from the first fixed resistor to the second fixed resistor) at both ends of the unit resistor.
N, -N + 1, ..., 0, ..., N-1, N)
Each of the input terminals is individually connected, and all of the output terminals of each of the switch means are connected to an inverting input terminal of the operational amplifier. And 2N unit resistors (resistance value r) connected in series as the second variable resistor between the fixed resistor (resistance value R40) and the unit resistor as a variable contact of the second variable resistor. 2N + 1 switch means (switch number n is from the third fixed resistor to the fourth fixed resistor-
N, -N + 1, ..., 0, ..., N-1, N)
Each input terminal is individually connected, and all of the output terminals of each of the switch means are connected to the non-inverting input terminal of the operational amplifier, and the switch means on the inverting input terminal side of the operational amplifier, With each of the switch means on the non-inverting input terminal side,
By turning on only one of the switch numbers n, the resistance value of each of the gain adjustment resistors changes R1 to the first value.
Where R2 is the resistance value of the second gain adjustment resistor, R3 is the resistance value of the third gain adjustment resistor, and R4 is the resistance value of the fourth gain adjustment resistor. 3. The RF signal gain adjustment circuit according to claim 2, wherein the gain changes in parallel so as to satisfy a relational expression. R1 = R10 + (N + n) * r R2 = R20 + (N-n) * r R3 = R30 + (N + n) * r R4 = R40 + (N-n) * r 4. The RF signal according to claim 3, wherein each of said switch means is constituted by an analog switch, and a transistor constituting said analog switch has a channel width of 10 μm or less. Gain adjustment circuit. 5. The first and third fixed resistors have the same resistance value (R10 = R30), and the second and fourth fixed resistors have the same resistance value (R20 = R40). 4. The RF signal according to claim 3, wherein the gain adjustment characteristic when the switch number n of the switch means to be turned on has the same characteristic in any of the modes. Gain adjustment circuit. 6. When the center gain of the differential operational amplifier when the variable contact point of the first and second variable resistors is at a middle point (n = 0) is A [dB], the first and second variable resistors are equal to each other. 6. The RF signal gain adjustment circuit according to claim 5, wherein the resistance value of each of the fixed resistors satisfies the following relational expression to realize ± α [dB] as a gain adjustment range. R10 = [2 * 10 ^{( A - α ) / 2 0} -10 ^{A / 2 0
+1] / [10 A / 2} 0 -10 (A - α) / 2 0] *
N * r R20 = [10 ^{( A - α ) / 2 0} + 10 ^{- α / 2 0} ]
^{/ [1-10 - α / 2 0} ] * N * r 7. In order to realize a specified gain adjustment range ± α [dB], a set value of a center gain A [dB] of the differential operational amplifier is limited to a range represented by the following relational expression. 7. The RF signal gain adjustment circuit according to claim 6, wherein: A <20 * log ₁₀ [1 / (1-2 * 10 ^{− α / 20} )] (where α> 20 * log ₁₀ 2 ≒ 6.02)