JPH1131678A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce interwiring capacity by embedding conduction materials in the opening pattern of an stack inter layer insulating film formed of the opening pattern of organic system inter layer insulating film containing fluorine and the opening pattern of a silicon oxide system inter layer insulating film. SOLUTION: A silicon oxide system inter layer insulating film 2 is formed on a semiconductor substrate 1 by plasma CVD, and the organic system inter layer insulating film 3 containing fluorine is formed. Then, a resist film containing silicon is applied, and the opening pattern of the resist film containing silicon is formed. The form of the opening pattern is copied on the organic system inter layer insulating film 3 containing fluoride, and the opening pattern 3a of the organic system inter layer insulating film containing fluoride is formed. Then, the silicon oxide inter system layer insulating film 2 is etched, and the opening pattern 2a is formed. Then, the conduction materials 5 are embedded in the respective opening patterns 2a and 3a, and a contact plug is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device, which has a high aspect ratio in a laminated interlayer insulating film of an organic interlayer insulating film containing fluorine and a silicon oxide based interlayer insulating film. The present invention relates to a method for manufacturing a highly integrated semiconductor device having a step of forming connection holes and grooves with a high precision.

[0002]

2. Description of the Related Art As the degree of integration of semiconductor devices such as LSIs increases, the width of an interlayer insulating film between adjacent wirings in the same wiring layer in a multi-layer wiring structure decreases, and the interlayer between different wiring layers decreases. The thickness of the insulating film is also reduced. Due to the reduction of the wiring interval, wiring delay due to an increase in capacitance between wirings is becoming a problem. Therefore, the actual operation speed of the semiconductor device is 1 / K (K is a scaling factor, and K>
This does not meet the scaling rule of 1), and the advantage of high integration cannot be fully enjoyed. Preventing an increase in the capacitance between wirings is one of the elemental technologies that must be solved in order to respond to various demands such as high-speed operation, low power consumption, and low heat generation of a highly integrated semiconductor device. The material conventionally used for an interlayer insulating film of a semiconductor device is S
iO ₂ (relative permittivity of about 4), SiON (relative permittivity of about 4 to
6) and inorganic materials such as Si ₃ N ₄ (relative permittivity of about 6). As a method for reducing the capacitance between wirings of a highly integrated semiconductor device, for example, as disclosed in Japanese Patent Application Laid-Open No. 63-7650, the use of an interlayer insulating film of a low dielectric constant material instead of these inorganic materials is effective. is there.

As a low dielectric constant interlayer insulating film material, a silicon oxide based insulating film containing fluorine (hereinafter referred to as SiOF) is used.
And the like are typical. SiOF is Si-O-
A low dielectric constant is achieved by terminating the Si bond network with F atoms to decrease its density and by reducing the polarizability of the Si—F bond. In addition, since the film forming process and the processing process are compatible with the film forming process and the processing process of a conventional inorganic interlayer insulating film such as SiO _2, it is attracting attention because it can be easily adopted even in a current manufacturing facility. Also, since it is an inorganic material, it naturally has excellent heat resistance. However, since the relative dielectric constant of SiOF is around 3, the effect of achieving a low dielectric constant is limited.

As a method of forming a SiOF film, TEF has been conventionally used.
A method of forming a CVD film by adding, for example, NF ₃ as a fluorine source to the OS (40th Joint Lecture on Applied Physics (19)
1993 Spring Annual Meeting) Lecture abstracts p799, Lecture number 1a-
ZV-9) has been reported. For the purpose of stabilizing the film quality, a method of forming low dielectric constant SiOF by dissociating hardly decomposable SiF ₄ by high-density plasma (No. 40)
Proceedings of the Federation Conference on Applied Physics (Spring Annual Meeting, 1993), p.752, lecture number 31p-ZV-1).

In a high-density plasma CVD method using SiF ₄ as a silicon source, SiOF having a relative dielectric constant of about 3.4 is used.
Is obtained. However, when attempting to introduce a high concentration of fluorine atoms into silicon oxide to achieve a low dielectric constant, free F and HF are incorporated into SiOF. In this case, a connection hole is opened in the interlayer insulating film in a later step, and when a TiN barrier layer or a W plug is buried in the connection hole, S
Free F or HF in iOF reacts with TiN, and TiN
The adhesion of the barrier layer is significantly reduced, and W (tungsten)
A situation that leads to peeling of the plug and the W layer occurs. Such a phenomenon is described in, for example, the 43rd Annual Meeting of the Japan Society of Applied Physics (1996)
Spring Annual Meeting) Lecture proceedings p672, Lecture number 28a-K
-3.

[0006] Even if it does not become free F or HF,
A SiF ₂ bond in which _two F atoms are bonded to one silicon atom is generated. The SiF ₂ bond is unstable and easily hydrolyzes to form a SiOH bond, and further, adsorbs H ₂ O in the atmosphere by a hydrogen bond to increase the water content in the SiOF. In this case, when a connection hole is opened in the interlayer insulating film in a later step and a metal film is buried in the connection hole, inconveniences such as poisoned vias are generated, which leads to deterioration of filling characteristics and an increase in contact resistance. Results. Regarding the SiOF low-dielectric-constant interlayer insulating film, see, for example, Monthly Semiconductor World Magazine (published by Press Journal), March 1996, p. 76 etc.

On the other hand, since a relative dielectric constant of about 2.0 to 2.5 can be obtained with an organic material-based low dielectric constant insulator film, it is expected to be used as an interlayer insulating film for next-generation and higher-integration semiconductor devices. large. Organic insulating film materials are roughly classified into hydrocarbon resins and fluorine resins. As the hydrocarbon resin,
Organic SOG having a siloxane bond (Spin OnG
las), polyimide, polyparaxylylene (trade name: parylene), polyarylether (trade name: flare),
Polymer materials such as polybenzocyclobutene and polynaphthalene are known. These materials achieve a low dielectric constant by reducing the density by containing carbon atoms and by decreasing the polarizability of the polymer material itself. In addition, a certain degree of heat resistance is obtained by introducing a siloxane bond, an imide bond, or an aromatic ring.

Examples of the fluorine resin include Teflon (trade name), Cytop (trade name), and fluororesin-based organic polymer materials such as polyimide containing perfluoro group and fluorinated polyaryl ether. In these fluorine-based resins, the introduction of a C—F bond having a low polarizability achieves a further lower dielectric constant than that of a hydrocarbon-based resin.
However, this CF bond has poor heat resistance, and is often used for sintering of Al-based metal wiring, for example.
Since the quality may change due to heat treatment at about ° C, consideration must be given to compatibility with the current LSI process.

These low dielectric constant material layers are applied not only between adjacent wirings but also between wiring layers of different levels, and the low dielectric constant material layers are excellent in film quality such as SiO ₂ , SiON and Si ₃ N ₄ . The present applicant discloses in Japanese Patent Application Laid-Open No. Hei 8-162528 a laminated interlayer insulating film having a structure sandwiched between insulating films to prevent the influence of corrosion of a wiring layer and the like, which has a low dielectric constant and high reliability. The possibility of a semiconductor device having an insulating film was shown.

On the other hand, due to the recent miniaturization of design rules for highly integrated semiconductor devices, the aspect ratio of connection holes in a multilayer wiring structure has been increased, and dual damascene (Dual Damascene) has been developed.
It is required to employ a trench wiring structure typified by the Damascene method. For this reason, the difficulty of the etching step when forming an opening pattern in a silicon oxide-based interlayer insulating film is increasing more and more.

[0011]

In the anisotropic etching step for forming an opening pattern having a high aspect ratio in a silicon oxide-based interlayer insulating film, the injection of a fluorocarbon polymer precursor, particularly the use of CF-based ions such as CF ions and CF radicals, is carried out. Recent studies have revealed that the incidence of active species on the bottom of the aperture pattern is important. However, it has been substantially difficult to obtain an amount of CF-based active species necessary for incidence on the bottom of the opening pattern from only an etching gas containing a CF-based gas. For this reason, the incidence of CF-based active species inside the connection holes or grooves having a high aspect ratio is insufficient, and a phenomenon called a so-called etch stop in which the etching is stopped during the opening process may occur.

The present invention has been made in view of such a technical background. In the present invention, connection holes and grooves having a high aspect ratio are formed with high precision in an interlayer insulating film of a highly integrated semiconductor device, and fluorine is added. It is an object of the present invention to provide a method of manufacturing a highly integrated semiconductor device with reduced inter-wiring capacitance using a low dielectric constant organic interlayer insulating film including a part of a laminated interlayer insulating film.

[0013]

SUMMARY OF THE INVENTION A method of manufacturing a semiconductor device according to the present invention is proposed to solve the above-mentioned problem. An organic interlayer insulating film containing fluorine is formed on a silicon oxide interlayer insulating film. Forming an opening pattern of the silicon oxide-based interlayer insulating film by etching the silicon oxide-based interlayer insulating film using at least the organic interlayer insulating film containing fluorine as an etching mask; A step of embedding a conductive material in the opening pattern of the stacked interlayer insulating film formed by the opening pattern of the organic interlayer insulating film including the opening pattern of the silicon oxide based interlayer insulating film. And

At the time of etching the silicon oxide-based interlayer insulating film, an etching gas containing a CF-based gas is used, and a CF-based active species generated by sputtering the fluorine-containing organic interlayer insulating film is removed. An opening pattern of a silicon oxide-based interlayer insulating film is formed while being supplied into the opening pattern of the system-based interlayer insulating film.

The opening pattern of the laminated interlayer insulating film obtained by the method of manufacturing a semiconductor device according to the present invention can be suitably used as a connection hole pattern such as a contact hole or a via hole or a groove pattern for groove wiring. The relative dielectric constant of the fluorine-containing organic interlayer insulating film is preferably smaller than the relative dielectric constant of the silicon oxide-based interlayer insulating film.

As the silicon oxide-based interlayer insulating film, Si
O ₂ , PSG, BSG, BPSG, AsSG, SiON
Alternatively, SOG or the like can be exemplified. As the organic interlayer insulating film containing fluorine, Cyclo Per is used.
Fluorocarbon Polymer (trade name:
Any of fluorocarbon resins or fluorocarbon resins such as CYTOP, fluorinated polyimide, fluorinated polyarylether, or Teflon (trade name) can be used.

Next, the operation will be described. The point of the present invention is that the opening pattern of the organic interlayer insulating film containing fluorine is used as an etching mask when forming the opening pattern of the silicon oxide based interlayer insulating film, and the organic interlayer containing fluorine is used as necessary. The point is that the opening pattern of the insulating film is used as a part of the laminated interlayer insulating film. The opening pattern of the silicon oxide-based interlayer insulating film can be used as a protective film of a fluorine-containing organic interlayer insulating film or a part thereof.

Generally, a photoresist such as a novolak resin is used as an etching mask when forming an opening pattern such as a connection hole or a groove for a groove wiring in a silicon oxide-based interlayer insulating film. Since this photoresist contains a large amount of hydrogen as a constituent element, fluorine is selectively scavenged from etching species such as fluorocarbon radicals and ions that enter the substrate to be etched from plasma during etching. Therefore, the etching species in the vicinity of the surface of the substrate to be etched tends to be carbon-rich, the C / F ratio increases, and the deposition property of the etching reaction system increases. Therefore, the etching rate is reduced when processing an opening pattern such as a connection hole having a small opening width and a large aspect ratio or a groove for a groove wiring, or an etch stop occurs in an extreme case. Note that the C / F ratio is a parameter indicating the balance between the carbon-based deposition species and the fluorine-based etching species in the etching reaction system. It is possible to optimize each etching condition of the ratio and the etching rate.

Conventionally, in consideration of the amount of scavenging of fluorine caused by the photoresist, the type of etching gas, the added gas, and the mixing ratio thereof have been adjusted to set the etching conditions. However, in the present situation where design rules are miniaturized and high-precision etching technology is required, an electron energy distribution function (EEDF;
Electron Energy Distribut
It is difficult to control the dissociation generated radicals at the time of plasma discharge, because the ion function is not clear and the relationship between EEDF and etching gas dissociation is not clear. Therefore, it was not possible to simultaneously satisfy various characteristics such as anisotropy, selectivity and etching rate at a high level.

In the present invention, an opening of an organic interlayer insulating film containing fluorine such as fluorocarbon resin is used as an etching mask when forming an opening pattern such as a connection hole or a groove for trench wiring in the silicon oxide based interlayer insulating film. Use a pattern. For this reason, hydrogen is reduced or eliminated from the constituent elements in the etching mask, and accordingly, fluorine is selectively scavenged from etching species such as fluorocarbon radicals and ions that enter the substrate to be etched from the plasma during etching. The phenomenon is reduced or eliminated. In addition, CF-based active species such as CF and CF ₂ are supplied to the etching reaction system as a sputtering product from the etching mask. Therefore, a large amount of CF-based active species, which is difficult to actively control only by the dissociation product of the etching gas, is supplied into the opening pattern such as the connection hole or the groove for the groove wiring, and the anisotropy, the selectivity, and the Various characteristics such as an etching rate can be simultaneously satisfied at a high level.

As an etching mask for forming an opening pattern in the organic interlayer insulating film containing fluorine, it is desirable to use a silicone-containing resist mask, a surface silylated resist mask, or an inorganic mask such as SiO ₂ . Since the silicon-containing resist mask or the surface silylated resist mask contains Si atoms in the film, the surface thereof is modified into a SiO _x layer by oxygen plasma irradiation. Utilizing this phenomenon, by using oxygen-based gas in etching of the organic interlayer insulating film containing fluorine and SiO _x the resist mask surface. Surface is S
and iO _x reduction resist mask, the inorganic mask such as SiO ₂ are not etched in the oxygen-based gas. Moreover, since the organic interlayer insulating film containing fluorine, which is the film to be etched, is easily etched by the combustion reaction, a high selectivity can be easily achieved, and an opening pattern is formed on the organic interlayer insulating film containing fluorine with high precision. You can do it. In this case, by controlling the substrate to be etched below room temperature, the isotropic radical reaction in the etching step is frozen, pattern abnormalities such as undercut and bowing are prevented, and highly accurate anisotropic processing is performed. of course,
Even when a silicon oxide-based interlayer insulating film is patterned using a fluorine-containing organic interlayer insulating film pattern as a mask, anisotropic processing with higher accuracy can be performed by controlling the substrate to be etched to room temperature or lower.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of the present invention will be described with reference to the drawings, but these are merely examples, and the present invention is not limited to these embodiments. Absent.

The basic configuration of the etching apparatus employed in the following embodiments is a magnetron type parallel plate type plasma etching apparatus (hereinafter, referred to as a magnetron RIE apparatus). The substrate stage has a cooling jacket made of aluminum metal. The cooling jacket made of aluminum metal has a refrigerant pipe as a cooling means, an embedded heater as a heating means, an electrode for an electrostatic chuck, a dielectric for an electrostatic chuck, and an electrostatic chuck. It is composed of a dielectric brazing layer, a temperature sensor and the like. This aluminum cooling jacket consists of an aluminum refrigerant pipe and a sheath heater (embedded heater).
Was poured into a mold, and molten aluminum was poured into the mold, followed by press casting under reduced pressure. According to this method, bubbles and voids are not generated in the aluminum metal as in ordinary casting, and a pre-patterned refrigerant pipe, an embedded heater, and the like can be easily integrated, and the production is simple, Moreover, the same quality as that produced by cutting out an aluminum block can be obtained. A dielectric for electrostatic chuck is joined to the aluminum metal cooling jacket with a brazing layer also serving as an electrode for electrostatic chuck, thereby forming a substrate stage.

The substrate stage has a refrigerant circulating device, H
A heating medium supply device for e-gas and the like, a temperature sensor, and the like are attached. This refrigerant circulating device includes a chiller capable of supplying a refrigerant such as Freon and ethanol, a piping line for circulating the refrigerant, and the like. A bypass line is provided in the piping line, and these are connected by a valve which can operate at a very low temperature. This valve detects a change in the temperature of the substrate to be etched and performs an opening / closing operation based on a preset temperature program. That is, the difference between the desired set temperature and the current substrate temperature to be etched is calculated,
If rapid cooling is required, open the valve on the piping line. If fine temperature control is required, open and close the valve on the bypass line and turn on / off the embedded heater to precisely control the temperature of the substrate to be etched. . Each control element of the above-described plasma etching apparatus can be uniformly controlled by a central processing control device such as a microcomputer by a preset program.

By employing the above-described etching apparatus, the substrate to be etched on which the laminated interlayer insulating film including the fluorine-containing organic interlayer insulating film and the silicon oxide-based interlayer insulating film are formed is controlled to room temperature or lower as required, ie, cooled. While anisotropic patterning can be performed. Since the cooling and heating of the substrate to be etched can be switched in a short time, patterning of the laminated interlayer insulating film and dew condensation at the time of carrying out the substrate to be etched can be prevented. Hereinafter, more specific examples of the present invention will be described.

Embodiment 1 This embodiment is an example in which a contact hole is formed in a laminated interlayer insulating film formed on a semiconductor substrate and formed of a silicon oxide-based interlayer insulating film and an organic interlayer insulating film containing fluorine. This step will be described with reference to FIGS.

As shown in FIG. 1A, a sample employed in this embodiment is a TEOS as a silicon oxide-based interlayer insulating film 2 on a semiconductor substrate 1 of silicon or the like on which elements such as transistors (not shown) are formed. (Tetra Ethyl Or
An SiO ₂ film formed by plasma CVD using oxygen as a raw material gas is, for example, 8
Cyclo Per Fluoro, which is formed to a thickness of 00 nm and further serves as an organic interlayer insulating film 3 containing fluorine.
Carbon Polymer (trade name: Cytop) is spin-coated to a thickness of, for example, 1 μm and baked.

Next, as shown in FIG. 1 (b), a commercially available silicone-containing resist film 4 is applied to a thickness of 0.1 nm, and subjected to a photolithography step to obtain a 0.18 μm thick film.
An opening pattern 4a of a silicone-containing resist film having an opening diameter of m is formed.

The substrate to be etched shown in FIG. 1B is set on the substrate stage of the magnetron RIE apparatus described above, and the organic interlayer insulating film 3 containing fluorine is etched using the silicon-containing resist film 4 as an etching mask. An example of the etching conditions is shown below. O ₂ 50 sccm pressure 1 Pa RF power 1500 W substrate to be etched temperature −50 ° C.

[0030] In this etching process, by irradiation of oxygen plasma or oxygen ions, because the silicone-containing resist film 4 surface is SiO _x of increased etching resistance, etching selectivity of the organic interlayer insulating film 3 containing fluorine Is sufficiently secured. In addition, by controlling the substrate to be etched to a room temperature or lower, in this example, to -50 ° C.,
The radical reaction is suppressed, undercuts and bowing do not occur, and highly anisotropic etching can be performed. As a result, as shown in FIG. 1C, the shape of the opening pattern 4a of the silicone-containing resist film is transferred to the organic interlayer insulating film 3 containing fluorine, and the opening pattern 3a of the organic interlayer insulating film containing fluorine is formed. Is done. The width of the opening pattern 3a of the fluorine-containing organic interlayer insulating film is about 0.18, which is almost the same as the width of the opening pattern 4a of the silicone-containing resist film.
μm.

Next, the etching conditions are switched, and the silicon oxide-based interlayer insulating film 2 is patterned. An example of this etching condition is shown below. _{C 4 F 8 8 sccm CO 50} sccm Ar 150 sccm O 2 2 sccm Pressure 1 Pa RF power 1500 W to be etched substrate temperature 30 ° C.

In this etching step, FIG.
As shown in (d), the silicon-containing resist film 4 is also etched, so that its thickness is reduced, and is etched off at a relatively early stage of etching, and thereafter, the exposed organic interlayer insulating film containing fluorine. Etching proceeds using 3 as an etching mask. At this stage, CF-based active species are released as sputter products of the organic interlayer insulating film 3 containing fluorine, and contribute to the etching of the silicon oxide-based interlayer insulating film 2 together with the CF-based active species generated from the etching gas. Therefore, despite etching at the bottom of the opening pattern having a large aspect ratio, an etch stop does not occur as in the case of using a normal resist mask or an inorganic hard mask, while preventing excessive polymer deposition. An opening pattern 2a of a silicon oxide-based interlayer insulating film is formed. Figure 2 shows the state after etching is completed.
(E). The width of the opening pattern 2a of the silicon oxide-based interlayer insulating film is substantially the same as the width of the opening pattern 4a of the silicone-containing resist film shown in FIG.
Met.

The aspect ratio of the contact hole formed by the opening pattern 2a of the silicon oxide-based interlayer insulating film and the opening pattern 3a of the organic interlayer insulating film containing fluorine is such that the thickness of the organic interlayer insulating film 3 containing fluorine is small. It was about 9 because it was reduced by sputtering.

Thereafter, as shown in FIG. 2F, the conductive material 5 is placed in the contact holes formed by the opening pattern 2a of the silicon oxide-based interlayer insulating film and the opening pattern 3a of the organic interlayer insulating film containing fluorine. Embedding and forming a contact plug. The conductive material 5 may be any of an Al-based metal, a refractory metal such as W or Ti, a refractory metal nitride such as TiN, polycrystalline silicon, or a laminated material thereof. Any of a chemical vapor deposition (CVD) method and the like may be used. After the formation of the conductive material, the surface thereof may be planarized by etch back or chemical mechanical polishing (CMP).

According to this embodiment, an organic interlayer insulating film containing fluorine is used as an etching mask for the silicon oxide based interlayer insulating film, and the organic interlayer insulating film containing fluorine is used as a part of the laminated interlayer insulating film. By employing this, a fine contact hole with a high aspect ratio can be formed with good controllability, and at the same time, a semiconductor device having a low dielectric constant laminated interlayer insulating film can be provided.

Embodiment 2 In this embodiment, a trench wiring is formed by a dual damascene method on a laminated interlayer insulating film formed of a silicon oxide-based interlayer insulating film and an organic interlayer insulating film containing fluorine formed on an Al-based metal wiring. FIG. 3 is an example in which a groove pattern is formed.
This will be described with reference to FIGS. Note that in FIGS. 3 to 5, the same reference numerals are given to components similar to the components in FIGS. 1 and 2 referred to in the first embodiment.

As shown in FIG. 3A, the sample employed in this embodiment is an Al film formed on a lower interlayer insulating film (not shown).
Silicon oxide based interlayer insulating film (lower layer) on base metal wiring 6
21, an etching stopper layer 7, a silicon oxide-based interlayer insulating film (upper layer) 22, and an organic interlayer insulating film 3 containing fluorine are sequentially formed. Of these, the etching stopper layer 7 is formed of S
Except for using i ₃ N _4, the materials and film forming methods of the silicon oxide-based interlayer insulating film (lower layer) 21, the silicon oxide-based interlayer insulating film (upper layer) 22, and the organic interlayer insulating film 3 containing fluorine are the same as those of the previous embodiment. 1 is the same as that of FIG.
The thickness of each layer is, for example, a silicon oxide-based interlayer insulating film (lower layer) 21 and a silicon oxide-based interlayer insulating film (upper layer) 22
Are both 500 nm, and the etching stopper layer 7 is 10 n
m, the thickness of the organic interlayer insulating film 3 containing fluorine is 1.0 μm.

Next, as shown in FIG. 3B, a commercially available silicone-containing resist film 4 is applied to a thickness of 0.1 nm, and is subjected to a photolithography process to obtain a 0.18 μm thick film.
An opening pattern 4a of a silicone-containing resist film having an opening diameter of m is formed.

The substrate to be etched shown in FIG. 3B is set on the substrate stage of the magnetron RIE apparatus described above, and the organic interlayer insulating film 3 containing fluorine is etched using the silicon-containing resist film 4 as an etching mask. . An example of the etching conditions is shown below. O ₂ 50 sccm pressure 1 Pa RF power 1500 W substrate to be etched temperature −50 ° C.

[0040] In this etching process, by irradiation of oxygen plasma or oxygen ions, because the silicone-containing resist film 4 surface is SiO _x of increased etching resistance, etching selectivity of the organic interlayer insulating film 3 containing fluorine Is sufficiently secured. In addition, by controlling the substrate to be etched to a room temperature or lower, in this example, to -50 ° C.,
The radical reaction is suppressed, undercuts and bowing do not occur, and highly anisotropic etching can be performed. Etching stops on the silicon oxide-based interlayer insulating film (upper layer) 22. As a result, as shown in FIG. 3C, the shape of the opening pattern 4a of the silicone-containing resist film is transferred to the fluorine-containing organic interlayer insulating film 3, and the opening pattern 3a of the fluorine-containing organic interlayer insulating film is changed. It is formed. The width of the opening pattern 3a of the fluorine-containing organic interlayer insulating film was 0.18 μm, which was almost the same as the width of the opening pattern 4a of the silicone-containing resist film.

Next, the etching conditions are switched, and the silicon oxide-based interlayer insulating film 2 is patterned. An example of this etching condition is shown below. _{C 4 F 8 8 sccm CO 50} sccm Ar 150 sccm O 2 2 sccm Pressure 1 Pa RF power 1500 W to be etched substrate temperature 30 ° C.

In this etching step, the thin silicone-containing resist film 4 is etched off at an early stage of the etching, and the etching proceeds using the exposed organic interlayer insulating film 3 containing fluorine as an etching mask. At this stage, CF-based active species are released as sputter products of the organic interlayer insulating film 3 containing fluorine, and contribute to the etching of the silicon oxide-based interlayer insulating film 2 together with the CF-based active species generated from the etching gas. Therefore, despite etching at the bottom of the opening pattern having a large aspect ratio, an etch stop does not occur as in the case of using a normal resist mask or an inorganic hard mask, while preventing excessive polymer deposition. An opening pattern 2a of a silicon oxide-based interlayer insulating film is formed. FIG. 4D shows the state after the completion of the etching. FIG.
The width of the opening pattern 4a of the silicone-containing resist film shown in FIG.

Thereafter, in the present embodiment, the organic interlayer insulating film 3 containing fluorine is entirely removed by oxygen plasma.
Cycl is again used as the organic interlayer insulating film 3 containing fluorine.
oPer Fluorocarbon Polymer
(Trade name: Cytop) is spin-coated to a thickness of, for example, 1 μm to form a baked product. Next, as shown in FIG. 4 (e), a commercially available silicone-containing resist film 4 is applied to a thickness of 0.1 nm and subjected to a photolithography process to form a silicone-containing resist film having an opening diameter of, for example, 0.25 μm. An opening pattern 4a is formed. The position of the opening pattern 4a of the silicone-containing resist film is aligned with the opening pattern 2a of the silicon oxide-based interlayer insulating film.

The substrate to be etched shown in FIG. 4E is again set on the substrate stage of the magnetron RIE apparatus described above, and the organic interlayer insulating film 3 containing fluorine is etched using the silicon-containing resist film 4 as an etching mask. . An example of the etching conditions is shown below. O ₂ 50 sccm pressure 1 Pa RF power 1500 W substrate to be etched temperature −50 ° C.

[0045] In this etching process, by irradiation of oxygen plasma or oxygen ions, because the silicone-containing resist film 4 surface is SiO _x of increased etching resistance, etching selectivity of the organic interlayer insulating film 3 containing fluorine Is sufficiently secured. In addition, by controlling the substrate to be etched to a room temperature or lower, in this example, to -50 ° C.,
The radical reaction is suppressed, undercuts and bowing do not occur, and highly anisotropic etching can be performed. As a result, as shown in FIG. 4F, the shape of the opening pattern 4a of the silicone-containing resist film is transferred to the organic interlayer insulating film 3 containing fluorine, and the opening pattern 3a of the organic interlayer insulating film containing fluorine is formed. Is done. The width of the opening pattern 3a of the fluorine-containing organic interlayer insulating film is substantially the same as the width of the opening pattern 4a of the silicone-containing resist film, ie, 0.25.
μm. Subsequently, over-etching is performed to form an opening pattern 2 of the silicon oxide-based interlayer insulating film.
Ashing also removes the organic interlayer insulating film 3 containing fluorine in a.

Next, the etching conditions are switched, and the silicon oxide-based interlayer insulating film 2 is patterned. An example of this etching condition is shown below. _{C 4 F 8 8 sccm CO 100} sccm Ar 100 sccm O 2 2 sccm Pressure 1 Pa RF power 1500 W to be etched substrate temperature 30 ° C.

In this etching step, the thin silicon-containing resist film 4 is etched off at an early stage of the etching, and the etching proceeds using the exposed organic interlayer insulating film 3 containing fluorine as an etching mask. At this stage, CF-based active species are released as a sputter product of the organic interlayer insulating film 3 containing fluorine, and contribute to the etching of the silicon oxide-based interlayer insulating film (upper layer) 22 together with the CF-based active species generated from the etching gas. I do. Therefore, despite the etching at the bottom of the opening pattern having a relatively large aspect ratio, excessive polymer deposition is prevented without generating an etch stop unlike the case of using a normal resist mask or an inorganic hard mask. While opening, the opening pattern 22a of the silicon oxide based interlayer insulating film (upper layer) is formed. The etching stops on the etching stopper layer 7 made of Si ₃ N ₄ by increasing the mixing ratio of CO. FIG. 5G shows a state where the groove for the dual damascene wiring is completed.

Thereafter, as shown in FIG. 5H, a conductive material 5 is buried in the groove for the dual damascene wiring to form a groove wiring. As the conductive material 5, Al-based metal, W or Ti
, High-melting metal nitride such as TiN, polycrystalline silicon, etc., and the film forming method thereof is also vapor deposition, sputtering or chemical vapor deposition (CVD).
It may be any of the methods. After the formation of the conductive material, the surface thereof may be planarized by etch back or chemical mechanical polishing (CMP).

According to the present embodiment, an organic interlayer insulating film containing fluorine is used as an etching mask for the silicon oxide based interlayer insulating film, and this organic interlayer insulating film containing fluorine is optionally used to form a laminated interlayer insulating film. By adopting a part as it is, a groove for groove wiring can be formed with good controllability, and at the same time, a semiconductor device having a groove wiring formed in a laminated interlayer insulating film having a low dielectric constant can be provided.

Although the present invention has been described in detail with reference to two examples, the present invention is not limited to these examples.

For example, in the first embodiment, the step of forming a contact hole facing a semiconductor substrate is illustrated, but the present invention may be applied to a step of forming a via hole facing a lower wiring.

In the second embodiment, the present invention is applied to the dual damascene process for simultaneously forming the groove wiring and the connection hole. However, it is needless to say that the present invention may be applied to a so-called damascene process for simply forming the groove wiring.

PSG, BSG, BP containing impurities other than SiO ₂ exemplified as the silicon oxide-based interlayer insulating film
SG or AsSG or a laminated interlayer insulating film of these materials may be used.
Various CVD methods such as D, a sputtering method, and a spin coating method may be employed.

As an organic interlayer insulating film containing fluorine, C
Cyclo Perfluorocarbon Poly
Although mer (trade name: Cytop) is illustrated, any fluorocarbon resin such as fluorinated polyimide, fluorinated polyaryl ether, or Teflon (trade name) can be used. In addition, as the film forming method, a vapor phase growth method such as a plasma CVD method can be used in addition to the coating method.

In addition to the semiconductor device, the present invention is also applicable to a case where an organic interlayer insulating film containing fluorine having a low dielectric constant is used for various high-frequency microelectronic devices such as a thin film head and a thin film inductor. Needless to say.

[0056]

As is apparent from the above description, according to the method of manufacturing a semiconductor device of the present invention, connection holes and grooves having a high aspect ratio are formed with high precision in an interlayer insulating film of a highly integrated semiconductor device. It is possible to provide a method for manufacturing a highly integrated semiconductor device with reduced inter-wiring capacitance, using a low dielectric constant organic interlayer insulating film containing fluorine as a part of the interlayer insulating film. Becomes

[Brief description of the drawings]

FIG. 1 is a schematic cross-sectional view illustrating a process of Example 1 of the present invention.

FIG. 2 is a schematic cross-sectional view illustrating a step of Example 1 of the present invention following the step of FIG.

FIG. 3 is a schematic cross-sectional view illustrating a process according to a second embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view for explaining a process of Example 2 of the present invention following the process of FIG. 3;

FIG. 5 is a schematic cross-sectional view illustrating a step of Example 2 of the present invention following the step of FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Silicon oxide type interlayer insulating film, 2a
... opening pattern of silicon oxide based interlayer insulating film, 3 ... organic interlayer insulating film containing fluorine, 3a ... opening pattern of organic interlayer insulating film containing fluorine, 4 ... silicone containing resist film, 4a ... silicone containing resist film Opening pattern, 5: conductive material, 6: Al-based metal wiring, 7: etching stopper layer

Claims (5)

[Claims] A step of forming an opening pattern of a fluorine-containing organic interlayer insulating film on the silicon oxide-based interlayer insulating film, wherein at least the fluorine-containing organic interlayer insulating film is used as an etching mask; Etching an insulating film to form an opening pattern of the silicon oxide based interlayer insulating film; an opening pattern of the fluorine-containing organic based interlayer insulating film;
A method of manufacturing a semiconductor device, comprising: a step of burying a conductive material in an opening pattern of a laminated interlayer insulating film formed by the opening pattern of the silicon oxide-based interlayer insulating film. 2. An etching gas containing a CF-based gas is used for etching the silicon oxide-based interlayer insulating film, and a CF-based active species generated by sputtering the fluorine-containing organic interlayer insulating film is formed. 2. The method for manufacturing a semiconductor device according to claim 1, wherein an opening pattern of the silicon oxide-based interlayer insulating film is formed while being supplied into an opening pattern of the silicon oxide-based interlayer insulating film. 3. An opening pattern of the laminated interlayer insulating film,
2. The method according to claim 1, wherein the pattern is a connection hole pattern. 4. An opening pattern of the laminated interlayer insulating film,
2. A groove pattern for groove wiring.
The manufacturing method of the semiconductor device described in the above. 5. The method according to claim 1, wherein a relative dielectric constant of the fluorine-containing organic interlayer insulating film is smaller than a relative dielectric constant of the silicon oxide-based interlayer insulating film.