JPH11311660A - Semiconductor-testing device and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor-testing device that is capable of being miniaturized and reducing cost by simplifying a circuit configuration. SOLUTION: In a semiconductor-testing device, a test signal 6a, that is generated by a timing control part 2, a pattern control part 3, a pattern memory part 41, a formatter 42, and a driver 6 is inputted to a DUT 8 for processing, an output signal 8a that is outputted from an output terminal 82 of the DUT 8 is compared with a preset value by a comparator 7, counting is executed by a counter 43 in synchronization with the rising, when the output of the comparison logic signal 7a changes from a Lo level to a Hi level, the count value of the counter 43 when the testing of the DUT 8 is completed is compared with a count value, when the testing by a conforming semiconductor device is completed, and the comparison result is outputted as a determining signal 1b.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for a semiconductor device, and more particularly, to a semiconductor device to be tested, which inputs a predetermined signal to execute a process, and executes a process based on a processing result. The present invention relates to a semiconductor device test apparatus for determining the quality of a device.

[0002]

2. Description of the Related Art In the process of manufacturing a semiconductor device such as an IC (Integrated Circuit), variations in characteristics may occur between products. For this reason, in general, in a semiconductor device manufacturing process, a semiconductor device test is often performed in order to detect a product whose characteristics are out of a predetermined range.

In a test of a semiconductor device, a predetermined signal is usually input to a device under test to be tested, and a process is executed based on the signal. Then, the obtained processing result is compared with an expected value stored in the semiconductor test apparatus in advance to determine whether the device under test is a non-defective product.

FIG. 2 is a block diagram showing a schematic configuration of a semiconductor test apparatus 100 as an example of a conventional semiconductor device test apparatus. As shown in FIG.
00 is a timing control unit 10, a pattern control unit 11, a pattern control unit 12, a driver / comparator unit 5.
And a DUT 8 which is a semiconductor device to be tested.
3, a formatter 14 and a determination circuit 15. The driver / comparator unit 5 includes a driver 6 and a comparator 7.

The DUT 8 by the semiconductor test apparatus 100
In the test of (1), the reference clock signal 10a is output from the timing control unit 10 to the pattern control unit 11 and the pattern memory unit 13, and the judgment circuit 1
5, the timing control unit 10C is output. When the reference clock signal 10 a is input to the pattern control unit 11, a pattern address signal 11 a is generated according to the reference clock signal 10 a and output to the pattern memory unit 13.

The pattern memory unit 13 stores a plurality of pattern data for testing the DUT 8 in association with the pattern addresses. This pattern memory unit 13
Pattern address signal 11 from pattern control unit 11
When "a" is input, the pattern data corresponding to the pattern address signal 11a is read and output to the formatter 14 as pattern data 13a in synchronization with the reference clock signal 10a input from the timing controller 10. The pattern memory unit 13 stores an expected value which is a result obtained when the DUT 8 is a non-defective semiconductor device, and the expected value 13b is synchronized with the reference clock signal 10a. Is output to In the formatter 14, an input test signal 14a is generated based on the pattern data 13a input from the pattern memory unit 13.
Is generated and output to the driver 6 in synchronization with the timing edge 10c input from the timing control unit 10.

The driver 6 generates a test signal 6 a based on the input test signal 14 a input from the formatter 14, outputs the test signal 6 a to the input terminal 81 of the DUT 8,
8 executes processing based on the test signal 6a input to the input terminal 81.

The processing result obtained by executing the processing by the DUT 8 is output from the output terminal 82 of the DUT 8 to the output signal 8.
It is output to the comparator 7 as a. Then, in the comparator 7, a preset set voltage value and D
The output signal 8a is compared with the output signal 8a input from the UT 8, and the comparison result is output to the determination circuit 15 as a comparison logic signal 7a.

In the determination circuit 15, when the strobe edge 10c is input from the timing control unit 10,
The comparison logic signal 7a input from the comparator 7 is compared with the expected value 13b input from the pattern memory unit 13, and a determination signal 15a indicating the result of the comparison is output to a device (not shown) not shown. .

Then, based on the judgment signal 15a output from the judgment circuit 15, it is judged whether the DUT 8 is a non-defective product which satisfies the standard or has a characteristic deviating from a predetermined range.

[0011]

However, in the above-described semiconductor test apparatus 100, the processing result obtained based on the processing executed by the DUT 8 is determined by the determination circuit 15.
Was compared with the expected value 13b in the judgment circuit 1
5, and further, it was necessary to input the expected value 13b to the determination circuit 15. by this,
Since the circuit configuration becomes complicated, there is a problem that it is difficult to reduce the size of the device, resulting in an increase in cost.

[0012] The present invention has been made in order to solve the above problems.
It is an object of the present invention to provide a semiconductor test apparatus capable of reducing the size and the cost by simplifying the circuit configuration.

[0013]

According to an aspect of the present invention, a semiconductor device to be tested executes a process based on a predetermined signal, and a process is performed on the basis of an obtained process result. In a semiconductor test apparatus for determining pass / fail of a semiconductor device to be tested, test signal output means for outputting a test signal, and processing is performed on the semiconductor device to be tested based on the test signal output from the test signal output means. And outputting a voltage value corresponding to the obtained processing result, and comparing the voltage value output from the testing means with a preset voltage value to indicate a comparison result. A comparing means for outputting a signal; a counting means for executing a count in accordance with the content of the comparison signal outputted by the comparing means to output a count value; and a signal outputted from the test signal output means. A count value storage unit that stores a count value output from the counting unit when the non-defective semiconductor device performs a process in advance based on the test signal; a count value output from the counting unit; Count value comparison means for comparing the count value stored in the count value storage means,
And a configuration characterized by comprising:

According to the first aspect of the present invention, the test target semiconductor device is caused to execute processing based on the predetermined signal, and the pass / fail of the test target semiconductor device is determined based on the obtained processing result. In a semiconductor test apparatus, a test signal is output by test signal output means, and the test means causes a test target semiconductor device to execute processing based on the test signal, and outputs a voltage value corresponding to the obtained processing result. Then, the output voltage value is compared with a preset voltage value by comparing means, and a comparison signal indicating a comparison result is output. According to the content of the comparison signal output by the comparing means, counting is performed. Means for executing a count and outputting a count value, and a count value storage means for executing a process on a good semiconductor device in advance based on the test signal output from the test signal output means. Storing the count value output from the counting means when allowed by the count value comparing means, for comparing the count and the numerical output from the counting means and a count value stored in the count storage means.

According to a fourth aspect of the present invention, a semiconductor device to be tested performs a process based on a predetermined signal, and the quality of the semiconductor device to be tested is determined based on the obtained processing result. A semiconductor test method in a semiconductor test apparatus, comprising: outputting a test signal; causing the test target semiconductor device to execute processing based on the test signal; and outputting a voltage value corresponding to an obtained processing result. ,
The output voltage value is compared with a preset voltage value, a comparison result is output as a comparison signal, counting is performed according to the content of the comparison signal, and based on the test signal,
Store the count value output when the non-defective semiconductor device performs the process in advance, and the stored count value,
It is characterized in that it is compared with a count value at the end of processing by the semiconductor device to be tested.

Therefore, the processing result obtained by causing the semiconductor device to be tested to execute the processing is compared with a preset numerical value, and the value of the comparison signal changes depending on whether or not they match. The counting is executed according to. Here, by comparing the count value when using a good semiconductor device and the count value when using the semiconductor device to be tested, it is possible to determine the quality of the semiconductor device to be tested. Thus, the semiconductor test device can be realized with a simpler circuit configuration, and the size and cost of the entire device can be reduced.

According to a second aspect of the present invention, in the semiconductor test apparatus according to the first aspect, the comparing means outputs a logical value signal indicating a result of the comparison as a comparison signal, and the counting means outputs the logical value signal from the comparing means. The counting is performed in synchronization with a change in the output comparison signal.

According to the second aspect of the present invention, in the semiconductor test apparatus according to the first aspect, the comparing means outputs a logical value signal indicating a result of the comparison as a comparison signal, and the counting means outputs the logical value signal from the comparing means. The counting is performed in synchronization with the change of the output comparison signal.

Here, the comparison signal is, for example, a logical value taking a value between the 'Lo' level and the 'Hi' level, and the counting means determines that the comparison signal has changed from the 'Lo' level to the 'Hi' level. May be detected and counting is performed in synchronization with the rise of the comparison signal.

Therefore, by performing processing based on simpler signals in the comparing means and the counting means, the circuit configuration can be made simpler, and the size and cost can be further reduced. Can be.

According to a third aspect of the present invention, there is provided a semiconductor test apparatus for causing a semiconductor device to be tested to execute processing based on a predetermined signal, and determining whether the semiconductor device to be tested is good or bad based on the obtained processing result. In the apparatus, a test signal output unit that outputs a test signal, and a process is executed by the semiconductor device to be tested based on the test signal output from the test signal output unit, and the process result corresponds to the obtained processing result. A testing unit that outputs a voltage value; a comparing unit that compares a voltage value output from the testing unit with a preset voltage value and outputs a logical value indicating a comparison result as a comparison signal; Means for performing counting in response to a change in a comparison signal output from the comparing means when the non-defective semiconductor device performs processing, and outputting a count value to the first counting means. And when the test means executes processing of the semiconductor device under test, the count value output from the first count means is used as an initial value, and the change in the comparison signal output from the comparison means is used. A second counting means for performing a subtraction count in response thereto, and a determination result detecting means for detecting whether or not the second counting means has performed the reduction count to a predetermined value.

According to the third aspect of the present invention, the test target semiconductor device is caused to execute processing based on a predetermined signal, and the pass / fail of the test target semiconductor device is determined based on the obtained processing result. In a semiconductor test apparatus, a test signal is output by test signal output means, and based on the test signal, the test means causes a test target semiconductor device to execute processing, and a voltage value corresponding to the obtained processing result. The voltage value is compared with a preset voltage value by a comparing means, and a logical value indicating the comparison result is output as a comparison signal. The semiconductor device to be tested is tested by the test means by performing a count in response to a change in the comparison signal output from the comparison means when the device executes the processing, and outputting a count value. When performing the process, the second counting means performs a decrement count according to a change in the comparison signal output from the comparing means, using the count value output from the first counting means as an initial value, The second counting means detects whether the decrement count has been performed to a predetermined value.

According to a fifth aspect of the present invention, a semiconductor device to be tested executes a process based on a predetermined signal, and the quality of the semiconductor device to be tested is determined based on the obtained processing result. A semiconductor test method in a semiconductor test apparatus, comprising: outputting a test signal; causing the test target semiconductor device to execute processing based on the test signal; and outputting a voltage value corresponding to an obtained processing result. ,
This voltage value is compared with a preset voltage value, a logical value indicating the result of the comparison is output as a comparison signal, and when a non-defective semiconductor device performs a process, a change in the comparison signal is detected. Executing the counting in accordance with, storing the count value, when executing the processing of the semiconductor device under test,
Using the stored count value as an initial value, a subtrahend count is performed according to a change in the comparison signal, and it is detected whether the subtrahend count has been performed to a predetermined value.

Therefore, the processing result obtained by causing the semiconductor device under test to execute the processing is compared with a preset numerical value, and the value of the comparison signal changes depending on whether or not they match. By referring to the count value, the pass / fail of the semiconductor device to be tested can be determined. At this time, it is only necessary to perform down-counting based on the count value output when performing processing by a non-defective semiconductor device, and to detect whether or not down-counting has been performed to, for example, “0”. This can be realized by a simpler circuit configuration, and the size and cost of the entire device can be reduced.

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIG.

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor test apparatus 1 as an embodiment of the present invention. As shown in FIG. 1, the semiconductor test apparatus 1 includes a timing control unit 2, a pattern control unit 3, a pattern control unit 4, and a driver / comparator unit 5. A pattern memory unit 41, a formatter 42,
An UP / DOWN counter 43 and a coincidence circuit 44 are provided, and a driver 6 and a comparator 7 are provided in the driver / comparator unit 5. The output side of the driver 6 is connected to an input terminal 81 of a DUT (Device Under Test) 8, and the input side of the comparator 7 is connected to the DUT 8
Are connected to the output terminal 82 of Note that the same reference numerals are given to portions having the same configuration as the above-described conventional semiconductor test apparatus 100.

The timing control unit 2, the pattern control unit 3, the pattern memory unit 41, the formatter 42,
The UP / DOWN counter 43 and the coincidence circuit 44 include:
A test start signal 1a is sent from an unillustrated device (not shown).
Is entered.

The timing control unit 2 generates a test start signal 1a
Is generated, a reference clock signal 2a, which is a transmission signal of a predetermined frequency, is generated and output to the pattern control unit 3 and the pattern memory unit 41.
The edge 2b is generated and output to the formatter 42.

When the test start signal 1a is input, the pattern control section 3 receives the test clock signal 2a from the timing control section 2 and outputs a pattern memory section 41 based on the reference clock signal 2a.
Generates a pattern address signal 3a for designating appropriate pattern data from the pattern data stored in the
Output to the pattern memory unit 41.

The pattern memory unit 41 stores a plurality of pattern data according to the type of the test to be executed and the type of the DUT 8.
When a pattern address signal 3a is input from the pattern control unit 3 after the test start signal 1a is input, the pattern data corresponding to the pattern address signal 3a is read out and stored. The formatter 42 as the data 41a in synchronization with the reference clock signal 2a input from the timing controller 2.
Output to

After the test start signal 1a is input, the formatter 42 generates an input test signal 42a based on the pattern data 41a input from the pattern memory unit 41,
The input test signal 42a is output to the driver 6 according to the timing edge 2b input from the timing control unit 2.

When the input test signal 42a is input from the formatter 42, the driver 6 receives the input test signal 42a.
a is converted into a test signal 6 a and output to the input terminal 81 of the DUT 8.

The DUT 8 performs processing based on the test signal 6a input to the DUT 81, and outputs the processing result as an output signal 8a to the comparator 7 from the output terminal 82.

In the comparator 7, a predetermined voltage value is set in advance as a set voltage value. And D
When the output signal 8a is output from the output terminal 82 of the UT 8, the comparator 7 compares the output signal 8a with the set voltage value, and uses the comparison result as a comparison logic signal 7a, UP / DO.
Output to the WN counter 43. This comparison logic signal 7a
Is a logical value signal indicating the result of comparison by the comparator 7. For example, when the output signal 8a is smaller than the set voltage value, it is at the “Lo” level, and when the output signal 8a is larger than the set voltage value, Hi 'level.

The UP / DOWN counter 43 is a counter whose operation can be set in advance to an UP count or a DOWN count. Executed when rising from the Lo level to the Hi level. When the UP count is set, the count value is reset to “0” by inputting the test start signal 1a, and the count value is reset from “0” in synchronization with the change of the comparison signal 7a output from the comparator 7. Execute UP count. On the other hand, when the DOWN count is set, when the test start signal 1a is input, the DOWN count is set in synchronization with a change in the comparison signal 7a with a predetermined value as an initial value.
Perform a count. Here, as the predetermined value serving as the initial value, a count value obtained by executing an UP count operation when a test using a good semiconductor device is performed in advance is set. That is, in the test of DUT 8, D
If the count value is '0' as a result of the OWN count,
It can be determined that the DUT 8 is a non-defective product that performs the same operation as a non-defective semiconductor device. When the counting is completed, a count signal 43 a indicating the count value is output to the matching circuit 44.

The matching circuit 44 includes a storage medium therein,
In this storage medium, the count value of the UP / DOWN counter 43 at the end of the test when a good semiconductor device is tested is stored in advance. UP / DOWN
When the UP count is executed by the counter 43, the count value of the UP / DOWN counter 43 at the time when the test of the DUT 8 is completed is confirmed by the count signal 43a, and this count value is stored in the internal storage medium. And outputs a determination signal 1b indicating the comparison result to a device (not shown) (not shown). In addition, the UP / DOWN counter 43 outputs DO
When the WN count is executed, the count signal 43
a, DOW by the UP / DOWN counter 43
It is checked whether the N count has been executed up to '0'.

Therefore, when the UP / DOWN counter 43 counts up, the count value of the UP / DOWN counter 43 at the end of the test of the DUT 8 is stored in a storage medium provided in the matching circuit 44. It is determined whether the DUT 8 is a non-defective product by comparing the count value, that is, the result of processing by a non-defective semiconductor device. When the DOWN count is performed by the UP / DOWN counter 43, whether or not the DUT 8 is a non-defective product can be detected by detecting whether or not the count value is “0”. .

As described above, according to the semiconductor test apparatus 1 according to the embodiment of the present invention, the processing result of the DUT 8 is compared by the comparator 7 to output the comparison logic signal 7a. UP / DOW accordingly
The count is performed by the N counter 43, and the count value is output as a count signal 43a.
Whether the DUT 8 is non-defective by comparing it with the count value in processing by a non-defective semiconductor device stored in the matching circuit 44 or detecting whether the count value is '0' Can be determined, and the circuit configuration can be simplified, so that the entire device can be reduced in size and cost can be reduced.

In the semiconductor test apparatus 1 according to the present embodiment, the UP / DOWN counter 43 counts in accordance with the rise of the comparison logic signal 7a. Conversely, the UP / DOWN counter 43 counts in response to the rise of the comparison logic signal 7a. The configuration may be such that counting is performed in accordance with the falling, and the configuration of other details may be appropriately changed without departing from the spirit of the present invention.

[0040]

According to the first and fourth aspects of the present invention,
The processing result obtained by causing the semiconductor device under test to execute the processing is compared with a preset numerical value, and the value of the comparison signal changes depending on whether or not they match, so that counting is performed according to this change. Execute. Here, by comparing the count value when using a good semiconductor device and the count value when using the semiconductor device to be tested, it is possible to determine the quality of the semiconductor device to be tested. Thus, the semiconductor test device can be realized with a simpler circuit configuration, and the size and cost of the entire device can be reduced.

According to the second aspect of the present invention, by performing processing based on simpler signals in the comparing means and the counting means, the circuit configuration can be made simpler, and furthermore, The size and cost can be reduced.

According to the third and fifth aspects of the present invention,
The processing result obtained by causing the semiconductor device under test to execute the processing is compared with a preset numerical value, and the value of the comparison signal changes depending on whether or not they match, so that counting is performed according to this change. The quality of the semiconductor device to be tested can be determined by referring to the count value. At this time, it is only necessary to perform down-counting based on the count value output when performing processing by a non-defective semiconductor device, and to detect whether or not down-counting has been performed to, for example, “0”. This can be realized by a simpler circuit configuration, and the size and cost of the entire device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor test apparatus as an embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a conventional semiconductor test apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor test apparatus 2 Timing control part 3 Pattern control part 4 Pattern control part 41 Pattern memory part 42 Formatter 43 Counter 44 Matching circuit 5 Driver / comparator part 6 Driver 7 Comparator 8 DUT

Claims (5)

[Claims] A semiconductor test apparatus which causes a semiconductor device to be tested to execute processing based on a predetermined signal, and judges the quality of the semiconductor device to be tested based on the obtained processing result. A test signal output means for outputting, and a test for causing the semiconductor device under test to execute processing based on the test signal output from the test signal output means, and outputting a voltage value corresponding to the obtained processing result. Means for comparing a voltage value output from the test means with a preset voltage value and outputting a comparison signal indicating a comparison result; and contents of the comparison signal output by the comparison means. A counting means for executing counting and outputting a count value in accordance with the test signal output from the test signal output means. A count value storage unit that stores a count value output from the counting unit when the count value is set, and a count value that compares the count value output from the count unit with the count value stored in the count value storage unit. A semiconductor test apparatus, comprising: comparing means. 2. The comparison means outputs a logical value signal indicating a result of the comparison as a comparison signal, and the counting means counts in synchronization with a change in the comparison signal output from the comparison means. The semiconductor test apparatus according to claim 1, wherein: 3. A semiconductor test apparatus which causes a semiconductor device to be tested to execute processing based on a predetermined signal and judges pass / fail of the semiconductor device to be tested based on the obtained processing result. A test signal output means for outputting, and a test for causing the semiconductor device under test to execute processing based on the test signal output from the test signal output means, and outputting a voltage value corresponding to the obtained processing result. Means for comparing a voltage value output from the test means with a preset voltage value, and outputting a logical value indicating a comparison result as a comparison signal; and A first step of performing a count in response to a change in a comparison signal output from the comparison means when the semiconductor device executes a process, and outputting a count value;
And a comparison signal output from the comparison means, using the count value output from the first counting means as an initial value when the processing of the semiconductor device under test is performed by the testing means. And a judgment result detecting means for detecting whether or not the subtrahend count has been performed to a predetermined value by the second counting means. Semiconductor test equipment. 4. A semiconductor test method in a semiconductor test apparatus, which causes a semiconductor device to be tested to execute processing based on a predetermined signal, and determines the acceptability of the semiconductor device to be tested based on the obtained processing result. Outputting a test signal, causing the semiconductor device under test to execute processing based on the test signal, and outputting a voltage value corresponding to the obtained processing result; and Comparing the voltage with a preset voltage value, outputting a comparison result as a comparison signal, performing a count in accordance with the content of the comparison signal, and processing the non-defective semiconductor device in advance based on the test signal. Storing a count value output when the process is executed, and comparing the stored count value with a count value at the time of termination of processing by the semiconductor device under test. Test method. 5. A semiconductor test method in a semiconductor test apparatus, which causes a test target semiconductor device to execute processing based on a predetermined signal, and determines the acceptability of the test target semiconductor device based on the obtained processing result. Outputting a test signal, causing the semiconductor device under test to execute processing based on the test signal, outputting a voltage value corresponding to the obtained processing result, and setting the voltage value and a preset value. Comparing the output voltage value with the output voltage value, outputting a logical value indicating the comparison result as a comparison signal, and executing a process according to a change in the comparison signal when the non-defective semiconductor device performs processing. When the processing of the semiconductor device under test is executed, the stored count value is used as an initial value, and a countdown is performed in accordance with a change in the comparison signal. There semiconductor test wherein the, for detecting whether or not been executed up to a predetermined value.