JPS6228873B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a testing device for semiconductor integrated circuits (hereinafter referred to as ICs) such as microprocessors or memories, and in particular to an IC test that can easily determine the location of a defect or the type of defect. The aim is to provide equipment.

microprocessor or semiconductor memory, etc.
To test an IC, generally, a test pattern with a predetermined pattern is applied to check whether the IC performs the specified operation or not, and the response output signal to the test pattern is outputted to each terminal pin in an expected value pattern. The system compares the quality of the product and determines whether it is good or bad based on whether it matches or does not match. like this
In IC test equipment, when a failure detection signal (hereinafter referred to as fail data) is issued,
By storing the test pattern applied to the IC and the address signal for reading the test pattern together with fail data for each terminal pin, it is possible to determine the defective location of the IC under test by reading and analyzing the memory. It is convenient. Traditional
In the IC test device, each time the fail data is output, the fail data is sequentially stored in the fail memory.

On the other hand, the above-mentioned test pattern and expected value pattern are read out from the memory constituting the pattern file and given to the IC under test and the comparator. The test pattern and expected value pattern can be read out by repeatedly reading out the test pattern and expected value pattern in a certain section a set number of times, or by repeatedly reading out the test pattern and expected value pattern at the same address a set number of times. It can be done. The former is generally called a pattern loop, and the latter is called a pattern pose. By using such a reading method, the pattern length can be shortened and the storage capacity of the memory constituting the pattern file can be reduced.

If the fail data described above is output in such a pattern loop and pattern pause state, the fail data is output and stored in the fail memory every time the same pattern at the same address is given to the IC, so the memory cannot be stored later. When reading data and analyzing defective parts, it is not possible to determine, for example, how many pattern loops were read out when fail data was output, or how many pattern poses were read out when fail data was output. For this reason, there is a drawback in that it is difficult to analyze defects.

In other words, depending on the degree of failure, fail data may be
When applying the same pattern to a defective part of an IC, it does not necessarily result in an output; in some cases, when the same pattern is applied several times, an output may occur. Therefore, simply storing fail data in the order of occurrence is insufficient as data for failure analysis.

An object of the present invention is to output fail data when a test pattern and an expected value pattern are read out in a pattern loop or pattern pause state. An object of the present invention is to provide an IC testing device that stores information on whether or not a signal has been output, and facilitates failure analysis.

FIG. 1 shows a conventional IC testing device. In the figure, 1 indicates a pattern file in which test patterns and expected value patterns are stored. This pattern file 1 receives an address signal from the program counter 2, and sequentially stores test patterns in a predetermined order.
Pa and the expected value pattern Pb are read out. The read test pattern Pa is supplied to the IC under test 4 through the input waveform shaping circuit 3. The input waveform shaping circuit 3 adjusts the signal level, etc., depending on the type of IC 4 under test, for example.

On the other hand, the expected value pattern Pb read from the pattern file 1 is supplied to the logic comparator 5. This logic comparator 5 has a response output signal of the IC under test 4.
Pc is supplied, and these signals Pb and Pc are compared for each terminal pin to detect coincidence or mismatch. 6 indicates a fail memory. The fail memory 6 has a pattern data file 6a, a fail data file 6b, and an address data file 6c. When fail data Pd is output from the comparator 5, the fail data Pd is stored in the fail data file 6b of the fail memory 6. be remembered. At this time, the test pattern read from pattern file 1 is stored at the same memory address location.
Pa and fail data Pe given to the pattern file 1 from the program counter 2 are stored in the pattern data file 6a and address data file 6c.

Conventionally, each time the fail data Pd is output, the fail data Pd, the test pattern Pa, and the address data Pe are sequentially stored in the fail memory 6. Therefore, when the test pattern of a certain section is repeatedly read out, the If fail data is output within the interval, the fail data Pd is repeatedly stored in the fail memory 6. However, there is no data indicating how many loops or pattern pauses the fail data Pd occurred during reading, making it difficult to analyze the failure.

FIG. 2 shows an embodiment of the invention. In FIG. 2, parts corresponding to those in FIG. 1 are designated by the same reference numerals, and redundant explanation thereof will be omitted. However, in this invention, a part indicated by 7 is added to the IC test device explained in FIG. 1. It is something. This additional part 7 includes an address register 8 that sequentially stores the specified addresses of the pattern file 1, and an address register 8 that stores the addresses stored in this address register 8 and an address counter 2.
an address match detection circuit 9 that compares the address output from the address output from the address match detection circuit 9 and detects a match; a counter 10 that counts the match output of the match detection circuit 9; and a counter 10 that counts the match output of the match detection circuit 9; It can be configured by a test pattern Pa and fail data Pe as well as a frequency data file 6d that is stored at the same address each time the test pattern Pa and fail data Pe are used.

In the present invention, each time a pattern loop command or a pattern pause command is read from the pattern file 1, in the case of a loop command, the address of a specified pattern within the loop, for example, the start address of the loop or the address of a predetermined pattern from the start address, is stored in the address register. Transfer to 8. Further, when a pattern pause command is read, the address of the repeatedly read pattern is transferred to the address register 8.

The address match detection circuit 9 compares this transferred address with the address given to the pattern file 1 from the program counter 2, and each time a match is detected, the match detection output is sent to the counter 10 for counting. By storing the counted value in the data file 6d each time the fail data Pd is output from the comparator 5, the fail memory 6 stores the fail data Pd, the test pattern Pa at that time, the address data Pe, and the pattern loop. The readout count data or pattern pause readout count data Pf can be stored, and this loop or pause readout count data Pf can be read out later as needed together with the fail data Pd to determine the defective part of the IC under test or to identify the defective part. This is effective when analyzing types, etc.

As explained above, according to the present invention, in an IC testing apparatus that is programmed to include a pattern loop or a pattern pause so that the pattern file 1 can be configured using a small capacity memory, When fail data is output, by storing the number of readings of the pattern loop or the number of readings of the pattern pause in the fail memory 6 together with the fail data, failure analysis becomes easy and the type of failure can be determined. It is possible to obtain defect analysis results that are not

In the above description, the fail data Pd, test pattern Pa, fail data Pe, and number of times data Pf are stored in the fail memory 6 every time the fail data Pd is output. However, if the capacity of the fail memory 6 can be increased, the test pattern
The test pattern Pa, data indicating the presence or absence of fail data Pd, address data Pe, number of times data Pf, etc. may all be stored every time Pa is read. Furthermore, if the capacity of the fail memory 6 is limited, fail data etc. may be stored in the fail memory 6 only for a predetermined address section of the pattern file 1.
The selection is arbitrary.

In addition, in the above example, the test pattern is stored in fail memory 6.
Although a case has been described in which Pa is stored, it is also possible to appropriately select and store a test pattern and an expected value pattern, for example.

[Brief explanation of the drawing]

FIG. 1 is a system diagram for explaining a conventional IC testing device, and FIG. 2 is a system diagram showing an embodiment of the present invention. 1: Pattern file, 2: Program counter, 4: IC under test, 5: Comparator, 6: Fail memory, 8: Address register, 8: Address match detection circuit, 10: Counter, 6d: Number of times data memory.

Claims (1)

[Claims] 1 A pattern file containing test patterns and expected value patterns and a test pattern read from the pattern file are given to the IC under test, and a comparison is made in which the response output from the IC is compared with the above expected value pattern. The above test pattern is repeatedly read out in an IC test device having a fail memory that stores the fail data, address data given to the pattern file at that time, and the test pattern when fail data is generated in the comparison output. A register that stores a certain specified address of the program, an address match detection circuit that compares the address set in the register with the address of the test pattern and detects a match, and counts the number of match outputs of the detection circuit. An IC testing device comprising a counter and a count data file whose count value of the counter is stored at an address corresponding to the fail data stored in the fail memory.