KR19990006173A - Test device and method of semiconductor memory device - Google Patents

Abstract

The present invention relates to a test apparatus for a semiconductor device, and more particularly, a function for masking a failed address during a probe test is added to a tester of a semiconductor device that performs pass / fail determination and stores a fail address in a fail memory. A test apparatus and method for a semiconductor memory device.

The present invention provides sense control means for checking whether a bit fails with respect to an address of a memory to be tested and skipping a failed address without performing a test; A low address fail checking unit for checking a fail generation of a row address by inputting an output of the sense control means and a row address; A column address fail check unit for checking a failure of a column address by inputting an output of the sense control means and a column address; A storage unit for storing a fail address of a final test by inputting a row and column address and a failed address of bits for a current test item from the row and column address fail check unit; And a fail generation signal output unit configured to input a row and column address fail detection signal output from the row and column address fail check unit and output a fail generation signal to the sense control means.

Description

Test device and method of semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus for a semiconductor device, and more particularly, to a tester of a semiconductor device that performs pass / fail determination and stores a fail address in a fail memory, wherein a function of masking a failed address during a probe test is added. A test device for a memory device.

Referring to FIG. 1, a general test and repair operation will be described. First, when fabrication of a semiconductor memory device is completed (FAB out) (S10), a wafer burn-in test is performed by applying dynamic stress (S20). Subsequently, a probe test is performed (S30) to generate first MRD (Memory Refair Data) data and SDA data (S300).

Subsequently, the long cycle test is performed (S40) to identify the wafer deterioration, the second MRD data is generated (S400), and the repair operation is performed (S50). The first MRD file and the long cycle of the probe test are then performed. After reading the 2nd MRD file of the test and writing it to the fail address memory, the software suitable for the device repair algorithm is started to generate the final repair MRD file (S500), and the monitored wafer is monitored (S60). ).

However, the conventional test method as described above allows the repairable die to be sorted as a non-repairable die when generating the final repair MRD data in step S500.

Further, in the long cycle test, since the long cycle test is performed with a plurality of items, it is possible to store information about repairability and impossibility only when configuring a fail memory having a larger capacity than the memory device under test.

As a result, a large amount of fail memory is required, which increases test cost and makes long cycle testing difficult.

The present invention is to solve the above problems, by masking the failed address in row and column unit in the previous test during the probe test and long cycle test, it is possible to test even in a low-capacity fail memory SUMMARY OF THE INVENTION An object of the present invention is to provide a test method and apparatus for a semiconductor memory device capable of obtaining fail address information in a current test by storing only an address value failed in a current test.

1 is a flowchart illustrating a test and repair method of a general semiconductor memory device.

2 is a circuit diagram of a test apparatus for a semiconductor memory device to which a fail address mask function is added according to an exemplary embodiment of the present invention.

Explanation of symbols for the main parts of the drawings

10, 10 ': address fail count memory

20, 20 ', 30, 30': mask memory

40, 40 ': Fail counter part 50, 50': Register

60, 60 ': comparison means 70: sense control means

100: fail memory 200: address counter

1: Low address fail check part 2: Column address fail check part

3: Storage unit 4: Fail generation signal output unit

OR1, OR1 ', OR2, OR2', OR3: Ora gate

In order to achieve the above object, the present invention provides a device for testing a semiconductor memory device for determining a pad / fail and storing a fail address by testing a semiconductor device, and at the same time checking whether a bit fails with respect to the address of the memory to be tested. Sense control means for skipping a failed address without testing it; A low address fail checking unit for checking a fail generation of a row address by inputting an output of the sense control means and a row address; A column address fail check unit for checking a failure of a column address by inputting an output of the sense control means and a column address; A storage unit for storing a fail address of a final test by inputting a row and column address and a failed address of bits for a current test item from the row and column address fail check unit; And a fail generation signal output unit configured to input a low and column address fail detection signal output from the row and column address fail check unit to output a fail generation signal to the sense control means. do.

In an embodiment of the present invention, the low address fail checking unit comprises: a row address fail count memory for storing the number of bits of a failed address currently being tested; A first low line mask memory for storing whether a bit fails for an item currently being tested during a long cycle test; A second low line mask memory that stores information about an address failed from an MRD file as a previous test result; Address path / fail determination means for inputting a failed address of the low address fail count memory to determine a fail and a path of an address by an output signal of the sense control means; And fail detection means for inputting the outputs of the first and second row mask memories to detect a low address fail.

The address path / fail determining means comprises: a register for storing a maximum number of occurrences of fail bits for an address; A line fail counter unit configured to increase the number of failed bits by inputting a fail bit generation signal of the sense control unit; And a comparison means for outputting a bit fail signal to the first low line mask memory by comparing a value of the register with a value of a line fail counter unit, and the address fail detection unit of the first and second low mask memories. It is composed of an OR gate that inputs an output and generates a low address fail detection signal.

In an embodiment of the present invention, the column address fail checking unit comprises: a column address fail count memory for storing the number of bits of the failed address currently being tested; A first column line mask memory for storing whether a bit for an item currently being tested is failed during a long cycle test; A second column line mask memory that stores information about an address failed from an MRD file as a result of a previous test; Address path / fail determination means for inputting a failed address of the column address fail count memory to determine a fail and a path of an address by an output signal of the sense control means; And fail detection means for detecting a column address failure by inputting the outputs of the first and second column mask memories.

The address path / fail determining means comprises: a register for storing a maximum number of occurrences of fail bits for an address; A line fail counter unit configured to increase the number of failed bits by inputting a fail bit generation signal of the sense control unit; And a comparison means for comparing a value of the register with a value of a line fail counter and outputting a bit fail signal to the first column line mask memory, wherein the address fail detection unit is configured to include the first and second column mask memories. It is composed of an OR gate that inputs an output and generates a low address fail detection signal.

In an exemplary embodiment of the present invention, the fail address storage unit may include an OR gate for inputting a signal from the row and column address fail check units; An address counter for incrementing an address by the output of the OR gate; And a fail address memory configured to input an output of the address counter to store the address value of the failed address and output the same for monitoring, wherein the fail generation signal output unit inputs the row and column address fail detection signals to receive a fail generation signal. Ora gate output to the detection control means.

In addition, the present invention provides a tester method for a semiconductor memory device for performing a pass / fail determination through a test of a semiconductor memory device and storing a fail address in a fail memory, the method comprising: initializing; Storing the failed address obtained up to the probe test operation; Performing a long cycle test by inputting an address, skipping a test on an address stored as a fail address until a probe test, and performing a test on a bit of a passed address; Determining a pass / fail of an address depending on a frequency of occurrence of a fail bit in a test of performing the test; A method of testing a semiconductor memory device, the method comprising: storing only a failed address in a fail memory as a result of determining a pass / fail of the address.

EXAMPLE

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a test apparatus for a semiconductor memory device having a fail address mask function according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the test apparatus of the semiconductor memory device of the present invention checks whether a bit fails with respect to an address of a memory to be tested and senses the skipped address without performing a test on the failed address. And a low address fail check unit 1 for inputting an output of the sense control means 70 and a row address to check a failure of a row address, and an output and a column address of the sense control means 70. Inputs the failed address of the bit for the current test item from the column address fail check unit 2 and the row and column addresses and the row and column address fail check units 1 and 2 to check the occurrence of the failure of the column address. A storage unit 3 for storing a fail address of a final test and the row and column address check unit ( And a fail generation signal output unit 4 for inputting the row and column address fail detection signals outputted from 1 and 2 and outputting a fail generation signal to the sense control means 70.

The low address fail check unit 1 stores a row address fail count memory 10 for storing the number of bits of a failed address to be tested currently, and whether or not to fail a bit for an item to be tested during a long cycle test. A first low line mask memory 20 for storing a second low line mask memory 30 for storing information on an address failed from an MRD file as a result of a previous test, and the low address fail count memory 10. Address path / fail determination means for determining a fail and path of an address by an output signal of the sense control means 70 by inputting a failed address and output of the first and second row mask memories 20 and 30. And a fail detection means composed of an OR gate, which detects a low address fail by input.

The address path / fail determining means inputs a register 50 for storing the maximum number of occurrences of fail bits for an address and a fail bit generation signal of the sense control means 70 to increase the number of failed bits. Comparison means for outputting a bit fail signal to the first low line mask memory 20 by comparing a value of the line fail counter unit 40 with the value of the register 50 and the value of the line fail counter unit 40. It consists of 60.

The column address fail check unit 2 is configured similarly to the low address fail check unit 1 and operates in the same manner.

The fail address storage unit 3 includes an OR gate OR3 for inputting an output of the comparison means 60 and 60 'of the row and column address fail check units 1 and 2, and an output of the OR gate OR3. And an address counter 200 for incrementing an address, and a fail address memory 100 for inputting the output of the address counter 200 to store the address value of the failed address and output the same for monitoring.

The fail generation signal output unit 4 inputs an output of the OR gates OR1 and OR1 'generating the row and column address fail detection signals, and outputs a fail generation signal to the sensing control means 70. (OR4 ').

Referring to the operation of the test apparatus having the configuration as described above, the operation before the long cycle is the same as in the prior art.

After starting the long cycle test to clear the row and column line fail counter memories 10 and 10 ', the first row and column line mask memories 20 and 20' and the line fail counters 40 and 40 '. The registers 50 and 50 'are set to predetermined values. The second low line mask memory 30 then stores the MRD data for the address previously determined to fail.

When the row address is applied, a signal corresponding to the address is output from the first and second row line mask memories 20 and 30 and input to the first OR gate OR1. In addition, when a column address is applied, a signal corresponding to the address is output from the first and second column line mask memories 20 'and 30' and input to the second OR gate OR2.

At this time, when the output of the second row and column mask memory 30 is 1, that is, when the previous test result is the fail address, the outputs of the OR gates OR1 and OR1 'are 1, and the OR gate OR1 of the high state is OR1. Or OR1 ') is applied to the sense control means 70 through the OR gate OR2, so the sense control means 70 tests the next address by skipping the address applied to the memory to be tested. .

On the other hand, if the output of the second row and column line mask memory 30 is zero, that is, the previous test result is not the fail address, the output of the OR gates OR1 and OR1 'is zero.

First, assuming that no failure occurs with respect to the column address, the output of the second OR gate OR2 is zero and is applied to the sense control 70. At this time, the sense control 70 starts to test a bit corresponding to the input address of the memory to be tested to check whether a failure occurs and generate fail data for the fail address.

When a failure occurs, the line fail counter unit 40 is counted up by applying the count up signal of the line fail counter unit 40. The fail generation check is repeatedly performed and the line fail counter is turned up whenever a bit is generated.

On the other hand, the output of the line fail counter unit 40 is stored in the line fail count memory 10 and is applied to the first input terminal A of the comparing means 60. The comparison means 60 outputs the state 1 only when the value of the first input terminal A, that is, the line fail counter 40 is large, compared with the value stored in the register 50 input through the second input terminal B. FIG. (S5)

The output of the comparison means 60 is applied to the node A, applied to the first OR gate OR1, and stored in the first low line mask memory 20. Since the value of the first low line mask memory 20 is 1, the sense control 70 stops the test and skips the current address to check the next address.

At the same time, in the fail address storage unit 3, the output of the OR gate OR3 becomes 1 when the values of the first row mask memory 20 and the first column mask memory 20 'are set to 1. The address counter 200 is counted up. Since the failed address value of the memory currently tested is recorded in the fail address memory designated by the output value of the address counter 200, the address failed in the current test is stored in the fail memory.

Even if a fail has not occurred in the column address, the operation is performed in the same manner as described above, and the present invention repeats the operation as described above and performs the test while increasing the address.

Thereafter, the row and column line fail counter memories 10 and 10 'and the line fail counter 40 are cleared to perform the long cycle test of other items, and the same operation is performed. When the final test is completed, information about the address that is failed in the long cycle test is input to the fail memory.

As a result, an address determined to fail in a previously performed test is written to the address mask memory and thus is not tested in the current test. Only the address value failed in the current test is stored in the fail address memory. Information about the fail address generated in the test can be obtained.

According to the present invention as described above, by adding a predetermined hardware for masking the failed address to the existing tester, the failed address is masked in the probe test so as not to be tested in the long cycle test. As a result, the MRD data generated during the probe test and the MRD data generated during the long cycle test are mixed to solve a problem of determining whether repair is possible or not.

In addition, the fail address memory needs only a space for storing only the failed addresses in the long cycle test. In the long cycle test for testing a plurality of items, the fail address memory requires a plurality of items at a lower price than the conventional one. Enable long cycle test for.

Claims (10)

A test apparatus for a semiconductor memory device for testing a semiconductor device and determining pass / fail and storing a fail address, Sense control means for checking whether a bit fails with respect to an address of a memory to be tested and skipping a failed address without a test; A low address fail checking unit for checking a fail generation of the row address by using the output of the sense control means and the row address as an input signal; A column address fail check unit for checking a failure of a column address by inputting an output of the sense control means and a column address; A storage unit for storing a fail address of a final test by inputting a row and column address and a failed address of bits for a current test item from the row and column address fail check unit; And a fail generation signal output unit configured to input a row and column address fail detection signal output from the row and column address fail check unit to output a fail generation signal to the sense control means. The method of claim 1, wherein the low address fail check unit A row address fail count memory for storing the number of bits of the failed address currently being tested; A first low line mask memory for storing whether a bit fails for an item currently being tested during a long cycle test; A second low line mask memory that stores information about an address failed from a previous test result; Address path / fail determination means for inputting a failed address of the low address fail count memory to determine a fail and a path of an address by an output signal of the sense control means; And fail detection means for inputting the outputs of the first and second low mask memories to detect a low address fail. The method of claim 2, wherein the address path / fail determination means A register that stores a maximum number of occurrences of fail bits for one address; A line fail counter unit configured to increase the number of failed bits by inputting a fail bit generation signal of the sense control unit; And a comparison means for comparing a value of the register with a value of a line fail counter and outputting a bit fail signal to the first low line mask memory. 3. The test apparatus of claim 2, wherein the address fail detection unit comprises an OR gate for inputting outputs of the first and second low mask memories to generate a low address fail detection signal. The method of claim 1, wherein the column address fail check unit A column address fail count memory for storing the number of bits of the failed address currently being tested; A first column line mask memory for storing whether a bit for an item currently being tested is failed during a long cycle test; A second column line mask memory that stores information about the failed address as a previous test result; Address path / fail determination means for inputting a failed address of the column address fail count memory to determine a fail and a path of an address by an output signal of the sense control means; And fail detection means for inputting outputs of the first and second column mask memories to detect column address failures. The method of claim 5, wherein the address path / fail determination means A register that stores a maximum number of occurrences of fail bits for one address; A line fail counter unit configured to increase the number of failed bits by inputting a fail bit generation signal of the sense control unit; And a comparison means for comparing a value of the register with a value of a line fail counter and outputting a bit fail signal to the first column mask mask memory. 6. The test apparatus of claim 5, wherein the address fail detection unit comprises an OR gate for inputting outputs of the first and second column mask memories to generate a low address fail detection signal. The method of claim 1, wherein the fail address storage unit An OR gate for inputting a signal from the row and column address fail check units; An address counter for incrementing an address by the output of the OR gate; And a fail address memory configured to input an output of the address counter to store the address value of the failed address and output the same for monitoring. The test apparatus of claim 1, wherein the fail generation signal output unit comprises an OR gate for inputting the row and column address fail detection signals to output the fail generation signal to the detection control means. In the test method of the semiconductor memory device to pass / fail determination through the test of the semiconductor memory device and to store the fail address in the fail memory, Initializing; Storing the failed address obtained up to the probe test operation; Skipping the test for the address stored as the fail address until the probe test by inputting the address, and performing a test on the bit of the passed address; Determining a pass / fail of an address depending on a frequency of occurrence of a fail bit in a test of performing the test; And storing only the failed addresses in the fail memory as a result of determining the pass / fail of the address.