JPH11306752A - Electronic circuit device for mixedly mounting dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve standby operation in an electronic circuit device where a DRAM requiring refresh operation is mixedly mounted, and at the same time to obtain the electronic circuit device that can reduce power consumption. SOLUTION: An electronic circuit device has a power supply selection circuit 14. The power supply selection circuit 14 changes main and sub power supplies on normal operation and standby, respectively, for supplying to an electronic circuit where a refreshing circuit 13 for refreshing a DRAM 11, a logic circuit 12, and a DRAM is mixedly mounted, and at the same time supplies the main power supply to at least the refreshing circuit 13 on the standby. On the standby of the electronic circuit device, the sub power supply is supplied to the electronic circuit by the power supply selection circuit 14. Also, only on the refreshing of the standby, the main power supply is supplied to at least the refreshing circuit 13, thus securing the refreshing of the DRAM 1 on the standby, achieving standby operation in the electronic circuit device where the DRAM is mixedly mounted, and hence reducing the power consumption of the entire electronic circuit device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic circuit device incorporating a DRAM (Dynamic Random Access Memory), and more particularly, to an electronic circuit device capable of reducing power consumption in an electronic circuit device capable of setting a standby state. Related to the device.

[0002]

2. Description of the Related Art In recent electronic circuit devices, in order to reduce power consumption during standby when the system is not operated, it is necessary to switch from a large current main power supply to a small current sub-power supply during standby to be in a standby state. The configuration is such that only the circuit is driven. In order to realize this, a power supply selection circuit is provided between the internal circuit of the electronic circuit device and the power supply circuit, and the power supply selection circuit switches between the main power supply and the sub power supply based on a standby signal that is turned on at the time of standby. It is configured to be connected to a circuit.

[0003]

However, in an electronic circuit device in which a DRAM is mounted as a storage device for storing various data, as is well known, refresh for holding data stored in the DRAM is required. In order to perform this refresh, it is necessary to supply the current of the main power supply to the refresh circuit. For this reason, in this type of electronic circuit device, at the time of standby, at least the state in which the main power supply is connected to the refresh circuit as in normal operation must be maintained, which is an obstacle to reducing power consumption. ing.

An object of the present invention is to provide an electronic circuit device which realizes a standby operation in such an electronic circuit device in which a DRAM is embedded and which can reduce power consumption.

[0005]

According to the present invention, there is provided an electronic circuit device including a DRAM and a refresh circuit for refreshing the DRAM as a part of a plurality of electronic circuits constituting the electronic circuit device. A power supply selection circuit that switches a power supply between a normal operation and a standby state; and the power supply selection circuit supplies a main power supply to the electronic circuit by switching a main power supply during a normal operation and a sub power supply during a standby state. In addition, at the time of standby, at least the refresh circuit is supplied to the main power supply.

As a first configuration, the power supply selection circuit can select one of a main power supply and a sub power supply, and receives a standby signal to select a sub power supply, and the first switch circuit; A second switch circuit that can select one of a circuit selection output and a main power supply, and selects a main power supply in response to a refresh timing signal; and supplies a selection output of the second switch circuit to the electronic circuit. It is configured as follows. Further, as a second configuration, a first switch circuit that can select either a main power supply or a sub power supply and selects a sub power supply in response to a standby signal, a selection output of the first switch circuit, and a main power supply And a second switch circuit that selects a main power supply in response to a refresh timing signal, and supplies a selected output of the second switch circuit to the refresh circuit, the first switch circuit Is supplied to an electronic circuit other than the refresh circuit.

In the present invention, when the electronic circuit device is on standby, the sub-power is supplied to the electronic circuit by the power supply selection circuit, thereby reducing power consumption. Only at the time of refreshing during standby, the power supply selecting circuit receives the refresh timing signal and supplies at least the main power to the refreshing circuit, thereby enabling refreshing.
A standby operation in an electronic circuit device including a DRAM is realized, and power consumption of the entire electronic circuit device is reduced.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block circuit diagram of a first embodiment of the present invention. In this embodiment, the present invention is applied to an electronic circuit device in which a DRAM 11 for storing data and a logic circuit unit 12 for performing a required logical operation based on the stored data are mounted as the electronic circuit device. An example is shown. The DRAM 11 is connected to a refresh circuit 13 for performing a refresh for holding stored data.
2 and the refresh circuit 13 share a common internal power line V
1 is connected to the power supply selection circuit 14. The refresh circuit 13 is connected to a refresh signal output circuit 15 for supplying various signals for refreshing, for example, a CAS signal and a RAS signal. The refresh signal output circuit 15 includes at least a clock generation circuit 16 and a counter 17 that counts clock signals generated by the clock generation circuit 16 and outputs a refresh timing signal.

The power supply selection circuit 14 has first and second power supply selection circuits.
Switch circuits SW1 and SW2 are built in, and a main power supply and a sub power supply are selected by these switch circuits so that they can be connected to the internal power supply line V1. The first switch circuit SW1 is configured as a switch circuit for selectively switching between a main power supply and a sub power supply, and is switched by a standby signal SST which is set to a high level during standby. Further, the second switch circuit SW2 is configured as a switch circuit for switching off the selection output of the first switch circuit SW1 and the main power supply, and is output from the refresh signal output circuit 15 and set to a high level at the time of refresh. The switching operation is performed by the refresh timing SRT signal.

The operation of the first embodiment will be described with reference to the timing chart of the operation shown in FIG. During a normal operation in which the standby signal SST is at a low level, the first switch circuit SW1 is connected to the main power supply. Therefore, regardless of the switching state of the second switch circuit SW2, the current from the main power supply is always supplied to the internal power supply line V0, and the normal operation of the refresh circuit 13 and the logic circuit unit 12 is ensured. You. When the standby signal SST goes high, the first switch circuit SW1
Is switched to the sub power supply side. At this time, when the refresh timing signal SRT is not input, since the second switch circuit SW2 is connected to the sub power supply side, the current from the sub power supply is supplied to the internal power supply line V0, and the refresh circuit 13 and logic circuit unit 1
2 is in a standby state, and power consumption in the logic circuit unit 12 and the refresh circuit 13 is reduced. When the refresh timing signal SRT from the refresh signal output circuit 15 goes high and is supplied to the second switch circuit SW2, the second switch circuit SW2 is switched to the main power supply side. Therefore, the current from the main power supply is supplied to the internal power supply line V0, and the DRAM 11 in the refresh circuit 13
Can be refreshed. At this time, the logic circuit unit 1
2, the current of the main power supply is also supplied. For example, if a circuit configuration for stopping the operation of the logic circuit unit 12 by the standby signal SST is used, a substantial increase in power consumption in the logic circuit unit 12 can be suppressed. Is possible.

As described above, in the first embodiment, the refresh circuit 13 and the logic circuit unit 1 are in standby mode.
2, the main power is supplied to the refresh circuit 13 and the logic circuit unit 12 at the time of refreshing during standby, so that the refresh operation of the DRAM 11 can be ensured and data loss is prevented. This makes it possible to reduce power consumption at least during times other than refreshing.

FIG. 3 is a block circuit diagram of a second embodiment of the present invention. Also in the second embodiment, a DRAM 11 for storing data is used as an electronic circuit device.
An example is shown in which the present invention is applied to an electronic circuit device in which a logic circuit unit 12 for performing a required logical operation based on stored data is mounted. The DRAM 11 includes:
A refresh circuit 13 for performing refresh for holding stored data is connected, and is connected to a power selection circuit 14 via a first internal power line V1. Further, the logic circuit section 12 includes a second internal power supply line V
2 is connected to the power supply selection circuit 14. Further, a refresh signal output circuit 15 for outputting a refresh timing signal SRT is provided.

The power supply selection circuit 14 has first and second
Switch circuits SW1 and SW2 are built in, so that a main power supply and a sub power supply can be selected by these switch circuits and connected to the first and second internal power supply lines V1 and V2. The first switch circuit SW1 is configured as a switch circuit for selectively switching between a main power supply and a sub power supply, and is switched by a standby signal SST which is set to a high level during standby. Further, the second switch circuit SW2 is configured as a switch circuit for switching and selecting the selected output of the first switch circuit SW1 and the main power supply, and is switched by a refresh timing signal SRT which is set to a high level at the time of refresh. It is configured to: The configuration of the first and second switch circuits SW1 and SW2 is the first
Although the second embodiment is the same as the second embodiment,
The selection output of the second switch circuit SW2 is connected to the first internal power supply line V1, and the first switch circuit S2
The selected output of W1 is connected to the second internal power supply line V2.

The operation of the second embodiment will be described with reference to the timing chart of the operation shown in FIG. During a normal operation in which the standby signal SST is at a low level, the first switch circuit SW1 is connected to the main power supply. Therefore, regardless of the switching state of the second switch circuit SW2, the current from the main power supply is supplied to the first internal power supply line V1 and the second internal power supply line V2, respectively.
Normal operations in the refresh circuit 13 and the logic circuit unit 12 are ensured. When the standby signal SST becomes high level, the first switch circuit SW1 is switched to the sub power supply side. At this time, when the refresh timing signal SRT is not input, the second switch circuit SW
2 is connected to the sub power supply side, the current from the sub power supply is supplied to the first internal power supply line V1, and at the same time, the second internal power supply line V2 is supplied by the first switch circuit SW1.
Is supplied with a current from the sub-power supply, the refresh circuit 13 and the logic circuit unit 12 are in a standby state, and power consumption in the electronic circuit device is reduced.
Then, when the refresh timing signal SRT from the refresh signal output circuit 15 becomes high level and is supplied to the second switch circuit SW2, the second switch circuit SW2 is switched to the main power supply side. Therefore, the current from the main power supply is supplied to the first internal power supply line V1, and the DRA in the refresh circuit 13
M11 can be refreshed. At this time, the first switch circuit SW1 outputs the refresh timing signal SRT
Does not change, the second internal power supply line V2 remains in the state where the current of the sub power supply is supplied, and the logic circuit unit 12 is continuously held in the standby state. An increase in power consumption in the unit 12 is suppressed.

Therefore, in the second embodiment,
At the time of standby, the sub-power is supplied to the refresh circuit 13 and the logic circuit unit 12, while at the time of refresh during standby, the main power is supplied only to the refresh circuit 13, so that the refresh operation of the DRAM 11 can be ensured, and the data loss. Is prevented. This makes it possible to reduce power consumption at least at times other than refreshing. In the second embodiment, the power consumption of the logic circuit unit 12 at the time of refreshing is reduced as compared with the first embodiment. It is also possible to achieve.

In each of the above embodiments, the first and second switch circuits are shown as switching contact type switches in FIGS. 1 and 3, but this switch circuit is composed of elements such as transistors. Electronic switch,
Alternatively, it is needless to say that the logic gate switch may be constituted by a combination of logic gates. Further, as the refresh timing signal,
Although not particularly limited, it is also possible to use various signals used in a conventional refresh operation.

[0017]

As described above, the present invention relates to a DRAM.
A main power supply is switched to a main power supply for normal operation and a sub power supply is switched and supplied to the electronic circuit in which a refresh circuit for refreshing the DRAM is mounted in standby mode, and at least a main power supply is supplied to the refresh circuit in standby mode. A sub-power supply to the electronic circuit by the power supply selection circuit when the electronic circuit device is on standby, and a main power supply to at least the refresh circuit only when the standby circuit is refreshed. Is supplied, the DRA during standby
While ensuring the refresh of M, the standby operation in the electronic circuit device mixed with the DRAM is realized, and the power consumption of the entire electronic circuit device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the first embodiment.

FIG. 3 is a block circuit diagram according to a second embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of the second embodiment.

[Explanation of symbols]

 Reference Signs List 11 DRAM 12 Logic circuit section 13 Refresh circuit 14 Power supply selection circuit 15 Refresh signal output circuit 16 Clock generation circuit 17 Counter circuit SW1 First switch circuit SW2 Second switch circuit V0 Internal power supply line V1 First internal power supply line V2 First 2 internal power lines

Claims (3)

[Claims] 1. An electronic circuit device in which a DRAM and a refresh circuit for refreshing the DRAM are mounted as a part of an electronic circuit constituting the electronic circuit device, a power supply to the electronic circuit is supplied during a normal operation and a standby time. And a power supply selection circuit that switches between a main power supply for normal operation and a sub power supply during standby for the electronic circuit, and at least to the refreshment circuit during standby. An electronic circuit device with embedded DRAM, wherein the electronic circuit device is configured to supply power to a main power supply. 2. The power supply selection circuit can select one of a main power supply and a sub power supply, receives a standby signal and selects a sub power supply, and a selection output of the first switch circuit. A second switch circuit that can select one of the main power supplies and selects a main power supply in response to a refresh timing signal, and is configured to supply a selection output of the second switch circuit to the electronic circuit. 2. The DRAM hybrid electronic circuit device according to claim 1, wherein: 3. The power supply selection circuit can select either a main power supply or a sub power supply, receives a standby signal and selects a sub power supply, and a selection output of the first switch circuit. A second switch circuit that can select one of the main power supplies and selects a main power supply in response to a refresh timing signal, and supplies a selection output of the second switch circuit to the refresh circuit;
2. The DRAM hybrid electronic circuit device according to claim 1, wherein the selected output of the first switch circuit is supplied to an electronic circuit other than the refresh circuit.